#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "bus_pci.h"
#include "console.h"
#include "cpu.h"
#include "device.h"
#include "devices.h"
#include "interrupt.h"
#include "machine.h"
#include "memory.h"
#include "misc.h"
#include "sh4_dmacreg.h"
#include "timer.h"
#include "thirdparty/sh4_bscreg.h"
#include "thirdparty/sh4_cache.h"
#include "thirdparty/sh4_exception.h"
#include "thirdparty/sh4_intcreg.h"
#include "thirdparty/sh4_mmu.h"
#include "thirdparty/sh4_pcicreg.h"
#include "thirdparty/sh4_rtcreg.h"
#include "thirdparty/sh4_scifreg.h"
#include "thirdparty/sh4_scireg.h"
#include "thirdparty/sh4_tmureg.h"
Go to the source code of this file.
Classes | |
struct | sh4_data |
Macros | |
#define | SH4_REG_BASE 0xff000000 |
#define | SH4_TICK_SHIFT 14 |
#define | N_SH4_TIMERS 3 |
#define | N_PCIC_REGS (0x224 / sizeof(uint32_t)) |
#define | N_PCIC_IRQS 16 |
#define | PCIC_REG(addr) ((addr - SH4_PCIC) / sizeof(uint32_t)) |
#define | PCI_VENDOR_HITACHI 0x1054 |
#define | PCI_PRODUCT_HITACHI_SH7751 0x3505 |
#define | PCI_PRODUCT_HITACHI_SH7751R 0x350e |
#define | SCIF_TX_FIFO_SIZE 16 |
#define | SCIF_DELAYED_TX_VALUE 2 /* 2 to be safe, 1 = fast but buggy */ |
#define | SH4_CPG_FRQCR 0xffc00000 /* 16-bit */ |
#define | SH4_CPG_STBCR 0xffc00004 /* 8-bit */ |
#define | SH4_CPG_WTCNT 0xffc00008 /* 8/16-bit */ |
#define | SH4_CPG_WTCSR 0xffc0000c /* 8/16-bit */ |
#define | SH4_CPG_STBCR2 0xffc00010 /* 8-bit */ |
#define | SH4_PSEUDO_TIMER_HZ 110.0 |
Functions | |
DEVICE_TICK (sh4) | |
void | sh4_dmac_transfer (struct cpu *cpu, struct sh4_data *d, int channel) |
DEVICE_ACCESS (sh4_itlb_aa) | |
DEVICE_ACCESS (sh4_itlb_da1) | |
DEVICE_ACCESS (sh4_utlb_aa) | |
DEVICE_ACCESS (sh4_utlb_da1) | |
DEVICE_ACCESS (sh4_pcic) | |
DEVICE_ACCESS (sh4_sq) | |
DEVICE_ACCESS (sh4) | |
DEVINIT (sh4) | |
#define N_PCIC_IRQS 16 |
Definition at line 74 of file dev_sh4.cc.
#define N_PCIC_REGS (0x224 / sizeof(uint32_t)) |
Definition at line 73 of file dev_sh4.cc.
#define N_SH4_TIMERS 3 |
Definition at line 70 of file dev_sh4.cc.
#define PCI_PRODUCT_HITACHI_SH7751 0x3505 |
Definition at line 77 of file dev_sh4.cc.
#define PCI_PRODUCT_HITACHI_SH7751R 0x350e |
Definition at line 78 of file dev_sh4.cc.
#define PCI_VENDOR_HITACHI 0x1054 |
Definition at line 76 of file dev_sh4.cc.
Definition at line 75 of file dev_sh4.cc.
#define SCIF_DELAYED_TX_VALUE 2 /* 2 to be safe, 1 = fast but buggy */ |
Definition at line 81 of file dev_sh4.cc.
#define SCIF_TX_FIFO_SIZE 16 |
Definition at line 80 of file dev_sh4.cc.
#define SH4_CPG_FRQCR 0xffc00000 /* 16-bit */ |
Definition at line 89 of file dev_sh4.cc.
#define SH4_CPG_STBCR 0xffc00004 /* 8-bit */ |
Definition at line 90 of file dev_sh4.cc.
#define SH4_CPG_STBCR2 0xffc00010 /* 8-bit */ |
Definition at line 93 of file dev_sh4.cc.
#define SH4_CPG_WTCNT 0xffc00008 /* 8/16-bit */ |
Definition at line 91 of file dev_sh4.cc.
#define SH4_CPG_WTCSR 0xffc0000c /* 8/16-bit */ |
Definition at line 92 of file dev_sh4.cc.
#define SH4_PSEUDO_TIMER_HZ 110.0 |
Definition at line 177 of file dev_sh4.cc.
#define SH4_REG_BASE 0xff000000 |
Definition at line 68 of file dev_sh4.cc.
#define SH4_TICK_SHIFT 14 |
Definition at line 69 of file dev_sh4.cc.
DEVICE_ACCESS | ( | sh4 | ) |
Definition at line 967 of file dev_sh4.cc.
References BCR1_LITTLE_ENDIAN, sh4_data::bsc_bcr1, sh4_data::bsc_bcr2, sh4_data::bsc_bcr3, sh4_data::bsc_gpioic, sh4_data::bsc_mcr, sh4_data::bsc_pcr, sh4_data::bsc_rfcr, sh4_data::bsc_rtcor, sh4_data::bsc_rtcsr, sh4_data::bsc_wcr1, sh4_data::bsc_wcr2, sh4_data::bsc_wcr3, cpu::byte_order, sh_cpu::ccr, cpu::cd, CHCR_CHSET, CHCR_TD, sh_cpu::cpu_type, data, debug, sh_cpu::dmac_chcr, sh_cpu::dmac_dar, sh_cpu::dmac_sar, sh_cpu::dmac_tcr, sh_cpu::dmaor, DMAOR_DDT, DMAOR_DME, DMAOR_PR0, DMAOR_PR1, EMUL_LITTLE_ENDIAN, sh_cpu::expevt, fatal(), INTERRUPT_DEASSERT, sh_cpu::intevt, INVALIDATE_ALL, cpu::invalidate_translation_caches, sh_cpu::itlb_lo, MEM_READ, MEM_WRITE, memory_readmax64(), sh_cpu::mmucr, sh_cpu::pclock, sh4_data::pctra, sh4_data::pctrb, sh4_data::pdtra, sh4_data::pdtrb, sh_cpu_type_def::prr, sh_cpu::ptea, sh_cpu::pteh, sh_cpu::ptel, sh_cpu_type_def::pvr, sh_cpu::qacr0, sh_cpu::qacr1, RTCSR_CMF, sh4_data::sdmr2, sh4_data::sdmr3, cpu::sh, SH4_BCR1, SH4_BCR2, SH4_BCR3, SH4_CCR, SH4_CHCR0, SH4_CHCR1, SH4_CHCR2, SH4_CHCR3, SH4_CHCR4, SH4_CHCR5, SH4_CHCR6, SH4_CHCR7, SH4_DAR0, SH4_DAR1, SH4_DAR2, SH4_DAR3, SH4_DAR4, SH4_DAR5, SH4_DAR6, SH4_DAR7, sh4_dmac_transfer(), SH4_DMAOR, SH4_DMATCR0, SH4_DMATCR1, SH4_DMATCR2, SH4_DMATCR3, SH4_DMATCR4, SH4_DMATCR5, SH4_DMATCR6, SH4_DMATCR7, SH4_EXPEVT, SH4_GPIOIC, SH4_INTEVT, SH4_MCR, SH4_MMUCR, SH4_MMUCR_TI, SH4_PCR, SH4_PCTRA, SH4_PCTRB, SH4_PDTRA, SH4_PDTRB, SH4_PRR_ADDR, SH4_PTEA, SH4_PTEH, SH4_PTEH_ASID_MASK, SH4_PTEL, SH4_PTEL_V, SH4_PVR_ADDR, SH4_QACR0, SH4_QACR1, SH4_REG_BASE, SH4_RFCR, SH4_RTCOR, SH4_RTCSR, SH4_SAR0, SH4_SAR1, SH4_SAR2, SH4_SAR3, SH4_SAR4, SH4_SAR5, SH4_SAR6, SH4_SAR7, SH4_TCNT0, SH4_TCNT1, SH4_TCNT2, SH4_TCOR0, SH4_TCOR1, SH4_TCOR2, SH4_TCR0, SH4_TCR1, SH4_TCR2, SH4_TEA, SH4_TOCR, SH4_TRA, SH4_TSTR, SH4_TTB, SH4_WCR1, SH4_WCR2, SH4_WCR3, SH_N_ITLB_ENTRIES, SH_N_UTLB_ENTRIES, SHREG_SCSPTR, sh4_data::tcnt, sh4_data::tcor, sh4_data::tcr, TCR_CKEG0, TCR_CKEG1, TCR_ICPE0, TCR_ICPE1, TCR_ICPF, TCR_TPSC2, TCR_TPSC_P16, TCR_TPSC_P256, TCR_TPSC_P4, TCR_TPSC_P64, TCR_UNF, sh_cpu::tea, sh4_data::timer_hz, sh4_data::timer_interrupts_pending, sh4_data::timer_irq, sh4_data::tocr, TOCR_TCOE, sh_cpu::tra, sh4_data::tstr, sh_cpu::ttb, and sh_cpu::utlb_lo.
DEVICE_ACCESS | ( | sh4_itlb_aa | ) |
Definition at line 544 of file dev_sh4.cc.
References cpu::cd, data, INVALIDATE_ALL, cpu::invalidate_translation_caches, INVALIDATE_VADDR, sh_cpu::itlb_hi, sh_cpu::itlb_lo, MEM_WRITE, memory_readmax64(), memory_writemax64(), sh_cpu::pteh, sh_cpu::ptel, cpu::sh, SH4_ITLB_AA_ASID_MASK, SH4_ITLB_AA_V, SH4_ITLB_AA_VPN_MASK, SH4_ITLB_E_MASK, SH4_ITLB_E_SHIFT, SH4_PTEH_ASID_MASK, SH4_PTEH_VPN_MASK, SH4_PTEL_SH, SH4_PTEL_SZ_4K, SH4_PTEL_SZ_MASK, and SH4_PTEL_V.
DEVICE_ACCESS | ( | sh4_itlb_da1 | ) |
Definition at line 588 of file dev_sh4.cc.
References cpu::cd, data, fatal(), INVALIDATE_ALL, cpu::invalidate_translation_caches, INVALIDATE_VADDR, sh_cpu::itlb_hi, sh_cpu::itlb_lo, MEM_WRITE, memory_readmax64(), memory_writemax64(), sh_cpu::pteh, cpu::sh, SH4_ITLB_AA_ASID_MASK, SH4_ITLB_E_MASK, SH4_ITLB_E_SHIFT, SH4_PTEH_ASID_MASK, SH4_PTEL_C, SH4_PTEL_PR_MASK, SH4_PTEL_SH, SH4_PTEL_SZ_4K, SH4_PTEL_SZ_MASK, and SH4_PTEL_V.
DEVICE_ACCESS | ( | sh4_pcic | ) |
Definition at line 792 of file dev_sh4.cc.
References bus_pci_data_access(), bus_pci_setaddr(), cpu::cd, sh_cpu::cpu_type, data, fatal(), MEM_READ, MEM_WRITE, memory_readmax64(), memory_writemax64(), sh_cpu_type_def::name, sh4_data::pci_data, PCI_ID_CODE, PCI_PRODUCT_HITACHI_SH7751, PCI_PRODUCT_HITACHI_SH7751R, PCI_VENDOR_HITACHI, PCIC_REG, sh4_data::pcic_reg, reg, cpu::sh, SH4_PCIBCR1, SH4_PCIBCR2, SH4_PCIBCR3, SH4_PCIC, SH4_PCIC_IO, SH4_PCIC_MEM, SH4_PCICONF0, SH4_PCICONF1, SH4_PCICONF2, SH4_PCICONF5, SH4_PCICONF6, SH4_PCICR, SH4_PCIIOBR, SH4_PCILAR0, SH4_PCILAR1, SH4_PCILSR0, SH4_PCILSR1, SH4_PCIMBR, SH4_PCIMCR, SH4_PCIPAR, SH4_PCIPDR, SH4_PCIWCR1, SH4_PCIWCR2, and SH4_PCIWCR3.
DEVICE_ACCESS | ( | sh4_sq | ) |
Definition at line 950 of file dev_sh4.cc.
References data, MEM_WRITE, and sh4_data::sq.
DEVICE_ACCESS | ( | sh4_utlb_aa | ) |
Definition at line 632 of file dev_sh4.cc.
References cpu::cd, data, EXPEVT_RESET_TLB_MULTI_HIT, INVALIDATE_ALL, cpu::invalidate_translation_caches, INVALIDATE_VADDR, sh_cpu::itlb_hi, sh_cpu::itlb_lo, MEM_WRITE, memory_readmax64(), memory_writemax64(), sh_cpu::pteh, cpu::sh, SH4_PTEH_ASID_MASK, SH4_PTEH_VPN_MASK, SH4_PTEL_D, SH4_PTEL_SH, SH4_PTEL_SZ_1K, SH4_PTEL_SZ_1M, SH4_PTEL_SZ_4K, SH4_PTEL_SZ_64K, SH4_PTEL_SZ_MASK, SH4_PTEL_V, SH4_UTLB_A, SH4_UTLB_AA_ASID_MASK, SH4_UTLB_AA_D, SH4_UTLB_AA_V, SH4_UTLB_AA_VPN_MASK, SH4_UTLB_E_MASK, SH4_UTLB_E_SHIFT, sh_exception(), SH_N_ITLB_ENTRIES, SH_N_UTLB_ENTRIES, sh_cpu::utlb_hi, and sh_cpu::utlb_lo.
DEVICE_ACCESS | ( | sh4_utlb_da1 | ) |
Definition at line 748 of file dev_sh4.cc.
References cpu::cd, data, fatal(), INVALIDATE_ALL, cpu::invalidate_translation_caches, INVALIDATE_VADDR, MEM_WRITE, memory_readmax64(), memory_writemax64(), sh_cpu::pteh, cpu::sh, SH4_ITLB_AA_ASID_MASK, SH4_PTEH_ASID_MASK, SH4_PTEL_C, SH4_PTEL_D, SH4_PTEL_PR_MASK, SH4_PTEL_SH, SH4_PTEL_SZ_4K, SH4_PTEL_SZ_MASK, SH4_PTEL_V, SH4_PTEL_WT, SH4_UTLB_E_MASK, SH4_UTLB_E_SHIFT, sh_cpu::utlb_hi, and sh_cpu::utlb_lo.
DEVICE_TICK | ( | sh4 | ) |
Definition at line 274 of file dev_sh4.cc.
References console_charavail(), console_putchar(), if(), sh4_data::scif_console_handle, sh4_data::scif_delayed_tx, sh4_data::scif_ssr, sh4_data::scif_tx_fifo, sh4_data::scif_tx_fifo_cursize, SCSSR2_DR, SCSSR2_TDFE, and SCSSR2_TEND.
DEVINIT | ( | sh4 | ) |
Definition at line 1848 of file dev_sh4.cc.
References BCR2_PORTEN, sh4_data::bsc_bcr2, CHECK_ALLOCATION, console_start_slave(), dev_ram_init(), DEV_RAM_RAM, DM_DEFAULT, interrupt::extra, interrupt::interrupt_assert, INTERRUPT_CONNECT, devinit::interrupt_path, interrupt::line, devinit::machine, machine::memory, memory_device_register(), N_PCIC_IRQS, N_PCIC_REGS, devinit::name, interrupt::name, PCI_CLASS_BRIDGE, PCI_CLASS_CODE, PCI_SUBCLASS_BRIDGE_HOST, PCIC_REG, sh4_data::pcic_reg, sh4_data::scif_console_handle, sh4_data::scif_rx_irq, sh4_data::scif_tx_irq, SH4_CCDA, SH4_CCDD, SH4_CCIA, SH4_CCID, SH4_DCACHE_SIZE, SH4_ICACHE_SIZE, SH4_INTEVT_SCIF_RXI, SH4_INTEVT_SCIF_TXI, SH4_ITLB_AA, SH4_ITLB_DA1, SH4_PCIC, SH4_PCICONF2, SH4_REG_BASE, SH4_UTLB_AA, and SH4_UTLB_DA1.
Definition at line 322 of file dev_sh4.cc.
References cpu::cd, CHCR_DM, CHCR_DM_DECREMENTED, CHCR_DM_FIXED, CHCR_DM_INCREMENTED, CHCR_IE, CHCR_RS, CHCR_SM, CHCR_SM_DECREMENTED, CHCR_SM_FIXED, CHCR_SM_INCREMENTED, CHCR_TD, CHCR_TE, CHCR_TS, CHCR_TS_1BYTE, CHCR_TS_2BYTE, CHCR_TS_32BYTE, CHCR_TS_4BYTE, CHCR_TS_8BYTE, sh_cpu::dmac_chcr, sh_cpu::dmac_dar, sh_cpu::dmac_sar, sh_cpu::dmac_tcr, fatal(), and cpu::sh.
Referenced by DEVICE_ACCESS().