cpu_alpha.h Source File

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cpu_alpha.h
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1 #ifndef CPU_ALPHA_H
2 #define CPU_ALPHA_H
3 
4 /*
5  * Copyright (C) 2005-2011 Anders Gavare. All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions are met:
9  *
10  * 1. Redistributions of source code must retain the above copyright
11  * notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  * notice, this list of conditions and the following disclaimer in the
14  * documentation and/or other materials provided with the distribution.
15  * 3. The name of the author may not be used to endorse or promote products
16  * derived from this software without specific prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28  * SUCH DAMAGE.
29  *
30  *
31  * Alpha CPU definitions.
32  */
33 
34 #include "misc.h"
35 
36 #include "thirdparty/alpha_cpu.h"
37 
38 
39 /* ALPHA CPU types: */
41  const char *name;
42  uint64_t pcs_type; /* See alpha_rpb.h */
43  int features;
44  int implver;
46  int ilinesize;
47  int iway;
49  int dlinesize;
50  int dway;
53  int l2way;
54 };
55 
56 /* TODO: More features */
57 #define ALPHA_FEATURE_BWX 1
58 
59 #define ALPHA_CPU_TYPE_DEFS { \
60  { "21064", 0x000000002ULL, 0, 0, 16,5,2, 16,5,2, 0,0,0 }, \
61  { "21066", 0x200000004ULL, 0, 0, 16,5,2, 16,5,2, 0,0,0 }, \
62  { "21164", 0x000000005ULL, 0, 1, 16,5,2, 16,5,2, 0,0,0 }, \
63  { "21164A-2", 0x000000007ULL, 0, 1, 16,5,2, 16,5,2, 0,0,0 }, \
64  { "21164PC", 0x000000009ULL, 0, 1, 16,5,2, 16,5,2, 0,0,0 }, \
65  { "21264", 0x00000000dULL, 0, 2, 16,5,2, 16,5,2, 0,0,0 }, \
66  { "21364", 0x000000000ULL, 0, 3, 16,5,2, 16,5,2, 0,0,0 }, \
67  { NULL, 0x000000000ULL, 0, 0, 0,0,0, 0,0,0, 0,0,0 } }
68 
69 
70 struct cpu_family;
71 
72 /* ALPHA_KENTRY_INT .. ALPHA_KENTRY_SYS */
73 #define N_ALPHA_KENTRY 6
74 
75 #define ALPHA_V0 0
76 #define ALPHA_T0 1
77 #define ALPHA_T1 2
78 #define ALPHA_T2 3
79 #define ALPHA_T3 4
80 #define ALPHA_T4 5
81 #define ALPHA_T5 6
82 #define ALPHA_T6 7
83 
84 #define ALPHA_T7 8
85 #define ALPHA_S0 9
86 #define ALPHA_S1 10
87 #define ALPHA_S2 11
88 #define ALPHA_S3 12
89 #define ALPHA_S4 13
90 #define ALPHA_S5 14
91 #define ALPHA_FP 15
92 
93 #define ALPHA_A0 16
94 #define ALPHA_A1 17
95 #define ALPHA_A2 18
96 #define ALPHA_A3 19
97 #define ALPHA_A4 20
98 #define ALPHA_A5 21
99 #define ALPHA_T8 22
100 #define ALPHA_T9 23
101 
102 #define ALPHA_T10 24
103 #define ALPHA_T11 25
104 #define ALPHA_RA 26
105 #define ALPHA_T12 27
106 #define ALPHA_AT 28
107 #define ALPHA_GP 29
108 #define ALPHA_SP 30
109 #define ALPHA_ZERO 31
110 
111 #define N_ALPHA_REGS 32
112 
113 #define ALPHA_REG_NAMES { \
114  "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6", \
115  "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp", \
116  "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9", \
117  "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero" }
118 
119 
120 /* Dyntrans definitions: */
121 
122 #define ALPHA_N_IC_ARGS 3
123 #define ALPHA_INSTR_ALIGNMENT_SHIFT 2
124 #define ALPHA_IC_ENTRIES_SHIFT 11
125 #define ALPHA_IC_ENTRIES_PER_PAGE (1 << ALPHA_IC_ENTRIES_SHIFT)
126 #define ALPHA_PC_TO_IC_ENTRY(a) (((a)>>ALPHA_INSTR_ALIGNMENT_SHIFT) \
127  & (ALPHA_IC_ENTRIES_PER_PAGE-1))
128 #define ALPHA_ADDR_TO_PAGENR(a) ((a) >> (ALPHA_IC_ENTRIES_SHIFT \
129  + ALPHA_INSTR_ALIGNMENT_SHIFT))
130 
131 #define ALPHA_MAX_VPH_TLB_ENTRIES 128
132 
133 #define ALPHA_L2N 17
134 #define ALPHA_L3N 17
135 
136 DYNTRANS_MISC_DECLARATIONS(alpha,ALPHA,uint64_t)
137 DYNTRANS_MISC64_DECLARATIONS(alpha,ALPHA,uint8_t)
138 
139 
140 #define ALPHA_PAGESHIFT 13
141 
142 
143 struct alpha_cpu {
145 
146 
147  /*
148  * General Purpose Registers:
149  */
150 
151  uint64_t r[N_ALPHA_REGS]; /* Integer */
152  uint64_t f[N_ALPHA_REGS]; /* Floating Point */
153 
154  uint64_t fpcr; /* FP Control Reg. */
155 
156  /* Misc.: */
157  uint64_t pcc; /* Cycle Counter */
159  int ll_flag;
160 
162 
163  /* OSF1 PALcode specific: */
164  uint64_t ps; /* Processor Status */
165  uint64_t vptptr; /* Virtual Page Table Ptr */
166  uint64_t sysvalue;
167  uint64_t mces; /* Machine Check Error Summary */
168  uint64_t kgp; /* Kernel GP */
170  uint64_t ctx; /* Ptr to current PCB (?) */
171  struct alpha_pcb pcb; /* Process Control Block */
172 
173 
174  /*
175  * Instruction translation cache and Virtual->Physical->Host
176  * address translation:
177  */
178  DYNTRANS_ITC(alpha)
179  VPH_TLBS(alpha,ALPHA)
180  VPH64(alpha,ALPHA)
181 };
182 
183 
184 /* cpu_alpha.c: */
185 void alpha_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
186  unsigned char *host_page, int writeflag, uint64_t paddr_page);
187 void alpha_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
188 void alpha_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
190 int alpha_run_instr(struct cpu *cpu);
191 int alpha_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
192  unsigned char *data, size_t len, int writeflag, int cache_flags);
194 
195 /* cpu_alpha_palcode.c: */
196 void alpha_palcode_name(uint32_t palcode, char *buf, size_t buflen);
197 void alpha_palcode(struct cpu *cpu, uint32_t palcode);
198 
199 /* memory_alpha.c: */
200 int alpha_translate_v2p(struct cpu *cpu, uint64_t vaddr,
201  uint64_t *return_addr, int flags);
202 
203 
204 #endif /* CPU_ALPHA_H */
data
u_short data
Definition: siireg.h:79
alpha_cpu::f
uint64_t f[N_ALPHA_REGS]
Definition: cpu_alpha.h:152
alpha_cpu::irq_asserted
int irq_asserted
Definition: cpu_alpha.h:161
memory
Definition: memory.h:75
alpha_cpu::fpcr
uint64_t fpcr
Definition: cpu_alpha.h:154
alpha_palcode_name
void alpha_palcode_name(uint32_t palcode, char *buf, size_t buflen)
Definition: cpu_alpha_palcode.cc:55
DYNTRANS_MISC64_DECLARATIONS
#define DYNTRANS_MISC64_DECLARATIONS(arch, ARCH, tlbindextype)
Definition: cpu.h:95
DYNTRANS_MISC_DECLARATIONS
#define DYNTRANS_MISC_DECLARATIONS(arch, ARCH, addrtype)
Definition: cpu.h:72
alpha_cpu_type_def
Definition: cpu_alpha.h:40
alpha_invalidate_translation_caches
void alpha_invalidate_translation_caches(struct cpu *cpu, uint64_t, int)
alpha_update_translation_table
void alpha_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page)
alpha_cpu::pcb
struct alpha_pcb pcb
Definition: cpu_alpha.h:171
alpha_translate_v2p
int alpha_translate_v2p(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
Definition: memory_alpha.cc:43
DYNTRANS_ITC
#define DYNTRANS_ITC(arch)
Definition: cpu.h:143
alpha_cpu_type_def::iway
int iway
Definition: cpu_alpha.h:47
alpha_cpu::kgp
uint64_t kgp
Definition: cpu_alpha.h:168
misc.h
VPH_TLBS
#define VPH_TLBS(arch, ARCH)
Definition: cpu.h:157
alpha_cpu::ps
uint64_t ps
Definition: cpu_alpha.h:164
alpha_cpu::r
uint64_t r[N_ALPHA_REGS]
Definition: cpu_alpha.h:151
alpha_cpu::vptptr
uint64_t vptptr
Definition: cpu_alpha.h:165
alpha_cpu::ctx
uint64_t ctx
Definition: cpu_alpha.h:170
alpha_palcode
void alpha_palcode(struct cpu *cpu, uint32_t palcode)
Definition: cpu_alpha_palcode.cc:163
alpha_cpu_type_def::l2linesize
int l2linesize
Definition: cpu_alpha.h:52
alpha_cpu::cpu_type
struct alpha_cpu_type_def cpu_type
Definition: cpu_alpha.h:144
alpha_cpu::mces
uint64_t mces
Definition: cpu_alpha.h:167
alpha_cpu_type_def::dway
int dway
Definition: cpu_alpha.h:50
alpha_invalidate_code_translation
void alpha_invalidate_code_translation(struct cpu *cpu, uint64_t, int)
alpha_cpu_type_def::pcs_type
uint64_t pcs_type
Definition: cpu_alpha.h:42
N_ALPHA_KENTRY
#define N_ALPHA_KENTRY
Definition: cpu_alpha.h:73
alpha_memory_rw
int alpha_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags)
alpha_cpu_type_def::dcache_shift
int dcache_shift
Definition: cpu_alpha.h:48
alpha_cpu::sysvalue
uint64_t sysvalue
Definition: cpu_alpha.h:166
VPH64
#define VPH64(arch, ARCH)
Definition: cpu.h:223
alpha_cpu::ll_flag
int ll_flag
Definition: cpu_alpha.h:159
alpha_pcb
Definition: alpha_cpu.h:61
alpha_run_instr
int alpha_run_instr(struct cpu *cpu)
alpha_cpu_type_def::implver
int implver
Definition: cpu_alpha.h:44
alpha_cpu_family_init
int alpha_cpu_family_init(struct cpu_family *)
alpha_init_64bit_dummy_tables
void alpha_init_64bit_dummy_tables(struct cpu *cpu)
alpha_cpu::kentry
uint64_t kentry[N_ALPHA_KENTRY]
Definition: cpu_alpha.h:169
alpha_cpu_type_def::l2cache_shift
int l2cache_shift
Definition: cpu_alpha.h:51
cpu
Definition: cpu.h:326
alpha_cpu_type_def::icache_shift
int icache_shift
Definition: cpu_alpha.h:45
alpha_cpu_type_def::ilinesize
int ilinesize
Definition: cpu_alpha.h:46
alpha_cpu_type_def::dlinesize
int dlinesize
Definition: cpu_alpha.h:49
alpha_cpu::load_linked_addr
uint64_t load_linked_addr
Definition: cpu_alpha.h:158
alpha_cpu_type_def::name
const char * name
Definition: cpu_alpha.h:41
alpha_cpu_type_def::l2way
int l2way
Definition: cpu_alpha.h:53
alpha_cpu
Definition: cpu_alpha.h:143
alpha_cpu_type_def::features
int features
Definition: cpu_alpha.h:43
N_ALPHA_REGS
#define N_ALPHA_REGS
Definition: cpu_alpha.h:111
alpha_cpu::pcc
uint64_t pcc
Definition: cpu_alpha.h:157
cpu_family
Definition: cpu.h:256
alpha_cpu.h

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