sh4_intcreg.h Source File
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3 #ifndef _SH3_INTCREG_H_
4 #define _SH3_INTCREG_H_
38 #define SH3_ICR0 0xfffffee0
39 #define SH3_IPRA 0xfffffee2
40 #define SH3_IPRB 0xfffffee4
43 #define SH7709_ICR1 0xa4000010
44 #define SH7709_ICR2 0xa4000012
45 #define SH7709_PINTER 0xa4000014
46 #define SH7709_IPRC 0xa4000016
47 #define SH7709_IPRD 0xa4000018
48 #define SH7709_IPRE 0xa400001a
49 #define SH7709_IRR0 0xa4000004
50 #define SH7709_IRR1 0xa4000006
51 #define SH7709_IRR2 0xa4000008
53 #define IPRC_IRQ3_MASK 0xf000
54 #define IPRC_IRQ2_MASK 0x0f00
55 #define IPRC_IRQ1_MASK 0x00f0
56 #define IPRC_IRQ0_MASK 0x000f
58 #define IPRD_PINT07_MASK 0xf000
59 #define IPRD_PINT8F_MASK 0x0f00
60 #define IPRD_IRQ5_MASK 0x00f0
61 #define IPRD_IRQ4_MASK 0x000f
63 #define IPRE_DMAC_MASK 0xf000
64 #define IPRE_IRDA_MASK 0x0f00
65 #define IPRE_SCIF_MASK 0x00f0
66 #define IPRE_ADC_MASK 0x000f
68 #define IRR0_PINT8F 0x80
69 #define IRR0_PINT07 0x40
70 #define IRR0_IRQ5 0x20
71 #define IRR0_IRQ4 0x10
72 #define IRR0_IRQ3 0x08
73 #define IRR0_IRQ2 0x04
74 #define IRR0_IRQ1 0x02
75 #define IRR0_IRQ0 0x01
79 #define SH4_ICR 0xffd00000
80 #define SH4_IPRA 0xffd00004
81 #define SH4_IPRB 0xffd00008
82 #define SH4_IPRC 0xffd0000c
83 #define SH4_IPRD 0xffd00010
84 #define SH4_INTPRI00 0xfe080000
85 #define SH4_INTREQ00 0xfe080020
86 #define SH4_INTMSK00 0xfe080040
87 #define SH4_INTMSKCLR00 0xfe080060
89 #define IPRC_GPIO_MASK 0xf000
90 #define IPRC_DMAC_MASK 0x0f00
91 #define IPRC_SCIF_MASK 0x00f0
92 #define IPRC_HUDI_MASK 0x000f
94 #define IPRD_IRL0_MASK 0xf000
95 #define IPRD_IRL1_MASK 0x0f00
96 #define IPRD_IRL2_MASK 0x00f0
97 #define IPRD_IRL3_MASK 0x000f
99 #define IPRA_TMU0_MASK 0xf000
100 #define IPRA_TMU1_MASK 0x0f00
101 #define IPRA_TMU2_MASK 0x00f0
102 #define IPRA_RTC_MASK 0x000f
104 #define IPRB_WDT_MASK 0xf000
105 #define IPRB_REF_MASK 0x0f00
106 #define IPRB_SCI_MASK 0x00f0
108 #define INTPRI00_PCI0_MASK 0x0000000f
109 #define INTPRI00_PCI1_MASK 0x000000f0
110 #define INTPRI00_TMU3_MASK 0x00000f00
111 #define INTPRI00_TMU4_MASK 0x0000f000
114 #define INTREQ00_PCISERR 0x00000001
115 #define INTREQ00_PCIDMA3 0x00000002
116 #define INTREQ00_PCIDMA2 0x00000004
117 #define INTREQ00_PCIDMA1 0x00000008
118 #define INTREQ00_PCIDMA0 0x00000010
119 #define INTREQ00_PCIPWON 0x00000020
120 #define INTREQ00_PCIPWDWN 0x00000040
121 #define INTREQ00_PCIERR 0x00000080
122 #define INTREQ00_TUNI3 0x00000100
123 #define INTREQ00_TUNI4 0x00000200
125 #define INTMSK00_MASK_ALL 0x000003ff
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