MainbusComponent.cc Source File

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MainbusComponent.cc
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1 /*
2  * Copyright (C) 2008-2019 Anders Gavare. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are met:
6  *
7  * 1. Redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution.
12  * 3. The name of the author may not be used to endorse or promote products
13  * derived from this software without specific prior written permission.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  */
27 
29 #include "GXemul.h"
30 
31 
33  : Component("mainbus", "mainbus")
34  , m_memoryMapFailed(false)
35  , m_memoryMapValid(false)
36  , m_currentAddressDataBus(NULL)
37 {
38 }
39 
40 
42 {
43 }
44 
45 
47 {
48  return new MainbusComponent();
49 }
50 
51 
52 string MainbusComponent::GetAttribute(const string& attributeName)
53 {
54  if (attributeName == "description")
55  return "A generic main bus.";
56 
57  return Component::GetAttribute(attributeName);
58 }
59 
60 
62 {
63  m_memoryMap.clear();
64  m_memoryMapValid = false;
65  m_memoryMapFailed = false;
66 
67  m_currentAddressDataBus = NULL;
68 
70 }
71 
72 
74 {
76  if (!MakeSureMemoryMapExists(gxemul)) {
77  gxemul->GetUI()->ShowDebugMessage(GenerateTreeDump(""));
78  return false;
79  }
80 
81  return true;
82 }
83 
84 
85 bool MainbusComponent::MakeSureMemoryMapExists(GXemul* gxemul)
86 {
87  if (m_memoryMapFailed)
88  return false;
89 
90  if (m_memoryMapValid)
91  return true;
92 
93  m_memoryMap.clear();
94 
95  m_memoryMapValid = true;
96  m_memoryMapFailed = false;
97 
98  // Build a memory map of all immediate children who implement the
99  // AddressDataBus interface:
100  Components children = GetChildren();
101  for (size_t i=0; i<children.size(); ++i) {
102  AddressDataBus* bus = children[i]->AsAddressDataBus();
103  if (bus == NULL)
104  continue;
105 
106  MemoryMapEntry mmEntry;
107  mmEntry.addressDataBus = bus;
108  mmEntry.addrMul = 1;
109  mmEntry.base = 0;
110 
111  const StateVariable* varBase =
112  children[i]->GetVariable("memoryMappedBase");
113  const StateVariable* varSize =
114  children[i]->GetVariable("memoryMappedSize");
115  const StateVariable* varAddrMul =
116  children[i]->GetVariable("memoryMappedAddrMul");
117 
118  if (varBase != NULL)
119  mmEntry.base = varBase->ToInteger();
120  if (varSize != NULL)
121  mmEntry.size = varSize->ToInteger();
122  if (varAddrMul != NULL)
123  mmEntry.addrMul = varAddrMul->ToInteger();
124 
125  // No base or size? Then skip this component.
126  if (varSize == NULL || varBase == NULL)
127  continue;
128 
129  // Treat the non-sensical addrMul value 0 as 1.
130  if (mmEntry.addrMul == 0)
131  mmEntry.addrMul = 1;
132 
133  // Empty memory mapped region? Then skip this component.
134  if (mmEntry.size == 0)
135  continue;
136 
137  // Check for overlaps against the already existing mappings.
138  //
139  // (Note: Current implementation results in O(n^2) time,
140  // but if the number of memory-mapped immediate childs are
141  // few, then this should not be a big problem.)
142  for (size_t j=0; j<m_memoryMap.size(); ++j) {
143  if (mmEntry.base+mmEntry.size <= m_memoryMap[j].base)
144  continue;
145 
146  if (mmEntry.base >= m_memoryMap[j].base +
147  m_memoryMap[j].size)
148  continue;
149 
150  // There is overlap!
151  if (gxemul != NULL)
152  gxemul->GetUI()->ShowDebugMessage(this,
153  "Error: the base and/or size of " +
154  children[i]->GenerateShortestPossiblePath() +
155  " conflicts with another memory mapped "
156  "component on this bus.\n");
157 
158  m_memoryMap.clear();
159  m_memoryMapValid = false;
160  m_memoryMapFailed = true;
161  return false;
162  }
163 
164  // Finally add the new mapping entry.
165  m_memoryMap.push_back(mmEntry);
166  }
167 
168  return true;
169 }
170 
171 
173 {
174  return this;
175 }
176 
177 
178 void MainbusComponent::AddressSelect(uint64_t address)
179 {
180  MakeSureMemoryMapExists();
181 
182  m_currentAddressDataBus = NULL;
183 
184  if (!m_memoryMapValid)
185  return;
186 
187  // Note: This is a linear O(n) scan of the list of memory-mapped
188  // components. For small n, this should be ok.
189  //
190  // In practice, my hope is that the bulk of all memory access will be
191  // using direct-mapped pages anyway, so this should not be that much
192  // of a problem.
193 
194  for (size_t i=0; i<m_memoryMap.size(); ++i) {
195  MemoryMapEntry& mmEntry = m_memoryMap[i];
196 
197  // If this memory map entry contains the address we wish to
198  // select, then...
199  if (address >= mmEntry.base &&
200  address < mmEntry.base + mmEntry.size) {
201  // ... tell the corresponding component which address
202  // within it we wish to select.
203  m_currentAddressDataBus = mmEntry.addressDataBus;
204  m_currentAddressDataBus->AddressSelect(
205  (address - mmEntry.base) / mmEntry.addrMul);
206  break;
207  }
208  }
209 }
210 
211 
212 bool MainbusComponent::ReadData(uint8_t& data, Endianness endianness)
213 {
214  if (!MakeSureMemoryMapExists())
215  return false;
216 
217  if (m_currentAddressDataBus != NULL)
218  return m_currentAddressDataBus->ReadData(data, endianness);
219  else
220  return false;
221 }
222 
223 
224 bool MainbusComponent::ReadData(uint16_t& data, Endianness endianness)
225 {
226  if (!MakeSureMemoryMapExists())
227  return false;
228 
229  if (m_currentAddressDataBus != NULL)
230  return m_currentAddressDataBus->ReadData(data, endianness);
231  else
232  return false;
233 }
234 
235 
236 bool MainbusComponent::ReadData(uint32_t& data, Endianness endianness)
237 {
238  if (!MakeSureMemoryMapExists())
239  return false;
240 
241  if (m_currentAddressDataBus != NULL)
242  return m_currentAddressDataBus->ReadData(data, endianness);
243  else
244  return false;
245 }
246 
247 
248 bool MainbusComponent::ReadData(uint64_t& data, Endianness endianness)
249 {
250  if (!MakeSureMemoryMapExists())
251  return false;
252 
253  if (m_currentAddressDataBus != NULL)
254  return m_currentAddressDataBus->ReadData(data, endianness);
255  else
256  return false;
257 }
258 
259 
260 bool MainbusComponent::WriteData(const uint8_t& data, Endianness endianness)
261 {
262  if (!MakeSureMemoryMapExists())
263  return false;
264 
265  if (m_currentAddressDataBus != NULL)
266  return m_currentAddressDataBus->WriteData(data, endianness);
267  else
268  return false;
269 }
270 
271 
272 bool MainbusComponent::WriteData(const uint16_t& data, Endianness endianness)
273 {
274  if (!MakeSureMemoryMapExists())
275  return false;
276 
277  if (m_currentAddressDataBus != NULL)
278  return m_currentAddressDataBus->WriteData(data, endianness);
279  else
280  return false;
281 }
282 
283 
284 bool MainbusComponent::WriteData(const uint32_t& data, Endianness endianness)
285 {
286  if (!MakeSureMemoryMapExists())
287  return false;
288 
289  if (m_currentAddressDataBus != NULL)
290  return m_currentAddressDataBus->WriteData(data, endianness);
291  else
292  return false;
293 }
294 
295 
296 bool MainbusComponent::WriteData(const uint64_t& data, Endianness endianness)
297 {
298  if (!MakeSureMemoryMapExists())
299  return false;
300 
301  if (m_currentAddressDataBus != NULL)
302  return m_currentAddressDataBus->WriteData(data, endianness);
303  else
304  return false;
305 }
306 
307 
308 /*****************************************************************************/
309 
310 
311 #ifdef WITHUNITTESTS
312 
313 #include "ComponentFactory.h"
314 
315 static void Test_MainbusComponent_Creatable()
316 {
317  refcount_ptr<Component> mainbus =
319 
320  UnitTest::Assert("The MainbusComponent should be "
321  "instanciable", !mainbus.IsNULL());
322 }
323 
324 static void Test_MainbusComponent_AddressDataBus()
325 {
326  refcount_ptr<Component> mainbus =
328 
329  AddressDataBus* bus = mainbus->AsAddressDataBus();
330  UnitTest::Assert("The MainbusComponent should implement the "
331  "AddressDataBus interface", bus != NULL);
332 }
333 
334 static void Test_MainbusComponent_Simple()
335 {
336  refcount_ptr<Component> mainbus =
340 
341  mainbus->AddChild(ram0);
342  ram0->SetVariableValue("memoryMappedSize", "0x100000");
343  ram0->SetVariableValue("memoryMappedBase", "0");
344 
345  AddressDataBus* bus = mainbus->AsAddressDataBus();
346 
347  uint8_t dataByte = 42;
348  bus->AddressSelect(128);
349  bus->WriteData(dataByte);
350  bus->AddressSelect(129);
351  dataByte = 100;
352  bus->WriteData(dataByte);
353  bus->AddressSelect(128);
354  bus->ReadData(dataByte);
355  UnitTest::Assert("memory wasn't written to correctly?", dataByte, 42);
356  bus->AddressSelect(129);
357  bus->ReadData(dataByte);
358  UnitTest::Assert("memory wasn't written to correctly?", dataByte, 100);
359 }
360 
361 static void Test_MainbusComponent_Remapping()
362 {
363  refcount_ptr<Component> mainbus =
367 
368  mainbus->AddChild(ram0);
369  ram0->SetVariableValue("memoryMappedSize", "0x10000");
370  ram0->SetVariableValue("memoryMappedBase", "0x1000");
371 
372  AddressDataBus* bus = mainbus->AsAddressDataBus();
373 
374  uint8_t dataByte = 123;
375  bus->AddressSelect(0x1030); // offset 0x30 of ram0
376  bus->WriteData(dataByte);
377  dataByte = 18;
378  bus->AddressSelect(0x1050); // offset 0x50 of ram0
379  bus->WriteData(dataByte);
380 
381  // Set a new base for ram0, but do _NOT_ flush cached state yet!
382  // (This is to assert that cached state is actually cached.)
383  ram0->SetVariableValue("memoryMappedBase", "0x1020");
384 
385  uint8_t dataByte2 = 99;
386  bus->AddressSelect(0x1050); // offset 0x30 of ram0
387  bus->ReadData(dataByte2);
388  UnitTest::Assert("remapping should NOT have taken place yet, "
389  "cached state should still be in effect!", dataByte2, 18);
390 
391  // Now, flush the state and make sure the new mapping takes effect:
392  mainbus->FlushCachedState();
393 
394  dataByte2 = 99;
395  bus->AddressSelect(0x1050); // offset 0x30 of ram0
396  bus->ReadData(dataByte2);
397  UnitTest::Assert("remapping failed?", dataByte2, 123);
398 }
399 
400 static void Test_MainbusComponent_Multiple_NonOverlapping()
401 {
402  refcount_ptr<Component> mainbus =
410 
411  mainbus->AddChild(ram0);
412  mainbus->AddChild(ram1);
413  mainbus->AddChild(ram2);
414  ram0->SetVariableValue("memoryMappedSize", "0x100");
415  ram0->SetVariableValue("memoryMappedBase", "0x000");
416  ram1->SetVariableValue("memoryMappedSize", "0x100");
417  ram1->SetVariableValue("memoryMappedBase", "0x100");
418  ram2->SetVariableValue("memoryMappedSize", "0x100");
419  ram2->SetVariableValue("memoryMappedBase", "0x200");
420 
421  AddressDataBus* bus = mainbus->AsAddressDataBus();
422 
423  for (size_t i = 0; i < 0x300; i += sizeof(uint16_t)) {
424  uint16_t data = (uint8_t) i;
425  bus->AddressSelect(i);
426  bus->WriteData(data, LittleEndian);
427  }
428 
429  for (size_t i = 0; i < 0x300; i += sizeof(uint16_t)) {
430  uint16_t data;
431  bus->AddressSelect(i);
432  bus->ReadData(data, BigEndian);
433  UnitTest::Assert("memory wasn't written to correctly?",
434  data, (uint16_t) (i << 8));
435  }
436 }
437 
438 static void Test_MainbusComponent_Simple_With_AddrMul()
439 {
440  refcount_ptr<Component> mainbus =
444 
445  mainbus->AddChild(ram0);
446  ram0->SetVariableValue("memoryMappedSize", "0x1000");
447  ram0->SetVariableValue("memoryMappedBase", "0x80");
448  ram0->SetVariableValue("memoryMappedAddrMul", "5");
449 
450  AddressDataBus* bus = mainbus->AsAddressDataBus();
451 
452  uint8_t dataByte = 42;
453  bus->AddressSelect(128);
454  bus->WriteData(dataByte);
455  bus->AddressSelect(133);
456  dataByte = 100;
457  bus->WriteData(dataByte);
458 
459  bus->AddressSelect(128);
460  bus->ReadData(dataByte);
461  UnitTest::Assert("memory wasn't written to correctly?", dataByte, 42);
462  bus->AddressSelect(133);
463  bus->ReadData(dataByte);
464  UnitTest::Assert("memory wasn't written to correctly?", dataByte, 100);
465 
466  ram0->SetVariableValue("memoryMappedAddrMul", "2");
467  mainbus->FlushCachedState();
468 
469  bus->AddressSelect(128);
470  bus->ReadData(dataByte);
471  UnitTest::Assert("addr mul strangeness?", dataByte, 42);
472  bus->AddressSelect(130);
473  bus->ReadData(dataByte);
474  UnitTest::Assert("offset 130 should have the same value as "
475  "offset 133 had", dataByte, 100);
476  bus->AddressSelect(133);
477  bus->ReadData(dataByte);
478  UnitTest::Assert("offset 133 should NOT have any value "
479  "written to it yet!", dataByte, 0);
480 
481  ram0->SetVariableValue("memoryMappedAddrMul", "1");
482  mainbus->FlushCachedState();
483 
484  bus->AddressSelect(128);
485  bus->ReadData(dataByte);
486  UnitTest::Assert("addr mul strangeness [2]", dataByte, 42);
487  bus->AddressSelect(129);
488  bus->ReadData(dataByte);
489  UnitTest::Assert("offset 129 mismatch [2]", dataByte, 100);
490  bus->AddressSelect(133);
491  bus->ReadData(dataByte);
492  UnitTest::Assert("offset 133 should NOT have any value "
493  "written to it yet! [2]", dataByte, 0);
494 
495  // AddrMul "0" should be same as "1", because the user might think that
496  // address multiplication is "turned off" by setting it to 0.
497  ram0->SetVariableValue("memoryMappedAddrMul", "0");
498  mainbus->FlushCachedState();
499 
500  bus->AddressSelect(128);
501  bus->ReadData(dataByte);
502  UnitTest::Assert("addr mul strangeness [3]", dataByte, 42);
503  bus->AddressSelect(129);
504  bus->ReadData(dataByte);
505  UnitTest::Assert("offset 129 mismatch [3]", dataByte, 100);
506  bus->AddressSelect(133);
507  bus->ReadData(dataByte);
508  UnitTest::Assert("offset 133 should NOT have any value "
509  "written to it yet! [3]", dataByte, 0);
510 }
511 
512 static void Test_MainbusComponent_PreRunCheck()
513 {
514  GXemul gxemul;
515 
516  gxemul.GetCommandInterpreter().RunCommand("add testm88k");
517 
518  UnitTest::Assert("preruncheck should initially succeed for testm88k",
519  gxemul.GetRootComponent()->PreRunCheck(&gxemul) == true);
520 
521  // Adding a second RAM component should succeed, since the initial size
522  // is 0, and does not (yet) conflict.
523  gxemul.GetCommandInterpreter().RunCommand("add ram mainbus0");
524  UnitTest::Assert("preruncheck should still succeed",
525  gxemul.GetRootComponent()->PreRunCheck(&gxemul) == true);
526 
527  // By changing the size to 42, the new ram1 component will overlap
528  // the ram0 component (at least partially).
529  gxemul.GetCommandInterpreter().RunCommand("ram1.memoryMappedSize = 42");
530  UnitTest::Assert("preruncheck should now fail",
531  gxemul.GetRootComponent()->PreRunCheck(&gxemul) == false);
532 }
533 
535 {
536  // Construction, etc.:
537  UNITTEST(Test_MainbusComponent_Creatable);
538  UNITTEST(Test_MainbusComponent_AddressDataBus);
539 
540  // Memory mapping, ranges, overlaps, addrmul, etc.:
541  UNITTEST(Test_MainbusComponent_Simple);
542  UNITTEST(Test_MainbusComponent_Remapping);
543  UNITTEST(Test_MainbusComponent_Multiple_NonOverlapping);
544  UNITTEST(Test_MainbusComponent_Simple_With_AddrMul);
545 
546  // TODO: Write outside of mapped space
547  // TODO: Write PARTIALLY outside of mapped space!!! e.g. 64-bit
548  // into a 3-byte memory area???
549 
550  UNITTEST(Test_MainbusComponent_PreRunCheck);
551 }
552 
553 #endif
554 
Component::PreRunCheck
bool PreRunCheck(GXemul *gxemul)
Checks the state of this component and all its children, before starting execution.
Definition: Component.cc:298
Component::GetChildren
Components & GetChildren()
Gets pointers to child components.
Definition: Component.cc:674
data
u_short data
Definition: siireg.h:79
Component::FlushCachedStateForComponent
virtual void FlushCachedStateForComponent()
Resets the cached state of this component.
Definition: Component.cc:327
AddressDataBus::ReadData
virtual bool ReadData(uint8_t &data, Endianness endianness=BigEndian)=0
Reads 8-bit data from the currently selected address.
refcount_ptr::IsNULL
bool IsNULL() const
Checks whether or not an object is referenced by the reference counted pointer.
Definition: refcount_ptr.h:218
Component::GenerateTreeDump
string GenerateTreeDump(const string &branchTemplate, bool htmlLinksForClassNames=false, string prefixForComponentUrls="") const
Generates an ASCII tree dump of a component tree.
Definition: Component.cc:459
Component::AddChild
void AddChild(refcount_ptr< Component > childComponent, size_t insertPosition=(size_t) -1)
Adds a reference to a child component.
Definition: Component.cc:595
MainbusComponent::Create
static refcount_ptr< Component > Create(const ComponentCreateArgs &args)
Creates a MainbusComponent.
Definition: MainbusComponent.cc:46
ComponentFactory.h
GXemul
The main emulator class.
Definition: GXemul.h:55
MainbusComponent::GetAttribute
static string GetAttribute(const string &attributeName)
Get attribute information about the MainbusComponent class.
Definition: MainbusComponent.cc:52
MainbusComponent::AddressSelect
virtual void AddressSelect(uint64_t address)
Place an address on the bus.
Definition: MainbusComponent.cc:178
MainbusComponent::MainbusComponent
MainbusComponent()
Constructs a MainbusComponent.
Definition: MainbusComponent.cc:32
MainbusComponent::AsAddressDataBus
virtual AddressDataBus * AsAddressDataBus()
Returns the component's AddressDataBus interface.
Definition: MainbusComponent.cc:172
GXemul::GetCommandInterpreter
CommandInterpreter & GetCommandInterpreter()
Gets a reference to the CommandInterpreter.
Definition: GXemul.cc:623
MainbusComponent::PreRunCheckForComponent
virtual bool PreRunCheckForComponent(GXemul *gxemul)
Checks the state of this component, before starting execution.
Definition: MainbusComponent.cc:73
LittleEndian
@ LittleEndian
Definition: misc.h:159
StateVariable
StateVariables make up the persistent state of Component objects.
Definition: StateVariable.h:69
refcount_ptr< Component >
StateVariable::ToInteger
uint64_t ToInteger() const
Returns the variable as an unsignedinteger value.
Definition: StateVariable.cc:280
UNITTESTS
#define UNITTESTS(class)
Helper for unit test case execution.
Definition: UnitTest.h:184
MainbusComponent::ReadData
virtual bool ReadData(uint8_t &data, Endianness endianness)
Reads 8-bit data from the currently selected address.
Definition: MainbusComponent.cc:212
GXemul::GetRootComponent
refcount_ptr< Component > GetRootComponent()
Gets a pointer to the root configuration component.
Definition: GXemul.cc:659
UNITTEST
#define UNITTEST(functionname)
Helper for unit test case execution.
Definition: UnitTest.h:217
UnitTest::Assert
static void Assert(const string &strFailMessage, bool condition)
Asserts that a boolean condition is correct.
Definition: UnitTest.cc:40
AddressDataBus::WriteData
virtual bool WriteData(const uint8_t &data, Endianness endianness=BigEndian)=0
Writes 8-bit data to the currently selected address.
UI::ShowDebugMessage
virtual void ShowDebugMessage(const string &msg)=0
Shows a debug message.
MainbusComponent::FlushCachedStateForComponent
virtual void FlushCachedStateForComponent()
Resets the cached state of this component.
Definition: MainbusComponent.cc:61
Endianness
Endianness
Definition: misc.h:157
MainbusComponent::WriteData
virtual bool WriteData(const uint8_t &data, Endianness endianness)
Writes 8-bit data to the currently selected address.
Definition: MainbusComponent.cc:260
ComponentFactory::CreateComponent
static refcount_ptr< Component > CreateComponent(const string &componentNameAndOptionalArgs, GXemul *gxemul=NULL)
Creates a component given a short component name.
Definition: ComponentFactory.cc:87
Component::SetVariableValue
bool SetVariableValue(const string &name, const string &expression)
Sets a variable to a new value.
Definition: Component.cc:1030
AddressDataBus::AddressSelect
virtual void AddressSelect(uint64_t address)=0
Place an address on the bus.
Component::GenerateShortestPossiblePath
string GenerateShortestPossiblePath() const
Generates a short string representation of the path to the Component.
Definition: Component.cc:721
CommandInterpreter::RunCommand
bool RunCommand(const string &command, bool *pSuccess=NULL)
Runs a command, given as a string.
Definition: CommandInterpreter.cc:958
GXemul::GetUI
UI * GetUI()
Gets a pointer to the GXemul instance' active UI.
Definition: GXemul.cc:653
Component
A Component is a node in the configuration tree that makes up an emulation setup.
Definition: Component.h:64
MainbusComponent
Main bus Component.
Definition: MainbusComponent.h:51
Components
vector< refcount_ptr< Component > > Components
Definition: Component.h:43
MainbusComponent::~MainbusComponent
virtual ~MainbusComponent()
Definition: MainbusComponent.cc:41
MainbusComponent.h
Component::FlushCachedState
void FlushCachedState()
Resets the cached state of this component and all its children.
Definition: Component.cc:317
AddressDataBus
An interface for implementing components that read/write data via an address bus.
Definition: AddressDataBus.h:45
Component::GetAttribute
static string GetAttribute(const string &attributeName)
Creates a Component.
Definition: Component.cc:66
BigEndian
@ BigEndian
Definition: misc.h:158
Component::AsAddressDataBus
virtual AddressDataBus * AsAddressDataBus()
Returns the component's AddressDataBus interface, if any.
Definition: Component.cc:367
ComponentCreateArgs
Definition: Component.h:49
GXemul.h

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