Go to the source code of this file.
Macros | |
#define | VERDE_OUT_DIRECT_WIN_BASE 0x00000000UL |
#define | VERDE_OUT_DIRECT_WIN_SIZE 0x80000000UL |
#define | VERDE_OUT_XLATE_MEM_WIN_SIZE 0x04000000UL |
#define | VERDE_OUT_XLATE_IO_WIN_SIZE 0x00010000UL |
#define | VERDE_OUT_XLATE_MEM_WIN0_BASE 0x80000000UL |
#define | VERDE_OUT_XLATE_MEM_WIN1_BASE 0x84000000UL |
#define | VERDE_OUT_XLATE_IO_WIN0_BASE 0x90000000UL |
#define | VERDE_EXTMEM_BASE 0x90020000UL |
#define | VERDE_PMMR_BASE 0xffffe000UL |
#define | VERDE_PMMR_SIZE 0x00001700UL |
#define | VERDE_ATU_BASE 0x0100 |
#define | VERDE_ATU_SIZE 0x0100 |
#define | VERDE_MU_BASE 0x0300 |
#define | VERDE_MU_SIZE 0x0100 |
#define | VERDE_DMA_BASE 0x0400 |
#define | VERDE_DMA_BASE0 (VERDE_DMA_BASE + 0x00) |
#define | VERDE_DMA_BASE1 (VERDE_DMA_BASE + 0x40) |
#define | VERDE_DMA_SIZE 0x0100 |
#define | VERDE_DMA_CHSIZE 0x0040 |
#define | VERDE_MCU_BASE 0x0500 |
#define | VERDE_MCU_SIZE 0x0100 |
#define | VERDE_SSP_BASE 0x0600 |
#define | VERDE_SSP_SIZE 0x0080 |
#define | VERDE_PBIU_BASE 0x0680 |
#define | VERDE_PBIU_SIZE 0x0080 |
#define | VERDE_AAU_BASE 0x0800 |
#define | VERDE_AAU_SIZE 0x0100 |
#define | VERDE_I2C_BASE 0x1680 |
#define | VERDE_I2C_BASE0 (VERDE_I2C_BASE + 0x00) |
#define | VERDE_I2C_BASE1 (VERDE_I2C_BASE + 0x20) |
#define | VERDE_I2C_SIZE 0x0080 |
#define | VERDE_I2C_CHSIZE 0x0020 |
#define | ATU_IALR0 0x40 /* Inbound ATU Limit 0 */ |
#define | ATU_IATVR0 0x44 /* Inbound ATU Xlate Value 0 */ |
#define | ATU_ERLR 0x48 /* Expansion ROM Limit */ |
#define | ATU_ERTVR 0x4c /* Expansion ROM Xlate Value */ |
#define | ATU_IALR1 0x50 /* Inbound ATU Limit 1 */ |
#define | ATU_IALR2 0x54 /* Inbound ATU Limit 2 */ |
#define | ATU_IATVR2 0x58 /* Inbound ATU Xlate Value 2 */ |
#define | ATU_OIOWTVR 0x5c /* Outbound I/O Window Xlate Value */ |
#define | ATU_OMWTVR0 0x60 /* Outbound Mem Window Xlate Value 0 */ |
#define | ATU_OUMWTVR0 0x64 /* Outbound Mem Window Xlate Value 0 Upper */ |
#define | ATU_OMWTVR1 0x68 /* Outbound Mem Window Xlate Value 1 */ |
#define | ATU_OUMWTVR1 0x6c /* Outbound Mem Window Xlate Value 1 Upper */ |
#define | ATU_OUDWTVR 0x78 /* Outbound Mem Direct Xlate Value Upper */ |
#define | ATU_ATUCR 0x80 /* ATU Configuration */ |
#define | ATU_PCSR 0x84 /* PCI Configuration and Status */ |
#define | ATU_ATUISR 0x88 /* ATU Interrupt Status */ |
#define | ATU_ATUIMR 0x8c /* ATU Interrupt Mask */ |
#define | ATU_IABAR3 0x90 /* Inbound ATU Base Address 3 */ |
#define | ATU_IAUBAR3 0x94 /* Inbound ATU Base Address 3 Upper */ |
#define | ATU_IALR3 0x98 /* Inbound ATU Limit 3 */ |
#define | ATU_IATVR3 0x9c /* Inbound ATU Xlate Value 3 */ |
#define | ATU_OCCAR 0xa4 /* Outbound Configuration Cycle Address */ |
#define | ATU_OCCDR 0xac /* Outbound Configuration Cycle Data */ |
#define | ATU_MSI_PORT 0xb4 /* MSI port */ |
#define | ATU_PDSCR 0xbc /* PCI Bus Drive Strength Control */ |
#define | ATU_PCI_X_CAP_ID 0xe0 /* (1) */ |
#define | ATU_PCI_X_NEXT 0xe1 /* (1) */ |
#define | ATU_PCIXCMD 0xe2 /* PCI-X Command Register (2) */ |
#define | ATU_PCIXSR 0xe4 /* PCI-X Status Register */ |
#define | ATUCR_DRC_ALIAS (1U << 19) |
#define | ATUCR_DAU2GXEN (1U << 18) |
#define | ATUCR_P_SERR_MA (1U << 16) |
#define | ATUCR_DTS (1U << 15) |
#define | ATUCR_P_SERR_DIE (1U << 9) |
#define | ATUCR_DAE (1U << 8) |
#define | ATUCR_BIST_IE (1U << 3) |
#define | ATUCR_OUT_EN (1U << 1) |
#define | PCSR_DAAAPE (1U << 18) |
#define | PCSR_PCI_X_CAP (3U << 16) |
#define | PCSR_PCI_X_CAP_BORING (0 << 16) |
#define | PCSR_PCI_X_CAP_66 (1U << 16) |
#define | PCSR_PCI_X_CAP_100 (2U << 16) |
#define | PCSR_PCI_X_CAP_133 (3U << 16) |
#define | PCSR_OTQB (1U << 15) |
#define | PCSR_IRTQB (1U << 14) |
#define | PCSR_DTV (1U << 12) |
#define | PCSR_BUS66 (1U << 10) |
#define | PCSR_BUS64 (1U << 8) |
#define | PCSR_RIB (1U << 5) |
#define | PCSR_RPB (1U << 4) |
#define | PCSR_CCR (1U << 2) |
#define | PCSR_CPR (1U << 1) |
#define | ATUISR_IMW1BU (1U << 14) |
#define | ATUISR_ISCEM (1U << 13) |
#define | ATUISR_RSCEM (1U << 12) |
#define | ATUISR_PST (1U << 11) |
#define | ATUISR_P_SERR_ASRT (1U << 10) |
#define | ATUISR_DPE (1U << 9) |
#define | ATUISR_BIST (1U << 8) |
#define | ATUISR_IBMA (1U << 7) |
#define | ATUISR_P_SERR_DET (1U << 4) |
#define | ATUISR_PMA (1U << 3) |
#define | ATUISR_PTAM (1U << 2) |
#define | ATUISR_PTAT (1U << 1) |
#define | ATUISR_PMPE (1U << 0) |
#define | ATUIMR_IMW1BU (1U << 11) |
#define | ATUIMR_ISCEM (1U << 10) |
#define | ATUIMR_RSCEM (1U << 9) |
#define | ATUIMR_PST (1U << 8) |
#define | ATUIMR_DPE (1U << 7) |
#define | ATUIMR_P_SERR_ASRT (1U << 6) |
#define | ATUIMR_PMA (1U << 5) |
#define | ATUIMR_PTAM (1U << 4) |
#define | ATUIMR_PTAT (1U << 3) |
#define | ATUIMR_PMPE (1U << 2) |
#define | ATUIMR_IE_SERR_EN (1U << 1) |
#define | ATUIMR_ECC_TAE (1U << 0) |
#define | PCIXCMD_MOST_1 (0 << 4) |
#define | PCIXCMD_MOST_2 (1 << 4) |
#define | PCIXCMD_MOST_3 (2 << 4) |
#define | PCIXCMD_MOST_4 (3 << 4) |
#define | PCIXCMD_MOST_8 (4 << 4) |
#define | PCIXCMD_MOST_12 (5 << 4) |
#define | PCIXCMD_MOST_16 (6 << 4) |
#define | PCIXCMD_MOST_32 (7 << 4) |
#define | PCIXCMD_MOST_MASK (7 << 4) |
#define | PCIXCMD_MMRBC_512 (0 << 2) |
#define | PCIXCMD_MMRBC_1024 (1 << 2) |
#define | PCIXCMD_MMRBC_2048 (2 << 2) |
#define | PCIXCMD_MMRBC_4096 (3 << 2) |
#define | PCIXCMD_MMRBC_MASK (3 << 2) |
#define | PCIXCMD_ERO (1U << 1) |
#define | PCIXCMD_DPERE (1U << 0) |
#define | PCIXSR_RSCEM (1U << 29) |
#define | PCIXSR_DMCRS_MASK (7 << 26) |
#define | PCIXSR_DMOST_MASK (7 << 23) |
#define | PCIXSR_COMPLEX (1U << 20) |
#define | PCIXSR_USC (1U << 19) |
#define | PCIXSR_SCD (1U << 18) |
#define | PCIXSR_133_CAP (1U << 17) |
#define | PCIXSR_32PCI (1U << 16) /* 0 = 32, 1 = 64 */ |
#define | PCIXSR_BUSNO(x) (((x) & 0xff00) >> 8) |
#define | PCIXSR_DEVNO(x) (((x) & 0xf8) >> 3) |
#define | PCIXSR_FUNCNO(x) ((x) & 0x7) |
#define | MCU_SDIR 0x00 /* DDR SDRAM Init. Register */ |
#define | MCU_SDCR 0x04 /* DDR SDRAM Control Register */ |
#define | MCU_SDBR 0x08 /* SDRAM Base Register */ |
#define | MCU_SBR0 0x0c /* SDRAM Boundary 0 */ |
#define | MCU_SBR1 0x10 /* SDRAM Boundary 1 */ |
#define | MCU_ECCR 0x34 /* ECC Control Register */ |
#define | MCU_ELOG0 0x38 /* ECC Log 0 */ |
#define | MCU_ELOG1 0x3c /* ECC Log 1 */ |
#define | MCU_ECAR0 0x40 /* ECC address 0 */ |
#define | MCU_ECAR1 0x44 /* ECC address 1 */ |
#define | MCU_ECTST 0x48 /* ECC test register */ |
#define | MCU_MCISR 0x4c /* MCU Interrupt Status Register */ |
#define | MCU_RFR 0x50 /* Refresh Frequency Register */ |
#define | MCU_DBUDSR 0x54 /* Data Bus Pull-up Drive Strength */ |
#define | MCU_DBDDSR 0x58 /* Data Bus Pull-down Drive Strength */ |
#define | MCU_CUDSR 0x5c /* Clock Pull-up Drive Strength */ |
#define | MCU_CDDSR 0x60 /* Clock Pull-down Drive Strength */ |
#define | MCU_CEUDSR 0x64 /* Clock En Pull-up Drive Strength */ |
#define | MCU_CEDDSR 0x68 /* Clock En Pull-down Drive Strength */ |
#define | MCU_CSUDSR 0x6c /* Chip Sel Pull-up Drive Strength */ |
#define | MCU_CSDDSR 0x70 /* Chip Sel Pull-down Drive Strength */ |
#define | MCU_REUDSR 0x74 /* Rx En Pull-up Drive Strength */ |
#define | MCU_REDDSR 0x78 /* Rx En Pull-down Drive Strength */ |
#define | MCU_ABUDSR 0x7c /* Addr Bus Pull-up Drive Strength */ |
#define | MCU_ABDDSR 0x80 /* Addr Bus Pull-down Drive Strength */ |
#define | MCU_DSDR 0x84 /* Data Strobe Delay Register */ |
#define | MCU_REDR 0x88 /* Rx Enable Delay Register */ |
#define | SDCR_DIMMTYPE (1U << 1) /* 0 = unbuf, 1 = reg */ |
#define | SDCR_BUSWIDTH (1U << 2) /* 0 = 64, 1 = 32 */ |
#define | SBRx_TECH (1U << 31) |
#define | SBRx_BOUND 0x0000003f |
#define | ECCR_SBERE (1U << 0) |
#define | ECCR_MBERE (1U << 1) |
#define | ECCR_SBECE (1U << 2) |
#define | ECCR_ECCEN (1U << 3) |
#define | ELOGx_SYNDROME 0x000000ff |
#define | ELOGx_ERRTYPE (1U << 8) /* 1 = multi-bit */ |
#define | ELOGx_RW (1U << 12) /* 1 = write error */ |
#define | ELOGx_REQ_DEV(x) (((x) >> 19) & 0x1f) |
#define | ELOGx_REQ_FUNC(x) (((x) >> 16) & 0x3) |
#define | MCISR_ECC_ERR0 (1U << 0) |
#define | MCISR_ECC_ERR1 (1U << 1) |
#define | MCISR_ECC_ERRN (1U << 2) |
#define | TMRx_TC (1U << 0) |
#define | TMRx_ENABLE (1U << 1) |
#define | TMRx_RELOAD (1U << 2) |
#define | TMRx_CSEL_CORE (0 << 4) |
#define | TMRx_CSEL_CORE_div4 (1 << 4) |
#define | TMRx_CSEL_CORE_div8 (2 << 4) |
#define | TMRx_CSEL_CORE_div16 (3 << 4) |
#define | TISR_TMR0 (1U << 0) |
#define | TISR_TMR1 (1U << 1) |
#define | WDTCR_ENABLE1 0x1e1e1e1e |
#define | WDTCR_ENABLE2 0xe1e1e1e1 |
#define | ICU_PIRSR 0x01ec |
#define | ICU_GPOE 0x07c4 |
#define | ICU_GPID 0x07c8 |
#define | ICU_GPOD 0x07cc |
#define | ICU_INT_HPI 31 /* high priority interrupt */ |
#define | ICU_INT_XINT0 27 /* external interrupts */ |
#define | ICU_INT_XINT(x) ((x) + ICU_INT_XINT0) |
#define | ICU_INT_bit26 26 |
#define | ICU_INT_SSP 25 /* SSP serial port */ |
#define | ICU_INT_MUE 24 /* msg unit error */ |
#define | ICU_INT_AAUE 23 /* AAU error */ |
#define | ICU_INT_bit22 22 |
#define | ICU_INT_DMA1E 21 /* DMA Ch 1 error */ |
#define | ICU_INT_DMA0E 20 /* DMA Ch 0 error */ |
#define | ICU_INT_MCUE 19 /* memory controller error */ |
#define | ICU_INT_ATUE 18 /* ATU error */ |
#define | ICU_INT_BIUE 17 /* bus interface unit error */ |
#define | ICU_INT_PMU 16 /* XScale PMU */ |
#define | ICU_INT_PPM 15 /* peripheral PMU */ |
#define | ICU_INT_BIST 14 /* ATU Start BIST */ |
#define | ICU_INT_MU 13 /* messaging unit */ |
#define | ICU_INT_I2C1 12 /* i2c unit 1 */ |
#define | ICU_INT_I2C0 11 /* i2c unit 0 */ |
#define | ICU_INT_TMR1 10 /* timer 1 */ |
#define | ICU_INT_TMR0 9 /* timer 0 */ |
#define | ICU_INT_CPPM 8 /* core processor PMU */ |
#define | ICU_INT_AAU_EOC 7 /* AAU end-of-chain */ |
#define | ICU_INT_AAU_EOT 6 /* AAU end-of-transfer */ |
#define | ICU_INT_bit5 5 |
#define | ICU_INT_bit4 4 |
#define | ICU_INT_DMA1_EOC 3 /* DMA1 end-of-chain */ |
#define | ICU_INT_DMA1_EOT 2 /* DMA1 end-of-transfer */ |
#define | ICU_INT_DMA0_EOC 1 /* DMA0 end-of-chain */ |
#define | ICU_INT_DMA0_EOT 0 /* DMA0 end-of-transfer */ |
#define | ICU_INT_HWMASK |
#define | SSP_SSCR0 0x00 /* SSC control 0 */ |
#define | SSP_SSCR1 0x04 /* SSC control 1 */ |
#define | SSP_SSSR 0x08 /* SSP status */ |
#define | SSP_SSITR 0x0c /* SSP interrupt test */ |
#define | SSP_SSDR 0x10 /* SSP data */ |
#define | SSP_SSCR0_DSIZE(x) ((x) - 1)/* data size: 4..16 */ |
#define | SSP_SSCR0_FRF_SPI (0 << 4) /* Motorola Serial Periph Iface */ |
#define | SSP_SSCR0_FRF_SSP (1U << 4)/* TI Sync. Serial Protocol */ |
#define | SSP_SSCR0_FRF_UWIRE (2U << 4)/* NatSemi Microwire */ |
#define | SSP_SSCR0_FRF_rsvd (3U << 4)/* reserved */ |
#define | SSP_SSCR0_ECS (1U << 6)/* external clock select */ |
#define | SSP_SSCR0_SSE (1U << 7)/* sync. serial port enable */ |
#define | SSP_SSCR0_SCR(x) ((x) << 8)/* serial clock rate */ |
#define | SSP_SSCR1_RIE (1U << 0)/* Rx FIFO interrupt enable */ |
#define | SSP_SSCR1_TIE (1U << 1)/* Tx FIFO interrupt enable */ |
#define | SSP_SSCR1_LBM (1U << 2)/* loopback mode enable */ |
#define | SSP_SSCR1_SPO (1U << 3)/* Moto SPI SSCLK pol. (1 = high) */ |
#define | SSP_SSCR1_SPH |
#define | SSP_SSCR1_MWDS |
#define | SSP_SSCR1_TFT (((x) - 1) << 6) /* Tx FIFO threshold */ |
#define | SSP_SSCR1_RFT (((x) - 1) << 10)/* Rx FIFO threshold */ |
#define | SSP_SSCR1_EFWR (1U << 14)/* enab. FIFO write/read */ |
#define | SSP_SSCR1_STRF |
#define | SSP_SSSR_TNF (1U << 2)/* Tx FIFO not full */ |
#define | SSP_SSSR_RNE (1U << 3)/* Rx FIFO not empty */ |
#define | SSP_SSSR_BSY (1U << 4)/* SSP is busy */ |
#define | SSP_SSSR_TFS (1U << 5)/* Tx FIFO service request */ |
#define | SSP_SSSR_RFS (1U << 6)/* Rx FIFO service request */ |
#define | SSP_SSSR_ROR (1U << 7)/* Rx FIFO overrun */ |
#define | SSP_SSSR_TFL(x) (((x) >> 8) & 0xf) /* Tx FIFO level */ |
#define | SSP_SSSR_RFL(x) (((x) >> 12) & 0xf)/* Rx FIFO level */ |
#define | SSP_SSITR_TTFS (1U << 5)/* Test Tx FIFO service */ |
#define | SSP_SSITR_TRFS (1U << 6)/* Test Rx FIFO service */ |
#define | SSP_SSITR_TROR (1U << 7)/* Test Rx overrun */ |
#define | PBIU_PBCR 0x00 /* PBIU Control Register */ |
#define | PBIU_PBBAR0 0x08 /* PBIU Base Address Register 0 */ |
#define | PBIU_PBLR0 0x0c /* PBIU Limit Register 0 */ |
#define | PBIU_PBBAR1 0x10 /* PBIU Base Address Register 1 */ |
#define | PBIU_PBLR1 0x14 /* PBIU Limit Register 1 */ |
#define | PBIU_PBBAR2 0x18 /* PBIU Base Address Register 2 */ |
#define | PBIU_PBLR2 0x1c /* PBIU Limit Register 2 */ |
#define | PBIU_PBBAR3 0x20 /* PBIU Base Address Register 3 */ |
#define | PBIU_PBLR3 0x24 /* PBIU Limit Register 3 */ |
#define | PBIU_PBBAR4 0x28 /* PBIU Base Address Register 4 */ |
#define | PBIU_PBLR4 0x2c /* PBIU Limit Register 4 */ |
#define | PBIU_PBBAR5 0x30 /* PBIU Base Address Register 5 */ |
#define | PBIU_PBLR5 0x34 /* PBIU Limit Register 5 */ |
#define | PBIU_DSCR 0x38 /* PBIU Drive Strength Control Reg. */ |
#define | PBIU_MBR0 0x40 /* PBIU Memory-less Boot Reg. 0 */ |
#define | PBIU_MBR1 0x60 /* PBIU Memory-less Boot Reg. 1 */ |
#define | PBIU_MBR2 0x64 /* PBIU Memory-less Boot Reg. 2 */ |
#define | PBIU_PBCR_PBIEN (1 << 0) |
#define | PBIU_PBCR_PBI100 (1 << 1) |
#define | PBIU_PBCR_PBI66 (2 << 1) |
#define | PBIU_PBCR_PBI33 (3 << 1) |
#define | PBIU_PBCR_PBBEN (1 << 3) |
#define | PBIU_PBARx_WIDTH8 (0 << 0) |
#define | PBIU_PBARx_WIDTH16 (1 << 0) |
#define | PBIU_PBARx_WIDTH32 (2 << 0) |
#define | PBIU_PBARx_ADWAIT4 (0 << 2) |
#define | PBIU_PBARx_ADWAIT8 (1 << 2) |
#define | PBIU_PBARx_ADWAIT12 (2 << 2) |
#define | PBIU_PBARx_ADWAIT16 (3 << 2) |
#define | PBIU_PBARx_ADWAIT20 (4 << 2) |
#define | PBIU_PBARx_RCWAIT1 (0 << 6) |
#define | PBIU_PBARx_RCWAIT4 (1 << 6) |
#define | PBIU_PBARx_RCWAIT8 (2 << 6) |
#define | PBIU_PBARx_RCWAIT12 (3 << 6) |
#define | PBIU_PBARx_RCWAIT16 (4 << 6) |
#define | PBIU_PBARx_RCWAIT20 (5 << 6) |
#define | PBIU_PBARx_FWE (1 << 9) |
#define | PBIU_BASE_MASK 0xfffff000U |
#define | PBIU_PBLRx_SIZE(x) (~((x) - 1)) |
#define | MU_IMR0 0x0010 /* MU Inbound Message Register 0 */ |
#define | MU_IMR1 0x0014 /* MU Inbound Message Register 1 */ |
#define | MU_OMR0 0x0018 /* MU Outbound Message Register 0 */ |
#define | MU_OMR1 0x001c /* MU Outbound Message Register 1 */ |
#define | MU_IDR 0x0020 /* MU Inbound Doorbell Register */ |
#define | MU_IISR 0x0024 /* MU Inbound Interrupt Status Reg */ |
#define | MU_IIMR 0x0028 /* MU Inbound Interrupt Mask Reg */ |
#define | MU_ODR 0x002c /* MU Outbound Doorbell Register */ |
#define | MU_OISR 0x0030 /* MU Outbound Interrupt Status Reg */ |
#define | MU_OIMR 0x0034 /* MU Outbound Interrupt Mask Reg */ |
#define | MU_MUCR 0x0050 /* MU Configuration Register */ |
#define | MU_QBAR 0x0054 /* MU Queue Base Address Register */ |
#define | MU_IFHPR 0x0060 /* MU Inbound Free Head Pointer Reg */ |
#define | MU_IFTPR 0x0064 /* MU Inbound Free Tail Pointer Reg */ |
#define | MU_IPHPR 0x0068 /* MU Inbound Post Head Pointer Reg */ |
#define | MU_IPTPR 0x006c /* MU Inbound Post Tail Pointer Reg */ |
#define | MU_OFHPR 0x0070 /* MU Outbound Free Head Pointer Reg */ |
#define | MU_OFTPR 0x0074 /* MU Outbound Free Tail Pointer Reg */ |
#define | MU_OPHPR 0x0078 /* MU Outbound Post Head Pointer Reg */ |
#define | MU_OPTPR 0x007c /* MU Outbound Post Tail Pointer Reg */ |
#define | MU_IAR 0x0080 /* MU Index Address Register */ |
#define | MU_IIMR_IRI (1 << 6) /* Index Register Interrupt */ |
#define | MU_IIMR_OFQFI (1 << 5) /* Outbound Free Queue Full Int. */ |
#define | MU_IIMR_IPQI (1 << 4) /* Inbound Post Queue Interrupt */ |
#define | MU_IIMR_EDI (1 << 3) /* Error Doorbell Interrupt */ |
#define | MU_IIMR_IDI (1 << 2) /* Inbound Doorbell Interrupt */ |
#define | MU_IIMR_IM1I (1 << 1) /* Inbound Message 1 Interrupt */ |
#define | MU_IIMR_IM0I (1 << 0) /* Inbound Message 0 Interrupt */ |
#define ATU_ATUCR 0x80 /* ATU Configuration */ |
Definition at line 125 of file i80321reg.h.
#define ATU_ATUIMR 0x8c /* ATU Interrupt Mask */ |
Definition at line 128 of file i80321reg.h.
#define ATU_ATUISR 0x88 /* ATU Interrupt Status */ |
Definition at line 127 of file i80321reg.h.
#define ATU_ERLR 0x48 /* Expansion ROM Limit */ |
Definition at line 114 of file i80321reg.h.
#define ATU_ERTVR 0x4c /* Expansion ROM Xlate Value */ |
Definition at line 115 of file i80321reg.h.
#define ATU_IABAR3 0x90 /* Inbound ATU Base Address 3 */ |
Definition at line 129 of file i80321reg.h.
#define ATU_IALR0 0x40 /* Inbound ATU Limit 0 */ |
Definition at line 112 of file i80321reg.h.
#define ATU_IALR1 0x50 /* Inbound ATU Limit 1 */ |
Definition at line 116 of file i80321reg.h.
#define ATU_IALR2 0x54 /* Inbound ATU Limit 2 */ |
Definition at line 117 of file i80321reg.h.
#define ATU_IALR3 0x98 /* Inbound ATU Limit 3 */ |
Definition at line 131 of file i80321reg.h.
#define ATU_IATVR0 0x44 /* Inbound ATU Xlate Value 0 */ |
Definition at line 113 of file i80321reg.h.
#define ATU_IATVR2 0x58 /* Inbound ATU Xlate Value 2 */ |
Definition at line 118 of file i80321reg.h.
#define ATU_IATVR3 0x9c /* Inbound ATU Xlate Value 3 */ |
Definition at line 132 of file i80321reg.h.
#define ATU_IAUBAR3 0x94 /* Inbound ATU Base Address 3 Upper */ |
Definition at line 130 of file i80321reg.h.
#define ATU_MSI_PORT 0xb4 /* MSI port */ |
Definition at line 135 of file i80321reg.h.
#define ATU_OCCAR 0xa4 /* Outbound Configuration Cycle Address */ |
Definition at line 133 of file i80321reg.h.
#define ATU_OCCDR 0xac /* Outbound Configuration Cycle Data */ |
Definition at line 134 of file i80321reg.h.
#define ATU_OIOWTVR 0x5c /* Outbound I/O Window Xlate Value */ |
Definition at line 119 of file i80321reg.h.
#define ATU_OMWTVR0 0x60 /* Outbound Mem Window Xlate Value 0 */ |
Definition at line 120 of file i80321reg.h.
#define ATU_OMWTVR1 0x68 /* Outbound Mem Window Xlate Value 1 */ |
Definition at line 122 of file i80321reg.h.
#define ATU_OUDWTVR 0x78 /* Outbound Mem Direct Xlate Value Upper */ |
Definition at line 124 of file i80321reg.h.
#define ATU_OUMWTVR0 0x64 /* Outbound Mem Window Xlate Value 0 Upper */ |
Definition at line 121 of file i80321reg.h.
#define ATU_OUMWTVR1 0x6c /* Outbound Mem Window Xlate Value 1 Upper */ |
Definition at line 123 of file i80321reg.h.
#define ATU_PCI_X_CAP_ID 0xe0 /* (1) */ |
Definition at line 137 of file i80321reg.h.
#define ATU_PCI_X_NEXT 0xe1 /* (1) */ |
Definition at line 138 of file i80321reg.h.
Definition at line 139 of file i80321reg.h.
#define ATU_PCIXSR 0xe4 /* PCI-X Status Register */ |
Definition at line 140 of file i80321reg.h.
#define ATU_PCSR 0x84 /* PCI Configuration and Status */ |
Definition at line 126 of file i80321reg.h.
#define ATU_PDSCR 0xbc /* PCI Bus Drive Strength Control */ |
Definition at line 136 of file i80321reg.h.
#define ATUCR_BIST_IE (1U << 3) |
Definition at line 148 of file i80321reg.h.
#define ATUCR_DAE (1U << 8) |
Definition at line 147 of file i80321reg.h.
#define ATUCR_DAU2GXEN (1U << 18) |
Definition at line 143 of file i80321reg.h.
#define ATUCR_DRC_ALIAS (1U << 19) |
Definition at line 142 of file i80321reg.h.
#define ATUCR_DTS (1U << 15) |
Definition at line 145 of file i80321reg.h.
#define ATUCR_OUT_EN (1U << 1) |
Definition at line 149 of file i80321reg.h.
#define ATUCR_P_SERR_DIE (1U << 9) |
Definition at line 146 of file i80321reg.h.
#define ATUCR_P_SERR_MA (1U << 16) |
Definition at line 144 of file i80321reg.h.
#define ATUIMR_DPE (1U << 7) |
Definition at line 185 of file i80321reg.h.
#define ATUIMR_ECC_TAE (1U << 0) |
Definition at line 192 of file i80321reg.h.
#define ATUIMR_IE_SERR_EN (1U << 1) |
Definition at line 191 of file i80321reg.h.
#define ATUIMR_IMW1BU (1U << 11) |
Definition at line 181 of file i80321reg.h.
#define ATUIMR_ISCEM (1U << 10) |
Definition at line 182 of file i80321reg.h.
#define ATUIMR_P_SERR_ASRT (1U << 6) |
Definition at line 186 of file i80321reg.h.
#define ATUIMR_PMA (1U << 5) |
Definition at line 187 of file i80321reg.h.
#define ATUIMR_PMPE (1U << 2) |
Definition at line 190 of file i80321reg.h.
#define ATUIMR_PST (1U << 8) |
Definition at line 184 of file i80321reg.h.
#define ATUIMR_PTAM (1U << 4) |
Definition at line 188 of file i80321reg.h.
#define ATUIMR_PTAT (1U << 3) |
Definition at line 189 of file i80321reg.h.
#define ATUIMR_RSCEM (1U << 9) |
Definition at line 183 of file i80321reg.h.
#define ATUISR_BIST (1U << 8) |
Definition at line 173 of file i80321reg.h.
#define ATUISR_DPE (1U << 9) |
Definition at line 172 of file i80321reg.h.
#define ATUISR_IBMA (1U << 7) |
Definition at line 174 of file i80321reg.h.
#define ATUISR_IMW1BU (1U << 14) |
Definition at line 167 of file i80321reg.h.
#define ATUISR_ISCEM (1U << 13) |
Definition at line 168 of file i80321reg.h.
#define ATUISR_P_SERR_ASRT (1U << 10) |
Definition at line 171 of file i80321reg.h.
#define ATUISR_P_SERR_DET (1U << 4) |
Definition at line 175 of file i80321reg.h.
#define ATUISR_PMA (1U << 3) |
Definition at line 176 of file i80321reg.h.
#define ATUISR_PMPE (1U << 0) |
Definition at line 179 of file i80321reg.h.
#define ATUISR_PST (1U << 11) |
Definition at line 170 of file i80321reg.h.
#define ATUISR_PTAM (1U << 2) |
Definition at line 177 of file i80321reg.h.
#define ATUISR_PTAT (1U << 1) |
Definition at line 178 of file i80321reg.h.
#define ATUISR_RSCEM (1U << 12) |
Definition at line 169 of file i80321reg.h.
#define ECCR_ECCEN (1U << 3) |
Definition at line 263 of file i80321reg.h.
#define ECCR_MBERE (1U << 1) |
Definition at line 261 of file i80321reg.h.
#define ECCR_SBECE (1U << 2) |
Definition at line 262 of file i80321reg.h.
#define ECCR_SBERE (1U << 0) |
Definition at line 260 of file i80321reg.h.
#define ELOGx_ERRTYPE (1U << 8) /* 1 = multi-bit */ |
Definition at line 266 of file i80321reg.h.
#define ELOGx_REQ_DEV | ( | x | ) | (((x) >> 19) & 0x1f) |
Definition at line 276 of file i80321reg.h.
#define ELOGx_REQ_FUNC | ( | x | ) | (((x) >> 16) & 0x3) |
Definition at line 277 of file i80321reg.h.
#define ELOGx_RW (1U << 12) /* 1 = write error */ |
Definition at line 267 of file i80321reg.h.
#define ELOGx_SYNDROME 0x000000ff |
Definition at line 265 of file i80321reg.h.
#define ICU_GPID 0x07c8 |
Definition at line 326 of file i80321reg.h.
#define ICU_GPOD 0x07cc |
Definition at line 327 of file i80321reg.h.
#define ICU_GPOE 0x07c4 |
Definition at line 325 of file i80321reg.h.
#define ICU_INT_AAU_EOC 7 /* AAU end-of-chain */ |
Definition at line 355 of file i80321reg.h.
#define ICU_INT_AAU_EOT 6 /* AAU end-of-transfer */ |
Definition at line 356 of file i80321reg.h.
#define ICU_INT_AAUE 23 /* AAU error */ |
Definition at line 339 of file i80321reg.h.
#define ICU_INT_ATUE 18 /* ATU error */ |
Definition at line 344 of file i80321reg.h.
#define ICU_INT_BIST 14 /* ATU Start BIST */ |
Definition at line 348 of file i80321reg.h.
#define ICU_INT_bit22 22 |
Definition at line 340 of file i80321reg.h.
#define ICU_INT_bit26 26 |
Definition at line 336 of file i80321reg.h.
#define ICU_INT_bit4 4 |
Definition at line 358 of file i80321reg.h.
#define ICU_INT_bit5 5 |
Definition at line 357 of file i80321reg.h.
#define ICU_INT_BIUE 17 /* bus interface unit error */ |
Definition at line 345 of file i80321reg.h.
#define ICU_INT_CPPM 8 /* core processor PMU */ |
Definition at line 354 of file i80321reg.h.
#define ICU_INT_DMA0_EOC 1 /* DMA0 end-of-chain */ |
Definition at line 361 of file i80321reg.h.
#define ICU_INT_DMA0_EOT 0 /* DMA0 end-of-transfer */ |
Definition at line 362 of file i80321reg.h.
#define ICU_INT_DMA0E 20 /* DMA Ch 0 error */ |
Definition at line 342 of file i80321reg.h.
#define ICU_INT_DMA1_EOC 3 /* DMA1 end-of-chain */ |
Definition at line 359 of file i80321reg.h.
#define ICU_INT_DMA1_EOT 2 /* DMA1 end-of-transfer */ |
Definition at line 360 of file i80321reg.h.
#define ICU_INT_DMA1E 21 /* DMA Ch 1 error */ |
Definition at line 341 of file i80321reg.h.
#define ICU_INT_HPI 31 /* high priority interrupt */ |
Definition at line 333 of file i80321reg.h.
#define ICU_INT_HWMASK |
Definition at line 364 of file i80321reg.h.
#define ICU_INT_I2C0 11 /* i2c unit 0 */ |
Definition at line 351 of file i80321reg.h.
#define ICU_INT_I2C1 12 /* i2c unit 1 */ |
Definition at line 350 of file i80321reg.h.
#define ICU_INT_MCUE 19 /* memory controller error */ |
Definition at line 343 of file i80321reg.h.
#define ICU_INT_MU 13 /* messaging unit */ |
Definition at line 349 of file i80321reg.h.
#define ICU_INT_MUE 24 /* msg unit error */ |
Definition at line 338 of file i80321reg.h.
#define ICU_INT_PMU 16 /* XScale PMU */ |
Definition at line 346 of file i80321reg.h.
#define ICU_INT_PPM 15 /* peripheral PMU */ |
Definition at line 347 of file i80321reg.h.
#define ICU_INT_SSP 25 /* SSP serial port */ |
Definition at line 337 of file i80321reg.h.
#define ICU_INT_TMR0 9 /* timer 0 */ |
Definition at line 353 of file i80321reg.h.
#define ICU_INT_TMR1 10 /* timer 1 */ |
Definition at line 352 of file i80321reg.h.
#define ICU_INT_XINT | ( | x | ) | ((x) + ICU_INT_XINT0) |
Definition at line 335 of file i80321reg.h.
#define ICU_INT_XINT0 27 /* external interrupts */ |
Definition at line 334 of file i80321reg.h.
#define ICU_PIRSR 0x01ec |
Definition at line 324 of file i80321reg.h.
#define MCISR_ECC_ERR0 (1U << 0) |
Definition at line 279 of file i80321reg.h.
#define MCISR_ECC_ERR1 (1U << 1) |
Definition at line 280 of file i80321reg.h.
#define MCISR_ECC_ERRN (1U << 2) |
Definition at line 281 of file i80321reg.h.
#define MCU_ABDDSR 0x80 /* Addr Bus Pull-down Drive Strength */ |
Definition at line 250 of file i80321reg.h.
#define MCU_ABUDSR 0x7c /* Addr Bus Pull-up Drive Strength */ |
Definition at line 249 of file i80321reg.h.
#define MCU_CDDSR 0x60 /* Clock Pull-down Drive Strength */ |
Definition at line 242 of file i80321reg.h.
#define MCU_CEDDSR 0x68 /* Clock En Pull-down Drive Strength */ |
Definition at line 244 of file i80321reg.h.
#define MCU_CEUDSR 0x64 /* Clock En Pull-up Drive Strength */ |
Definition at line 243 of file i80321reg.h.
#define MCU_CSDDSR 0x70 /* Chip Sel Pull-down Drive Strength */ |
Definition at line 246 of file i80321reg.h.
#define MCU_CSUDSR 0x6c /* Chip Sel Pull-up Drive Strength */ |
Definition at line 245 of file i80321reg.h.
#define MCU_CUDSR 0x5c /* Clock Pull-up Drive Strength */ |
Definition at line 241 of file i80321reg.h.
#define MCU_DBDDSR 0x58 /* Data Bus Pull-down Drive Strength */ |
Definition at line 240 of file i80321reg.h.
#define MCU_DBUDSR 0x54 /* Data Bus Pull-up Drive Strength */ |
Definition at line 239 of file i80321reg.h.
#define MCU_DSDR 0x84 /* Data Strobe Delay Register */ |
Definition at line 251 of file i80321reg.h.
#define MCU_ECAR0 0x40 /* ECC address 0 */ |
Definition at line 234 of file i80321reg.h.
#define MCU_ECAR1 0x44 /* ECC address 1 */ |
Definition at line 235 of file i80321reg.h.
#define MCU_ECCR 0x34 /* ECC Control Register */ |
Definition at line 231 of file i80321reg.h.
#define MCU_ECTST 0x48 /* ECC test register */ |
Definition at line 236 of file i80321reg.h.
#define MCU_ELOG0 0x38 /* ECC Log 0 */ |
Definition at line 232 of file i80321reg.h.
#define MCU_ELOG1 0x3c /* ECC Log 1 */ |
Definition at line 233 of file i80321reg.h.
#define MCU_MCISR 0x4c /* MCU Interrupt Status Register */ |
Definition at line 237 of file i80321reg.h.
#define MCU_REDDSR 0x78 /* Rx En Pull-down Drive Strength */ |
Definition at line 248 of file i80321reg.h.
#define MCU_REDR 0x88 /* Rx Enable Delay Register */ |
Definition at line 252 of file i80321reg.h.
#define MCU_REUDSR 0x74 /* Rx En Pull-up Drive Strength */ |
Definition at line 247 of file i80321reg.h.
#define MCU_RFR 0x50 /* Refresh Frequency Register */ |
Definition at line 238 of file i80321reg.h.
#define MCU_SBR0 0x0c /* SDRAM Boundary 0 */ |
Definition at line 229 of file i80321reg.h.
#define MCU_SBR1 0x10 /* SDRAM Boundary 1 */ |
Definition at line 230 of file i80321reg.h.
#define MCU_SDBR 0x08 /* SDRAM Base Register */ |
Definition at line 228 of file i80321reg.h.
#define MCU_SDCR 0x04 /* DDR SDRAM Control Register */ |
Definition at line 227 of file i80321reg.h.
#define MCU_SDIR 0x00 /* DDR SDRAM Init. Register */ |
Definition at line 226 of file i80321reg.h.
#define MU_IAR 0x0080 /* MU Index Address Register */ |
Definition at line 485 of file i80321reg.h.
#define MU_IDR 0x0020 /* MU Inbound Doorbell Register */ |
Definition at line 469 of file i80321reg.h.
#define MU_IFHPR 0x0060 /* MU Inbound Free Head Pointer Reg */ |
Definition at line 477 of file i80321reg.h.
#define MU_IFTPR 0x0064 /* MU Inbound Free Tail Pointer Reg */ |
Definition at line 478 of file i80321reg.h.
#define MU_IIMR 0x0028 /* MU Inbound Interrupt Mask Reg */ |
Definition at line 471 of file i80321reg.h.
#define MU_IIMR_EDI (1 << 3) /* Error Doorbell Interrupt */ |
Definition at line 490 of file i80321reg.h.
#define MU_IIMR_IDI (1 << 2) /* Inbound Doorbell Interrupt */ |
Definition at line 491 of file i80321reg.h.
#define MU_IIMR_IM0I (1 << 0) /* Inbound Message 0 Interrupt */ |
Definition at line 493 of file i80321reg.h.
#define MU_IIMR_IM1I (1 << 1) /* Inbound Message 1 Interrupt */ |
Definition at line 492 of file i80321reg.h.
#define MU_IIMR_IPQI (1 << 4) /* Inbound Post Queue Interrupt */ |
Definition at line 489 of file i80321reg.h.
#define MU_IIMR_IRI (1 << 6) /* Index Register Interrupt */ |
Definition at line 487 of file i80321reg.h.
#define MU_IIMR_OFQFI (1 << 5) /* Outbound Free Queue Full Int. */ |
Definition at line 488 of file i80321reg.h.
#define MU_IISR 0x0024 /* MU Inbound Interrupt Status Reg */ |
Definition at line 470 of file i80321reg.h.
#define MU_IMR0 0x0010 /* MU Inbound Message Register 0 */ |
Definition at line 465 of file i80321reg.h.
#define MU_IMR1 0x0014 /* MU Inbound Message Register 1 */ |
Definition at line 466 of file i80321reg.h.
#define MU_IPHPR 0x0068 /* MU Inbound Post Head Pointer Reg */ |
Definition at line 479 of file i80321reg.h.
#define MU_IPTPR 0x006c /* MU Inbound Post Tail Pointer Reg */ |
Definition at line 480 of file i80321reg.h.
#define MU_MUCR 0x0050 /* MU Configuration Register */ |
Definition at line 475 of file i80321reg.h.
#define MU_ODR 0x002c /* MU Outbound Doorbell Register */ |
Definition at line 472 of file i80321reg.h.
#define MU_OFHPR 0x0070 /* MU Outbound Free Head Pointer Reg */ |
Definition at line 481 of file i80321reg.h.
#define MU_OFTPR 0x0074 /* MU Outbound Free Tail Pointer Reg */ |
Definition at line 482 of file i80321reg.h.
#define MU_OIMR 0x0034 /* MU Outbound Interrupt Mask Reg */ |
Definition at line 474 of file i80321reg.h.
#define MU_OISR 0x0030 /* MU Outbound Interrupt Status Reg */ |
Definition at line 473 of file i80321reg.h.
#define MU_OMR0 0x0018 /* MU Outbound Message Register 0 */ |
Definition at line 467 of file i80321reg.h.
#define MU_OMR1 0x001c /* MU Outbound Message Register 1 */ |
Definition at line 468 of file i80321reg.h.
#define MU_OPHPR 0x0078 /* MU Outbound Post Head Pointer Reg */ |
Definition at line 483 of file i80321reg.h.
#define MU_OPTPR 0x007c /* MU Outbound Post Tail Pointer Reg */ |
Definition at line 484 of file i80321reg.h.
#define MU_QBAR 0x0054 /* MU Queue Base Address Register */ |
Definition at line 476 of file i80321reg.h.
#define PBIU_BASE_MASK 0xfffff000U |
Definition at line 458 of file i80321reg.h.
#define PBIU_DSCR 0x38 /* PBIU Drive Strength Control Reg. */ |
Definition at line 432 of file i80321reg.h.
#define PBIU_MBR0 0x40 /* PBIU Memory-less Boot Reg. 0 */ |
Definition at line 433 of file i80321reg.h.
#define PBIU_MBR1 0x60 /* PBIU Memory-less Boot Reg. 1 */ |
Definition at line 434 of file i80321reg.h.
#define PBIU_MBR2 0x64 /* PBIU Memory-less Boot Reg. 2 */ |
Definition at line 435 of file i80321reg.h.
#define PBIU_PBARx_ADWAIT12 (2 << 2) |
Definition at line 448 of file i80321reg.h.
#define PBIU_PBARx_ADWAIT16 (3 << 2) |
Definition at line 449 of file i80321reg.h.
#define PBIU_PBARx_ADWAIT20 (4 << 2) |
Definition at line 450 of file i80321reg.h.
#define PBIU_PBARx_ADWAIT4 (0 << 2) |
Definition at line 446 of file i80321reg.h.
#define PBIU_PBARx_ADWAIT8 (1 << 2) |
Definition at line 447 of file i80321reg.h.
#define PBIU_PBARx_FWE (1 << 9) |
Definition at line 457 of file i80321reg.h.
#define PBIU_PBARx_RCWAIT1 (0 << 6) |
Definition at line 451 of file i80321reg.h.
#define PBIU_PBARx_RCWAIT12 (3 << 6) |
Definition at line 454 of file i80321reg.h.
#define PBIU_PBARx_RCWAIT16 (4 << 6) |
Definition at line 455 of file i80321reg.h.
#define PBIU_PBARx_RCWAIT20 (5 << 6) |
Definition at line 456 of file i80321reg.h.
#define PBIU_PBARx_RCWAIT4 (1 << 6) |
Definition at line 452 of file i80321reg.h.
#define PBIU_PBARx_RCWAIT8 (2 << 6) |
Definition at line 453 of file i80321reg.h.
#define PBIU_PBARx_WIDTH16 (1 << 0) |
Definition at line 444 of file i80321reg.h.
#define PBIU_PBARx_WIDTH32 (2 << 0) |
Definition at line 445 of file i80321reg.h.
#define PBIU_PBARx_WIDTH8 (0 << 0) |
Definition at line 443 of file i80321reg.h.
#define PBIU_PBBAR0 0x08 /* PBIU Base Address Register 0 */ |
Definition at line 420 of file i80321reg.h.
#define PBIU_PBBAR1 0x10 /* PBIU Base Address Register 1 */ |
Definition at line 422 of file i80321reg.h.
#define PBIU_PBBAR2 0x18 /* PBIU Base Address Register 2 */ |
Definition at line 424 of file i80321reg.h.
#define PBIU_PBBAR3 0x20 /* PBIU Base Address Register 3 */ |
Definition at line 426 of file i80321reg.h.
#define PBIU_PBBAR4 0x28 /* PBIU Base Address Register 4 */ |
Definition at line 428 of file i80321reg.h.
#define PBIU_PBBAR5 0x30 /* PBIU Base Address Register 5 */ |
Definition at line 430 of file i80321reg.h.
#define PBIU_PBCR 0x00 /* PBIU Control Register */ |
Definition at line 419 of file i80321reg.h.
#define PBIU_PBCR_PBBEN (1 << 3) |
Definition at line 441 of file i80321reg.h.
#define PBIU_PBCR_PBI100 (1 << 1) |
Definition at line 438 of file i80321reg.h.
#define PBIU_PBCR_PBI33 (3 << 1) |
Definition at line 440 of file i80321reg.h.
#define PBIU_PBCR_PBI66 (2 << 1) |
Definition at line 439 of file i80321reg.h.
#define PBIU_PBCR_PBIEN (1 << 0) |
Definition at line 437 of file i80321reg.h.
#define PBIU_PBLR0 0x0c /* PBIU Limit Register 0 */ |
Definition at line 421 of file i80321reg.h.
#define PBIU_PBLR1 0x14 /* PBIU Limit Register 1 */ |
Definition at line 423 of file i80321reg.h.
#define PBIU_PBLR2 0x1c /* PBIU Limit Register 2 */ |
Definition at line 425 of file i80321reg.h.
#define PBIU_PBLR3 0x24 /* PBIU Limit Register 3 */ |
Definition at line 427 of file i80321reg.h.
#define PBIU_PBLR4 0x2c /* PBIU Limit Register 4 */ |
Definition at line 429 of file i80321reg.h.
#define PBIU_PBLR5 0x34 /* PBIU Limit Register 5 */ |
Definition at line 431 of file i80321reg.h.
#define PBIU_PBLRx_SIZE | ( | x | ) | (~((x) - 1)) |
Definition at line 460 of file i80321reg.h.
#define PCIXCMD_DPERE (1U << 0) |
Definition at line 209 of file i80321reg.h.
#define PCIXCMD_ERO (1U << 1) |
Definition at line 208 of file i80321reg.h.
#define PCIXCMD_MMRBC_1024 (1 << 2) |
Definition at line 204 of file i80321reg.h.
#define PCIXCMD_MMRBC_2048 (2 << 2) |
Definition at line 205 of file i80321reg.h.
#define PCIXCMD_MMRBC_4096 (3 << 2) |
Definition at line 206 of file i80321reg.h.
#define PCIXCMD_MMRBC_512 (0 << 2) |
Definition at line 203 of file i80321reg.h.
#define PCIXCMD_MMRBC_MASK (3 << 2) |
Definition at line 207 of file i80321reg.h.
#define PCIXCMD_MOST_1 (0 << 4) |
Definition at line 194 of file i80321reg.h.
#define PCIXCMD_MOST_12 (5 << 4) |
Definition at line 199 of file i80321reg.h.
#define PCIXCMD_MOST_16 (6 << 4) |
Definition at line 200 of file i80321reg.h.
#define PCIXCMD_MOST_2 (1 << 4) |
Definition at line 195 of file i80321reg.h.
#define PCIXCMD_MOST_3 (2 << 4) |
Definition at line 196 of file i80321reg.h.
#define PCIXCMD_MOST_32 (7 << 4) |
Definition at line 201 of file i80321reg.h.
#define PCIXCMD_MOST_4 (3 << 4) |
Definition at line 197 of file i80321reg.h.
#define PCIXCMD_MOST_8 (4 << 4) |
Definition at line 198 of file i80321reg.h.
#define PCIXCMD_MOST_MASK (7 << 4) |
Definition at line 202 of file i80321reg.h.
#define PCIXSR_133_CAP (1U << 17) |
Definition at line 217 of file i80321reg.h.
#define PCIXSR_32PCI (1U << 16) /* 0 = 32, 1 = 64 */ |
Definition at line 218 of file i80321reg.h.
#define PCIXSR_BUSNO | ( | x | ) | (((x) & 0xff00) >> 8) |
Definition at line 219 of file i80321reg.h.
#define PCIXSR_COMPLEX (1U << 20) |
Definition at line 214 of file i80321reg.h.
#define PCIXSR_DEVNO | ( | x | ) | (((x) & 0xf8) >> 3) |
Definition at line 220 of file i80321reg.h.
#define PCIXSR_DMCRS_MASK (7 << 26) |
Definition at line 212 of file i80321reg.h.
#define PCIXSR_DMOST_MASK (7 << 23) |
Definition at line 213 of file i80321reg.h.
#define PCIXSR_FUNCNO | ( | x | ) | ((x) & 0x7) |
Definition at line 221 of file i80321reg.h.
#define PCIXSR_RSCEM (1U << 29) |
Definition at line 211 of file i80321reg.h.
#define PCIXSR_SCD (1U << 18) |
Definition at line 216 of file i80321reg.h.
#define PCIXSR_USC (1U << 19) |
Definition at line 215 of file i80321reg.h.
#define PCSR_BUS64 (1U << 8) |
Definition at line 161 of file i80321reg.h.
#define PCSR_BUS66 (1U << 10) |
Definition at line 160 of file i80321reg.h.
#define PCSR_CCR (1U << 2) |
Definition at line 164 of file i80321reg.h.
#define PCSR_CPR (1U << 1) |
Definition at line 165 of file i80321reg.h.
#define PCSR_DAAAPE (1U << 18) |
Definition at line 151 of file i80321reg.h.
#define PCSR_DTV (1U << 12) |
Definition at line 159 of file i80321reg.h.
#define PCSR_IRTQB (1U << 14) |
Definition at line 158 of file i80321reg.h.
#define PCSR_OTQB (1U << 15) |
Definition at line 157 of file i80321reg.h.
#define PCSR_PCI_X_CAP (3U << 16) |
Definition at line 152 of file i80321reg.h.
#define PCSR_PCI_X_CAP_100 (2U << 16) |
Definition at line 155 of file i80321reg.h.
#define PCSR_PCI_X_CAP_133 (3U << 16) |
Definition at line 156 of file i80321reg.h.
#define PCSR_PCI_X_CAP_66 (1U << 16) |
Definition at line 154 of file i80321reg.h.
#define PCSR_PCI_X_CAP_BORING (0 << 16) |
Definition at line 153 of file i80321reg.h.
#define PCSR_RIB (1U << 5) |
Definition at line 162 of file i80321reg.h.
#define PCSR_RPB (1U << 4) |
Definition at line 163 of file i80321reg.h.
#define SBRx_BOUND 0x0000003f |
Definition at line 258 of file i80321reg.h.
#define SBRx_TECH (1U << 31) |
Definition at line 257 of file i80321reg.h.
#define SDCR_BUSWIDTH (1U << 2) /* 0 = 64, 1 = 32 */ |
Definition at line 255 of file i80321reg.h.
Definition at line 254 of file i80321reg.h.
#define SSP_SSCR0 0x00 /* SSC control 0 */ |
Definition at line 374 of file i80321reg.h.
#define SSP_SSCR0_DSIZE | ( | x | ) | ((x) - 1)/* data size: 4..16 */ |
Definition at line 380 of file i80321reg.h.
Definition at line 385 of file i80321reg.h.
#define SSP_SSCR0_FRF_rsvd (3U << 4)/* reserved */ |
Definition at line 384 of file i80321reg.h.
#define SSP_SSCR0_FRF_SPI (0 << 4) /* Motorola Serial Periph Iface */ |
Definition at line 381 of file i80321reg.h.
#define SSP_SSCR0_FRF_SSP (1U << 4)/* TI Sync. Serial Protocol */ |
Definition at line 382 of file i80321reg.h.
#define SSP_SSCR0_FRF_UWIRE (2U << 4)/* NatSemi Microwire */ |
Definition at line 383 of file i80321reg.h.
#define SSP_SSCR0_SCR | ( | x | ) | ((x) << 8)/* serial clock rate */ |
Definition at line 387 of file i80321reg.h.
#define SSP_SSCR0_SSE (1U << 7)/* sync. serial port enable */ |
Definition at line 386 of file i80321reg.h.
#define SSP_SSCR1 0x04 /* SSC control 1 */ |
Definition at line 375 of file i80321reg.h.
#define SSP_SSCR1_EFWR (1U << 14)/* enab. FIFO write/read */ |
Definition at line 399 of file i80321reg.h.
#define SSP_SSCR1_LBM (1U << 2)/* loopback mode enable */ |
Definition at line 393 of file i80321reg.h.
#define SSP_SSCR1_MWDS |
Definition at line 396 of file i80321reg.h.
#define SSP_SSCR1_RFT (((x) - 1) << 10)/* Rx FIFO threshold */ |
Definition at line 398 of file i80321reg.h.
Definition at line 391 of file i80321reg.h.
#define SSP_SSCR1_SPH |
Definition at line 395 of file i80321reg.h.
#define SSP_SSCR1_SPO (1U << 3)/* Moto SPI SSCLK pol. (1 = high) */ |
Definition at line 394 of file i80321reg.h.
#define SSP_SSCR1_STRF |
Definition at line 400 of file i80321reg.h.
#define SSP_SSCR1_TFT (((x) - 1) << 6) /* Tx FIFO threshold */ |
Definition at line 397 of file i80321reg.h.
Definition at line 392 of file i80321reg.h.
#define SSP_SSDR 0x10 /* SSP data */ |
Definition at line 378 of file i80321reg.h.
#define SSP_SSITR 0x0c /* SSP interrupt test */ |
Definition at line 377 of file i80321reg.h.
#define SSP_SSITR_TRFS (1U << 6)/* Test Rx FIFO service */ |
Definition at line 412 of file i80321reg.h.
#define SSP_SSITR_TROR (1U << 7)/* Test Rx overrun */ |
Definition at line 413 of file i80321reg.h.
#define SSP_SSITR_TTFS (1U << 5)/* Test Tx FIFO service */ |
Definition at line 411 of file i80321reg.h.
#define SSP_SSSR 0x08 /* SSP status */ |
Definition at line 376 of file i80321reg.h.
#define SSP_SSSR_BSY (1U << 4)/* SSP is busy */ |
Definition at line 404 of file i80321reg.h.
#define SSP_SSSR_RFL | ( | x | ) | (((x) >> 12) & 0xf)/* Rx FIFO level */ |
Definition at line 409 of file i80321reg.h.
#define SSP_SSSR_RFS (1U << 6)/* Rx FIFO service request */ |
Definition at line 406 of file i80321reg.h.
#define SSP_SSSR_RNE (1U << 3)/* Rx FIFO not empty */ |
Definition at line 403 of file i80321reg.h.
#define SSP_SSSR_ROR (1U << 7)/* Rx FIFO overrun */ |
Definition at line 407 of file i80321reg.h.
#define SSP_SSSR_TFL | ( | x | ) | (((x) >> 8) & 0xf) /* Tx FIFO level */ |
Definition at line 408 of file i80321reg.h.
#define SSP_SSSR_TFS (1U << 5)/* Tx FIFO service request */ |
Definition at line 405 of file i80321reg.h.
#define SSP_SSSR_TNF (1U << 2)/* Tx FIFO not full */ |
Definition at line 402 of file i80321reg.h.
#define TISR_TMR0 (1U << 0) |
Definition at line 308 of file i80321reg.h.
#define TISR_TMR1 (1U << 1) |
Definition at line 309 of file i80321reg.h.
#define TMRx_CSEL_CORE (0 << 4) |
Definition at line 303 of file i80321reg.h.
#define TMRx_CSEL_CORE_div16 (3 << 4) |
Definition at line 306 of file i80321reg.h.
#define TMRx_CSEL_CORE_div4 (1 << 4) |
Definition at line 304 of file i80321reg.h.
#define TMRx_CSEL_CORE_div8 (2 << 4) |
Definition at line 305 of file i80321reg.h.
#define TMRx_ENABLE (1U << 1) |
Definition at line 301 of file i80321reg.h.
#define TMRx_RELOAD (1U << 2) |
Definition at line 302 of file i80321reg.h.
#define TMRx_TC (1U << 0) |
Definition at line 300 of file i80321reg.h.
#define VERDE_AAU_BASE 0x0800 |
Definition at line 99 of file i80321reg.h.
#define VERDE_AAU_SIZE 0x0100 |
Definition at line 100 of file i80321reg.h.
#define VERDE_ATU_BASE 0x0100 |
Definition at line 78 of file i80321reg.h.
#define VERDE_ATU_SIZE 0x0100 |
Definition at line 79 of file i80321reg.h.
#define VERDE_DMA_BASE 0x0400 |
Definition at line 84 of file i80321reg.h.
#define VERDE_DMA_BASE0 (VERDE_DMA_BASE + 0x00) |
Definition at line 85 of file i80321reg.h.
#define VERDE_DMA_BASE1 (VERDE_DMA_BASE + 0x40) |
Definition at line 86 of file i80321reg.h.
#define VERDE_DMA_CHSIZE 0x0040 |
Definition at line 88 of file i80321reg.h.
#define VERDE_DMA_SIZE 0x0100 |
Definition at line 87 of file i80321reg.h.
#define VERDE_EXTMEM_BASE 0x90020000UL |
Definition at line 69 of file i80321reg.h.
#define VERDE_I2C_BASE 0x1680 |
Definition at line 102 of file i80321reg.h.
#define VERDE_I2C_BASE0 (VERDE_I2C_BASE + 0x00) |
Definition at line 103 of file i80321reg.h.
#define VERDE_I2C_BASE1 (VERDE_I2C_BASE + 0x20) |
Definition at line 104 of file i80321reg.h.
#define VERDE_I2C_CHSIZE 0x0020 |
Definition at line 106 of file i80321reg.h.
#define VERDE_I2C_SIZE 0x0080 |
Definition at line 105 of file i80321reg.h.
#define VERDE_MCU_BASE 0x0500 |
Definition at line 90 of file i80321reg.h.
#define VERDE_MCU_SIZE 0x0100 |
Definition at line 91 of file i80321reg.h.
#define VERDE_MU_BASE 0x0300 |
Definition at line 81 of file i80321reg.h.
#define VERDE_MU_SIZE 0x0100 |
Definition at line 82 of file i80321reg.h.
#define VERDE_OUT_DIRECT_WIN_BASE 0x00000000UL |
Definition at line 58 of file i80321reg.h.
#define VERDE_OUT_DIRECT_WIN_SIZE 0x80000000UL |
Definition at line 59 of file i80321reg.h.
#define VERDE_OUT_XLATE_IO_WIN0_BASE 0x90000000UL |
Definition at line 67 of file i80321reg.h.
#define VERDE_OUT_XLATE_IO_WIN_SIZE 0x00010000UL |
Definition at line 62 of file i80321reg.h.
#define VERDE_OUT_XLATE_MEM_WIN0_BASE 0x80000000UL |
Definition at line 64 of file i80321reg.h.
#define VERDE_OUT_XLATE_MEM_WIN1_BASE 0x84000000UL |
Definition at line 65 of file i80321reg.h.
#define VERDE_OUT_XLATE_MEM_WIN_SIZE 0x04000000UL |
Definition at line 61 of file i80321reg.h.
#define VERDE_PBIU_BASE 0x0680 |
Definition at line 96 of file i80321reg.h.
#define VERDE_PBIU_SIZE 0x0080 |
Definition at line 97 of file i80321reg.h.
#define VERDE_PMMR_BASE 0xffffe000UL |
Definition at line 71 of file i80321reg.h.
#define VERDE_PMMR_SIZE 0x00001700UL |
Definition at line 72 of file i80321reg.h.
#define VERDE_SSP_BASE 0x0600 |
Definition at line 93 of file i80321reg.h.
#define VERDE_SSP_SIZE 0x0080 |
Definition at line 94 of file i80321reg.h.
#define WDTCR_ENABLE1 0x1e1e1e1e |
Definition at line 311 of file i80321reg.h.
#define WDTCR_ENABLE2 0xe1e1e1e1 |
Definition at line 312 of file i80321reg.h.