tc_ioasicreg.h Source File
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74 #define IOASIC_SLOT_0_START 0x000000
75 #define IOASIC_SLOT_1_START 0x040000
76 #define IOASIC_SLOT_2_START 0x080000
77 #define IOASIC_SLOT_3_START 0x0c0000
78 #define IOASIC_SLOT_4_START 0x100000
79 #define IOASIC_SLOT_5_START 0x140000
80 #define IOASIC_SLOT_6_START 0x180000
81 #define IOASIC_SLOT_7_START 0x1c0000
82 #define IOASIC_SLOT_8_START 0x200000
83 #define IOASIC_SLOT_9_START 0x240000
84 #define IOASIC_SLOT_10_START 0x280000
85 #define IOASIC_SLOT_11_START 0x2c0000
86 #define IOASIC_SLOT_12_START 0x300000
87 #define IOASIC_SLOT_13_START 0x340000
88 #define IOASIC_SLOT_14_START 0x380000
89 #define IOASIC_SLOT_15_START 0x3c0000
90 #define IOASIC_SLOTS_END 0x3fffff
96 #define IOASIC_SCSI_DMAPTR IOASIC_SLOT_1_START+0x000
97 #define IOASIC_SCSI_NEXTPTR IOASIC_SLOT_1_START+0x010
98 #define IOASIC_LANCE_DMAPTR IOASIC_SLOT_1_START+0x020
99 #define IOASIC_SCC_T1_DMAPTR IOASIC_SLOT_1_START+0x030
100 #define IOASIC_SCC_R1_DMAPTR IOASIC_SLOT_1_START+0x040
101 #define IOASIC_SCC_T2_DMAPTR IOASIC_SLOT_1_START+0x050
102 #define IOASIC_SCC_R2_DMAPTR IOASIC_SLOT_1_START+0x060
103 #define IOASIC_FLOPPY_DMAPTR IOASIC_SLOT_1_START+0x070
104 #define IOASIC_ISDN_X_DMAPTR IOASIC_SLOT_1_START+0x080
105 #define IOASIC_ISDN_X_NEXTPTR IOASIC_SLOT_1_START+0x090
106 #define IOASIC_ISDN_R_DMAPTR IOASIC_SLOT_1_START+0x0a0
107 #define IOASIC_ISDN_R_NEXTPTR IOASIC_SLOT_1_START+0x0b0
108 #define IOASIC_BUFF0 IOASIC_SLOT_1_START+0x0c0
109 #define IOASIC_BUFF1 IOASIC_SLOT_1_START+0x0d0
110 #define IOASIC_BUFF2 IOASIC_SLOT_1_START+0x0e0
111 #define IOASIC_BUFF3 IOASIC_SLOT_1_START+0x0f0
112 #define IOASIC_CSR IOASIC_SLOT_1_START+0x100
113 #define IOASIC_INTR IOASIC_SLOT_1_START+0x110
114 #define IOASIC_IMSK IOASIC_SLOT_1_START+0x120
115 #define IOASIC_CURADDR IOASIC_SLOT_1_START+0x130
116 #define IOASIC_ISDN_X_DATA IOASIC_SLOT_1_START+0x140
117 #define IOASIC_ISDN_R_DATA IOASIC_SLOT_1_START+0x150
118 #define IOASIC_LANCE_DECODE IOASIC_SLOT_1_START+0x160
119 #define IOASIC_SCSI_DECODE IOASIC_SLOT_1_START+0x170
120 #define IOASIC_SCC0_DECODE IOASIC_SLOT_1_START+0x180
121 #define IOASIC_SCC1_DECODE IOASIC_SLOT_1_START+0x190
122 #define IOASIC_FLOPPY_DECODE IOASIC_SLOT_1_START+0x1a0
123 #define IOASIC_SCSI_SCR IOASIC_SLOT_1_START+0x1b0
124 #define IOASIC_SCSI_SDR0 IOASIC_SLOT_1_START+0x1c0
125 #define IOASIC_SCSI_SDR1 IOASIC_SLOT_1_START+0x1d0
126 #define IOASIC_CTR IOASIC_SLOT_1_START+0x1e0
129 #define IOASIC_CSR_DMAEN_T1 0x80000000
130 #define IOASIC_CSR_DMAEN_R1 0x40000000
131 #define IOASIC_CSR_DMAEN_T2 0x20000000
132 #define IOASIC_CSR_DMAEN_R2 0x10000000
133 #define IOASIC_CSR_FASTMODE 0x08000000
134 #define IOASIC_CSR_xxx 0x07800000
135 #define IOASIC_CSR_DS_xxx 0x0f800000
136 #define IOASIC_CSR_FLOPPY_DIR 0x00400000
137 #define IOASIC_CSR_DMAEN_FLOPPY 0x00200000
138 #define IOASIC_CSR_DMAEN_ISDN_T 0x00100000
139 #define IOASIC_CSR_DMAEN_ISDN_R 0x00080000
140 #define IOASIC_CSR_SCSI_DIR 0x00040000
141 #define IOASIC_CSR_DMAEN_SCSI 0x00020000
142 #define IOASIC_CSR_DMAEN_LANCE 0x00010000
144 #define IOASIC_CSR_DIAGDN 0x00008000
145 #define IOASIC_CSR_TXDIS_2 0x00004000
146 #define IOASIC_CSR_TXDIS_1 0x00002000
147 #define IOASIC_CSR_ISDN_ENABLE 0x00001000
148 #define IOASIC_CSR_SCC_ENABLE 0x00000800
149 #define IOASIC_CSR_RTC_ENABLE 0x00000400
150 #define IOASIC_CSR_SCSI_ENABLE 0x00000200
151 #define IOASIC_CSR_LANCE_ENABLE 0x00000100
154 #define IOASIC_INTR_T1_PAGE_END 0x80000000
155 #define IOASIC_INTR_T1_READ_E 0x40000000
156 #define IOASIC_INTR_R1_HALF_PAGE 0x20000000
157 #define IOASIC_INTR_R1_DMA_OVRUN 0x10000000
158 #define IOASIC_INTR_T2_PAGE_END 0x08000000
159 #define IOASIC_INTR_T2_READ_E 0x04000000
160 #define IOASIC_INTR_R2_HALF_PAGE 0x02000000
161 #define IOASIC_INTR_R2_DMA_OVRUN 0x01000000
162 #define IOASIC_INTR_FLOPPY_DMA_E 0x00800000
163 #define IOASIC_INTR_ISDN_TXLOAD 0x00400000
164 #define IOASIC_INTR_ISDN_RXLOAD 0x00200000
165 #define IOASIC_INTR_ISDN_OVRUN 0x00100000
166 #define IOASIC_INTR_SCSI_PTR_LOAD 0x00080000
167 #define IOASIC_INTR_SCSI_OVRUN 0x00040000
168 #define IOASIC_INTR_SCSI_READ_E 0x00020000
169 #define IOASIC_INTR_LANCE_READ_E 0x00010000
172 #define IOASIC_INTR_NVR_JUMPER 0x00004000
173 #define IOASIC_INTR_ISDN 0x00002000
174 #define IOASIC_INTR_NRMOD_JUMPER 0x00000400
175 #define IOASIC_INTR_SEC_CON 0x00000200
176 #define IOASIC_INTR_SCSI 0x00000200
177 #define IOASIC_INTR_LANCE 0x00000100
178 #define IOASIC_INTR_SCC_1 0x00000080
179 #define IOASIC_INTR_SCC_0 0x00000040
180 #define IOASIC_INTR_ALT_CON 0x00000008
181 #define IOASIC_INTR_300_OPT1 0x00000008
182 #define IOASIC_INTR_300_OPT0 0x00000004
186 #define IOASIC_DMA_ADDR(p) \
187 ((((p) << 3) & ~0x1f) | (((p) >> 29) & 0x1f))
188 #define IOASIC_DMA_BLOCKSIZE 0x1000
194 #define IOASIC_SCR_STATUS 0x00000004
195 #define IOASIC_SCR_WORD 0x00000003
199 #define IOASIC_DECODE_HW_ADDRESS 0x000003f0
200 #define IOASIC_DECODE_CHIP_SELECT 0x0000000f
205 #define IOASIC_SYS_ETHER_ADDRESS(base) ((base) + IOASIC_SLOT_2_START)
206 #define IOASIC_SYS_LANCE(base) ((base) + IOASIC_SLOT_3_START)
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