dev_dec5800.cc Source File
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56 #define DEV_DEC5800_LENGTH 0x1000
72 if (d->
csr & 0x10000000)
79 if (!(d->
csr & 0x10000000))
89 if (d->
csr & 0x8000) {
90 debug(
"[ dec5800: timer interrupt! ]\n");
102 uint64_t idata = 0, odata = 0;
114 debug(
"[ dec5800_vectors: read from 0x%02x: 0x%02x ]\n",
115 (
int)relative_addr, (
int)odata);
118 debug(
"[ dec5800_vectors: write to 0x%02x: 0x%02x ]\n",
119 (
int)relative_addr, (
int)idata);
131 uint64_t idata = 0, odata = 0;
140 switch (relative_addr) {
144 odata ^= random() & 0x10000;
145 debug(
"[ dec5800: read from csr: 0x%08x ]\n",
151 d->
csr &= ~0x20000000;
154 debug(
"[ dec5800: write to csr: 0x%08x ]\n",
160 debug(
"[ dec5800: read from 0x%08lx ]\n",
161 (
long)relative_addr);
163 debug(
"[ dec5800: write to 0x%08lx: 0x%08x ]\n",
164 (
long)relative_addr, (
int)idata);
191 for (i=0; i<32; i++) {
194 snprintf(n,
sizeof(n),
"%s.dec5800.%i",
196 memset(&templ, 0,
sizeof(templ));
209 devinit->
addr + 0x30000000, 0x100, dev_dec5800_vectors_access,
224 #define DEV_DECBI_LENGTH 0x20000
233 uint64_t idata = 0, odata = 0;
246 if (node_nr > 1 || node_nr >=
NNODEBI)
249 switch (relative_addr) {
266 debug(
"[ decbi: (node %i) read from BIREG_DTYPE:"
267 " 0x%x ]\n", node_nr, (
int)odata);
269 debug(
"[ decbi: (node %i) attempt to write to "
270 "BIREG_DTYPE: 0x%08x ]\n", node_nr, (
int)idata);
276 debug(
"[ decbi: (node %i) read from BIREG_"
277 "VAXBICSR: 0x%x ]\n", node_nr, (
int)odata);
279 d->
csr[node_nr] = idata;
280 debug(
"[ decbi: (node %i) attempt to write to "
281 "BIREG_VAXBICSR: 0x%08x ]\n", node_nr, (
int)idata);
287 debug(
"[ decbi: (node %i) read from 0xf4: "
288 "0x%x ]\n", node_nr, (
int)odata);
290 debug(
"[ decbi: (node %i) attempt to write "
291 "to 0xf4: 0x%08x ]\n", node_nr, (
int)idata);
296 debug(
"[ decbi: (node %i) read from unimplemented "
297 "0x%08lx ]\n", node_nr, (
long)relative_addr,
300 debug(
"[ decbi: (node %i) write to unimplemented "
301 "0x%08lx: 0x%08x ]\n", node_nr,
302 (
long)relative_addr, (
int)idata);
342 uint64_t idata = 0, odata = 0;
348 switch (relative_addr) {
371 debug(
"[ deccca: read from 0x%08lx ]\n",
372 (
long)relative_addr);
374 debug(
"[ deccca: write to 0x%08lx: 0x%08x ]\n",
375 (
long)relative_addr, (
int)idata);
420 uint64_t idata = 0, odata = 0;
433 switch (relative_addr) {
444 debug(
"[ decxmi: (node %i) read from XMI_TYPE: "
445 "0x%08x ]\n", node_nr, (
int)odata);
447 debug(
"[ decxmi: (node %i) write to XMI_TYPE: "
448 "0x%08x ]\n", node_nr, (
int)idata);
453 debug(
"[ decxmi: (node %i) read from XMI_BUSERR: "
454 "0x%08x ]\n", node_nr, (
int)odata);
456 debug(
"[ decxmi: (node %i) write to XMI_BUSERR: "
457 "0x%08x ]\n", node_nr, (
int)idata);
462 debug(
"[ decxmi: (node %i) read from XMI_FAIL: "
463 "0x%08x ]\n", node_nr, (
int)odata);
465 debug(
"[ decxmi: (node %i) write to XMI_FAIL: "
466 "0x%08x ]\n", node_nr, (
int)idata);
471 debug(
"[ decxmi: (node %i) read from REG 0xC: "
472 "0x%08x ]\n", node_nr, (
int)odata);
475 debug(
"[ decxmi: (node %i) write to REG 0xC: "
476 "0x%08x ]\n", node_nr, (
int)idata);
481 debug(
"[ decxmi: (node %i) read from unimplemented "
482 "0x%08lx ]\n", node_nr, (
long)relative_addr,
485 debug(
"[ decxmi: (node %i) write to unimplemented "
486 "0x%08lx: 0x%08x ]\n", node_nr,
487 (
long)relative_addr, (
int)idata);
#define INTERRUPT_CONNECT(name, istruct)
#define INTERRUPT_ASSERT(istruct)
void(* interrupt_deassert)(struct interrupt *)
DEVICE_ACCESS(dec5800_vectors)
void memory_device_register(struct memory *mem, const char *, uint64_t baseaddr, uint64_t len, int(*f)(struct cpu *, struct memory *, uint64_t, unsigned char *, size_t, int, void *), void *extra, int flags, unsigned char *dyntrans_data)
int dev_deccca_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *)
uint32_t reg_0xc[NNODEXMI]
void machine_add_tickfunction(struct machine *machine, void(*func)(struct cpu *, void *), void *extra, int clockshift)
uint64_t memory_readmax64(struct cpu *cpu, unsigned char *buf, int len)
void dec5800_interrupt_deassert(struct interrupt *interrupt)
void dev_deccca_init(struct memory *mem, uint64_t baseaddr)
#define DEV_DECXMI_LENGTH
void dec5800_interrupt_assert(struct interrupt *interrupt)
#define INTERRUPT_DEASSERT(istruct)
void(* interrupt_assert)(struct interrupt *)
void interrupt_handler_register(struct interrupt *templ)
struct interrupt timer_irq
void memory_writemax64(struct cpu *cpu, unsigned char *buf, int len, uint64_t data)
#define DEV_DECCCA_LENGTH
void dev_decxmi_init(struct memory *mem, uint64_t baseaddr)
#define DEV_DEC5800_LENGTH
int dev_decxmi_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *)
#define CHECK_ALLOCATION(ptr)
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