cpu_mips.h Source File
Back to the index.
Go to the documentation of this file.
68 #define INITIAL_PC 0xffffffffbfc00000ULL
69 #define INITIAL_STACK_POINTER (0xffffffffa0008000ULL - 256)
78 #define N_MIPS_COPROC_REGS 32
91 #define N_MIPS_FCRS 32
92 #define MIPS_FPU_FCIR 0
93 #define MIPS_FPU_FCCR 25
94 #define MIPS_FPU_FCSR 31
95 #define MIPS_FCSR_FCC0_SHIFT 23
96 #define MIPS_FCSR_FCC1_SHIFT 25
98 #define N_VADDR_TO_TLB_INDEX_ENTRIES (1 << 20)
113 #define N_MIPS_COPROCS 4
115 #define N_MIPS_GPRS 32
116 #define N_MIPS_FPRS 32
128 #define MIPS_REGISTER_NAMES { \
129 "zr", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
130 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
131 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
132 "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra" }
134 #define MIPS_GPR_ZERO 0
135 #define MIPS_GPR_AT 1
136 #define MIPS_GPR_V0 2
137 #define MIPS_GPR_V1 3
138 #define MIPS_GPR_A0 4
139 #define MIPS_GPR_A1 5
140 #define MIPS_GPR_A2 6
141 #define MIPS_GPR_A3 7
142 #define MIPS_GPR_T0 8
143 #define MIPS_GPR_T1 9
144 #define MIPS_GPR_T2 10
145 #define MIPS_GPR_T3 11
146 #define MIPS_GPR_T4 12
147 #define MIPS_GPR_T5 13
148 #define MIPS_GPR_T6 14
149 #define MIPS_GPR_T7 15
150 #define MIPS_GPR_S0 16
151 #define MIPS_GPR_S1 17
152 #define MIPS_GPR_S2 18
153 #define MIPS_GPR_S3 19
154 #define MIPS_GPR_S4 20
155 #define MIPS_GPR_S5 21
156 #define MIPS_GPR_S6 22
157 #define MIPS_GPR_S7 23
158 #define MIPS_GPR_T8 24
159 #define MIPS_GPR_T9 25
160 #define MIPS_GPR_K0 26
161 #define MIPS_GPR_K1 27
162 #define MIPS_GPR_GP 28
163 #define MIPS_GPR_SP 29
164 #define MIPS_GPR_FP 30
165 #define MIPS_GPR_RA 31
173 #define IMPOSSIBLE_PADDR 0x1212343456566767ULL
175 #define DEFAULT_PCACHE_SIZE 15
176 #define DEFAULT_PCACHE_LINESIZE 5
182 #define R3000_TAG_VALID 1
183 #define R3000_TAG_DIRTY 2
186 #define MIPS_IC_ENTRIES_SHIFT 10
188 #define MIPS_N_IC_ARGS 3
189 #define MIPS_INSTR_ALIGNMENT_SHIFT 2
190 #define MIPS_IC_ENTRIES_PER_PAGE (1 << MIPS_IC_ENTRIES_SHIFT)
191 #define MIPS_PC_TO_IC_ENTRY(a) (((a)>>MIPS_INSTR_ALIGNMENT_SHIFT) \
192 & (MIPS_IC_ENTRIES_PER_PAGE-1))
193 #define MIPS_ADDR_TO_PAGENR(a) ((a) >> (MIPS_IC_ENTRIES_SHIFT \
194 + MIPS_INSTR_ALIGNMENT_SHIFT))
199 #define MIPS_MAX_VPH_TLB_ENTRIES 192
227 int32_t count_register_read_count;
267 unsigned char *cache[2];
269 uint64_t cache_last_paddr[2];
271 int cache_linesize[2];
292 int writeflag, uint64_t *valuep,
int *match_register);
295 int running, uint64_t
addr);
297 int coproc_nr, uint64_t vaddr_vpn2,
298 int vaddr_asid,
int x_64);
308 uint64_t vaddr, uint64_t paddr0, uint64_t paddr1,
309 int valid0,
int valid1,
int dirty0,
int dirty1,
int global,
int asid,
310 int cachealgo0,
int cachealgo1);
312 struct mips_coproc *cp,
int reg_nr, uint64_t *ptr,
int select);
314 struct mips_coproc *cp,
int reg_nr, uint64_t *ptr,
int flag64,
321 uint32_t
function,
int unassemble_only,
int running);
326 int writeflag,
size_t len,
unsigned char *
data);
328 unsigned char *
data,
size_t len,
int writeflag,
int cache_flags);
331 uint64_t *return_addr,
int flags);
333 uint64_t *return_addr,
int flags);
335 uint64_t *return_addr,
int flags);
337 uint64_t *return_addr,
int flags);
339 uint64_t *return_addr,
int flags);
344 int is_left,
int wlen,
int store);
349 unsigned char *host_page,
int writeflag, uint64_t paddr_page);
354 unsigned char *host_page,
int writeflag, uint64_t paddr_page);
int last_written_tlb_index
uint64_t reg[N_MIPS_COPROC_REGS]
int compare_interrupts_pending
void coproc_tlbpr(struct cpu *cpu, int readflag)
#define VPH32(arch, ARCH)
int cache_secondary_linesize
void mips_cpu_tlbdump(struct machine *m, int x, int rawflag)
void coproc_register_read(struct cpu *cpu, struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int select)
void coproc_rfe(struct cpu *cpu)
int mips_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, int running, uint64_t addr)
struct mips_coproc * mips_coproc_new(struct cpu *cpu, int coproc_nr)
void mips_cpu_list_available_types(void)
int mips32_run_instr(struct cpu *cpu)
#define N_MIPS_COPROC_REGS
#define DYNTRANS_MISC64_DECLARATIONS(arch, ARCH, tlbindextype)
void coproc_eret(struct cpu *cpu)
int cache_picache_linesize
void mips_cpu_interrupt_assert(struct interrupt *interrupt)
void mips32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int)
int translate_v2p_mmu3k(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
#define DYNTRANS_MISC_DECLARATIONS(arch, ARCH, addrtype)
void mips_unaligned_loadstore(struct cpu *cpu, struct mips_instr_call *ic, int is_left, int wlen, int store)
void mips32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page)
void mips_cpu_dumpinfo(struct cpu *cpu)
int mips_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags)
void coproc_register_write(struct cpu *cpu, struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int flag64, int select)
#define DYNTRANS_ITC(arch)
int mips_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib)
uint64_t fcr[N_MIPS_FCRS]
int memory_cache_R3000(struct cpu *cpu, int cache, uint64_t paddr, int writeflag, size_t len, unsigned char *data)
void mips_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page)
#define VPH_TLBS(arch, ARCH)
int mips_run_instr(struct cpu *cpu)
struct arm_instr_call * ic
int translate_v2p_mmu4100(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
void mips_cpu_register_match(struct machine *m, char *name, int writeflag, uint64_t *valuep, int *match_register)
int translate_v2p_mmu8k(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
void coproc_function(struct cpu *cpu, struct mips_coproc *cp, int cpnr, uint32_t function, int unassemble_only, int running)
void mips_coproc_tlb_set_entry(struct cpu *cpu, int entrynr, int size, uint64_t vaddr, uint64_t paddr0, uint64_t paddr1, int valid0, int valid1, int dirty0, int dirty1, int global, int asid, int cachealgo0, int cachealgo1)
void mips_cpu_exception(struct cpu *cpu, int exccode, int tlb, uint64_t vaddr, int coproc_nr, uint64_t vaddr_vpn2, int vaddr_asid, int x_64)
uint64_t cop0_config_select1
#define VPH64(arch, ARCH)
int cache_pdcache_linesize
void mips32_invalidate_code_translation(struct cpu *cpu, uint64_t, int)
int mips_cpu_run(struct emul *emul, struct machine *machine)
void coproc_tlbwri(struct cpu *cpu, int randomflag)
void mips_invalidate_translation_caches(struct cpu *cpu, uint64_t, int)
void mips_invalidate_code_translation(struct cpu *cpu, uint64_t, int)
void mips_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
int translate_v2p_generic(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
void mips_cpu_interrupt_deassert(struct interrupt *interrupt)
int mips_cpu_family_init(struct cpu_family *)
int translate_v2p_mmu10k(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
Generated on Tue Aug 25 2020 19:25:06 for GXemul by
1.8.18