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Macros | |
#define | IOASIC_SLOT_0_START 0x000000 |
#define | IOASIC_SLOT_1_START 0x040000 |
#define | IOASIC_SLOT_2_START 0x080000 |
#define | IOASIC_SLOT_3_START 0x0c0000 |
#define | IOASIC_SLOT_4_START 0x100000 |
#define | IOASIC_SLOT_5_START 0x140000 |
#define | IOASIC_SLOT_6_START 0x180000 |
#define | IOASIC_SLOT_7_START 0x1c0000 |
#define | IOASIC_SLOT_8_START 0x200000 |
#define | IOASIC_SLOT_9_START 0x240000 |
#define | IOASIC_SLOT_10_START 0x280000 |
#define | IOASIC_SLOT_11_START 0x2c0000 |
#define | IOASIC_SLOT_12_START 0x300000 |
#define | IOASIC_SLOT_13_START 0x340000 |
#define | IOASIC_SLOT_14_START 0x380000 |
#define | IOASIC_SLOT_15_START 0x3c0000 |
#define | IOASIC_SLOTS_END 0x3fffff |
#define | IOASIC_SCSI_DMAPTR IOASIC_SLOT_1_START+0x000 |
#define | IOASIC_SCSI_NEXTPTR IOASIC_SLOT_1_START+0x010 |
#define | IOASIC_LANCE_DMAPTR IOASIC_SLOT_1_START+0x020 |
#define | IOASIC_SCC_T1_DMAPTR IOASIC_SLOT_1_START+0x030 |
#define | IOASIC_SCC_R1_DMAPTR IOASIC_SLOT_1_START+0x040 |
#define | IOASIC_SCC_T2_DMAPTR IOASIC_SLOT_1_START+0x050 |
#define | IOASIC_SCC_R2_DMAPTR IOASIC_SLOT_1_START+0x060 |
#define | IOASIC_FLOPPY_DMAPTR IOASIC_SLOT_1_START+0x070 |
#define | IOASIC_ISDN_X_DMAPTR IOASIC_SLOT_1_START+0x080 |
#define | IOASIC_ISDN_X_NEXTPTR IOASIC_SLOT_1_START+0x090 |
#define | IOASIC_ISDN_R_DMAPTR IOASIC_SLOT_1_START+0x0a0 |
#define | IOASIC_ISDN_R_NEXTPTR IOASIC_SLOT_1_START+0x0b0 |
#define | IOASIC_BUFF0 IOASIC_SLOT_1_START+0x0c0 |
#define | IOASIC_BUFF1 IOASIC_SLOT_1_START+0x0d0 |
#define | IOASIC_BUFF2 IOASIC_SLOT_1_START+0x0e0 |
#define | IOASIC_BUFF3 IOASIC_SLOT_1_START+0x0f0 |
#define | IOASIC_CSR IOASIC_SLOT_1_START+0x100 |
#define | IOASIC_INTR IOASIC_SLOT_1_START+0x110 |
#define | IOASIC_IMSK IOASIC_SLOT_1_START+0x120 |
#define | IOASIC_CURADDR IOASIC_SLOT_1_START+0x130 |
#define | IOASIC_ISDN_X_DATA IOASIC_SLOT_1_START+0x140 |
#define | IOASIC_ISDN_R_DATA IOASIC_SLOT_1_START+0x150 |
#define | IOASIC_LANCE_DECODE IOASIC_SLOT_1_START+0x160 |
#define | IOASIC_SCSI_DECODE IOASIC_SLOT_1_START+0x170 |
#define | IOASIC_SCC0_DECODE IOASIC_SLOT_1_START+0x180 |
#define | IOASIC_SCC1_DECODE IOASIC_SLOT_1_START+0x190 |
#define | IOASIC_FLOPPY_DECODE IOASIC_SLOT_1_START+0x1a0 |
#define | IOASIC_SCSI_SCR IOASIC_SLOT_1_START+0x1b0 |
#define | IOASIC_SCSI_SDR0 IOASIC_SLOT_1_START+0x1c0 |
#define | IOASIC_SCSI_SDR1 IOASIC_SLOT_1_START+0x1d0 |
#define | IOASIC_CTR IOASIC_SLOT_1_START+0x1e0 /*3max+/3000*/ |
#define | IOASIC_CSR_DMAEN_T1 0x80000000 /* rw */ |
#define | IOASIC_CSR_DMAEN_R1 0x40000000 /* rw */ |
#define | IOASIC_CSR_DMAEN_T2 0x20000000 /* rw */ |
#define | IOASIC_CSR_DMAEN_R2 0x10000000 /* rw */ |
#define | IOASIC_CSR_FASTMODE 0x08000000 /* rw - 3000 */ |
#define | IOASIC_CSR_xxx 0x07800000 /* reserved - 3000 */ |
#define | IOASIC_CSR_DS_xxx 0x0f800000 /* reserved - DS */ |
#define | IOASIC_CSR_FLOPPY_DIR 0x00400000 /* rw - maxine */ |
#define | IOASIC_CSR_DMAEN_FLOPPY 0x00200000 /* rw - maxine */ |
#define | IOASIC_CSR_DMAEN_ISDN_T 0x00100000 /* rw */ |
#define | IOASIC_CSR_DMAEN_ISDN_R 0x00080000 /* rw */ |
#define | IOASIC_CSR_SCSI_DIR 0x00040000 /* rw - DS */ |
#define | IOASIC_CSR_DMAEN_SCSI 0x00020000 /* rw - DS */ |
#define | IOASIC_CSR_DMAEN_LANCE 0x00010000 /* rw - DS */ |
#define | IOASIC_CSR_DIAGDN 0x00008000 /* rw */ |
#define | IOASIC_CSR_TXDIS_2 0x00004000 /* rw - 3min,3max+ */ |
#define | IOASIC_CSR_TXDIS_1 0x00002000 /* rw - 3min,3max+ */ |
#define | IOASIC_CSR_ISDN_ENABLE 0x00001000 /* rw - 3000/maxine */ |
#define | IOASIC_CSR_SCC_ENABLE 0x00000800 /* rw */ |
#define | IOASIC_CSR_RTC_ENABLE 0x00000400 /* rw */ |
#define | IOASIC_CSR_SCSI_ENABLE 0x00000200 /* rw - DS */ |
#define | IOASIC_CSR_LANCE_ENABLE 0x00000100 /* rw */ |
#define | IOASIC_INTR_T1_PAGE_END 0x80000000 /* rz */ |
#define | IOASIC_INTR_T1_READ_E 0x40000000 /* rz */ |
#define | IOASIC_INTR_R1_HALF_PAGE 0x20000000 /* rz */ |
#define | IOASIC_INTR_R1_DMA_OVRUN 0x10000000 /* rz */ |
#define | IOASIC_INTR_T2_PAGE_END 0x08000000 /* rz */ |
#define | IOASIC_INTR_T2_READ_E 0x04000000 /* rz */ |
#define | IOASIC_INTR_R2_HALF_PAGE 0x02000000 /* rz */ |
#define | IOASIC_INTR_R2_DMA_OVRUN 0x01000000 /* rz */ |
#define | IOASIC_INTR_FLOPPY_DMA_E 0x00800000 /* rz - maxine */ |
#define | IOASIC_INTR_ISDN_TXLOAD 0x00400000 /* rz - 3000/maxine */ |
#define | IOASIC_INTR_ISDN_RXLOAD 0x00200000 /* rz - 3000/maxine */ |
#define | IOASIC_INTR_ISDN_OVRUN 0x00100000 /* rz - 3000/maxine */ |
#define | IOASIC_INTR_SCSI_PTR_LOAD 0x00080000 /* rz - DS */ |
#define | IOASIC_INTR_SCSI_OVRUN 0x00040000 /* rz - DS */ |
#define | IOASIC_INTR_SCSI_READ_E 0x00020000 /* rz - DS */ |
#define | IOASIC_INTR_LANCE_READ_E 0x00010000 /* rz - DS */ |
#define | IOASIC_INTR_NVR_JUMPER 0x00004000 /* ro */ |
#define | IOASIC_INTR_ISDN 0x00002000 /* ro - 3000 */ |
#define | IOASIC_INTR_NRMOD_JUMPER 0x00000400 /* ro */ |
#define | IOASIC_INTR_SEC_CON 0x00000200 /* ro */ |
#define | IOASIC_INTR_SCSI 0x00000200 /* ro - DS */ |
#define | IOASIC_INTR_LANCE 0x00000100 /* ro */ |
#define | IOASIC_INTR_SCC_1 0x00000080 /* ro */ |
#define | IOASIC_INTR_SCC_0 0x00000040 /* ro */ |
#define | IOASIC_INTR_ALT_CON 0x00000008 /* ro - 3000/500 */ |
#define | IOASIC_INTR_300_OPT1 0x00000008 /* ro - 3000/300 */ |
#define | IOASIC_INTR_300_OPT0 0x00000004 /* ro - 3000/300 */ |
#define | IOASIC_DMA_ADDR(p) ((((p) << 3) & ~0x1f) | (((p) >> 29) & 0x1f)) |
#define | IOASIC_DMA_BLOCKSIZE 0x1000 |
#define | IOASIC_SCR_STATUS 0x00000004 |
#define | IOASIC_SCR_WORD 0x00000003 |
#define | IOASIC_DECODE_HW_ADDRESS 0x000003f0 |
#define | IOASIC_DECODE_CHIP_SELECT 0x0000000f |
#define | IOASIC_SYS_ETHER_ADDRESS(base) ((base) + IOASIC_SLOT_2_START) |
#define | IOASIC_SYS_LANCE(base) ((base) + IOASIC_SLOT_3_START) |
#define IOASIC_BUFF0 IOASIC_SLOT_1_START+0x0c0 |
Definition at line 109 of file tc_ioasicreg.h.
#define IOASIC_BUFF1 IOASIC_SLOT_1_START+0x0d0 |
Definition at line 110 of file tc_ioasicreg.h.
#define IOASIC_BUFF2 IOASIC_SLOT_1_START+0x0e0 |
Definition at line 111 of file tc_ioasicreg.h.
#define IOASIC_BUFF3 IOASIC_SLOT_1_START+0x0f0 |
Definition at line 112 of file tc_ioasicreg.h.
#define IOASIC_CSR IOASIC_SLOT_1_START+0x100 |
Definition at line 113 of file tc_ioasicreg.h.
#define IOASIC_CSR_DIAGDN 0x00008000 /* rw */ |
Definition at line 145 of file tc_ioasicreg.h.
#define IOASIC_CSR_DMAEN_FLOPPY 0x00200000 /* rw - maxine */ |
Definition at line 138 of file tc_ioasicreg.h.
#define IOASIC_CSR_DMAEN_ISDN_R 0x00080000 /* rw */ |
Definition at line 140 of file tc_ioasicreg.h.
#define IOASIC_CSR_DMAEN_ISDN_T 0x00100000 /* rw */ |
Definition at line 139 of file tc_ioasicreg.h.
#define IOASIC_CSR_DMAEN_LANCE 0x00010000 /* rw - DS */ |
Definition at line 143 of file tc_ioasicreg.h.
#define IOASIC_CSR_DMAEN_R1 0x40000000 /* rw */ |
Definition at line 131 of file tc_ioasicreg.h.
#define IOASIC_CSR_DMAEN_R2 0x10000000 /* rw */ |
Definition at line 133 of file tc_ioasicreg.h.
#define IOASIC_CSR_DMAEN_SCSI 0x00020000 /* rw - DS */ |
Definition at line 142 of file tc_ioasicreg.h.
#define IOASIC_CSR_DMAEN_T1 0x80000000 /* rw */ |
Definition at line 130 of file tc_ioasicreg.h.
#define IOASIC_CSR_DMAEN_T2 0x20000000 /* rw */ |
Definition at line 132 of file tc_ioasicreg.h.
#define IOASIC_CSR_DS_xxx 0x0f800000 /* reserved - DS */ |
Definition at line 136 of file tc_ioasicreg.h.
#define IOASIC_CSR_FASTMODE 0x08000000 /* rw - 3000 */ |
Definition at line 134 of file tc_ioasicreg.h.
#define IOASIC_CSR_FLOPPY_DIR 0x00400000 /* rw - maxine */ |
Definition at line 137 of file tc_ioasicreg.h.
#define IOASIC_CSR_ISDN_ENABLE 0x00001000 /* rw - 3000/maxine */ |
Definition at line 148 of file tc_ioasicreg.h.
#define IOASIC_CSR_LANCE_ENABLE 0x00000100 /* rw */ |
Definition at line 152 of file tc_ioasicreg.h.
#define IOASIC_CSR_RTC_ENABLE 0x00000400 /* rw */ |
Definition at line 150 of file tc_ioasicreg.h.
#define IOASIC_CSR_SCC_ENABLE 0x00000800 /* rw */ |
Definition at line 149 of file tc_ioasicreg.h.
#define IOASIC_CSR_SCSI_DIR 0x00040000 /* rw - DS */ |
Definition at line 141 of file tc_ioasicreg.h.
#define IOASIC_CSR_SCSI_ENABLE 0x00000200 /* rw - DS */ |
Definition at line 151 of file tc_ioasicreg.h.
#define IOASIC_CSR_TXDIS_1 0x00002000 /* rw - 3min,3max+ */ |
Definition at line 147 of file tc_ioasicreg.h.
#define IOASIC_CSR_TXDIS_2 0x00004000 /* rw - 3min,3max+ */ |
Definition at line 146 of file tc_ioasicreg.h.
#define IOASIC_CSR_xxx 0x07800000 /* reserved - 3000 */ |
Definition at line 135 of file tc_ioasicreg.h.
#define IOASIC_CTR IOASIC_SLOT_1_START+0x1e0 /*3max+/3000*/ |
Definition at line 127 of file tc_ioasicreg.h.
#define IOASIC_CURADDR IOASIC_SLOT_1_START+0x130 |
Definition at line 116 of file tc_ioasicreg.h.
#define IOASIC_DECODE_CHIP_SELECT 0x0000000f |
Definition at line 201 of file tc_ioasicreg.h.
#define IOASIC_DECODE_HW_ADDRESS 0x000003f0 |
Definition at line 200 of file tc_ioasicreg.h.
#define IOASIC_DMA_ADDR | ( | p | ) | ((((p) << 3) & ~0x1f) | (((p) >> 29) & 0x1f)) |
Definition at line 187 of file tc_ioasicreg.h.
#define IOASIC_DMA_BLOCKSIZE 0x1000 |
Definition at line 189 of file tc_ioasicreg.h.
#define IOASIC_FLOPPY_DECODE IOASIC_SLOT_1_START+0x1a0 |
Definition at line 123 of file tc_ioasicreg.h.
#define IOASIC_FLOPPY_DMAPTR IOASIC_SLOT_1_START+0x070 |
Definition at line 104 of file tc_ioasicreg.h.
#define IOASIC_IMSK IOASIC_SLOT_1_START+0x120 |
Definition at line 115 of file tc_ioasicreg.h.
#define IOASIC_INTR IOASIC_SLOT_1_START+0x110 |
Definition at line 114 of file tc_ioasicreg.h.
#define IOASIC_INTR_300_OPT0 0x00000004 /* ro - 3000/300 */ |
Definition at line 183 of file tc_ioasicreg.h.
#define IOASIC_INTR_300_OPT1 0x00000008 /* ro - 3000/300 */ |
Definition at line 182 of file tc_ioasicreg.h.
#define IOASIC_INTR_ALT_CON 0x00000008 /* ro - 3000/500 */ |
Definition at line 181 of file tc_ioasicreg.h.
#define IOASIC_INTR_FLOPPY_DMA_E 0x00800000 /* rz - maxine */ |
Definition at line 163 of file tc_ioasicreg.h.
#define IOASIC_INTR_ISDN 0x00002000 /* ro - 3000 */ |
Definition at line 174 of file tc_ioasicreg.h.
#define IOASIC_INTR_ISDN_OVRUN 0x00100000 /* rz - 3000/maxine */ |
Definition at line 166 of file tc_ioasicreg.h.
#define IOASIC_INTR_ISDN_RXLOAD 0x00200000 /* rz - 3000/maxine */ |
Definition at line 165 of file tc_ioasicreg.h.
#define IOASIC_INTR_ISDN_TXLOAD 0x00400000 /* rz - 3000/maxine */ |
Definition at line 164 of file tc_ioasicreg.h.
#define IOASIC_INTR_LANCE 0x00000100 /* ro */ |
Definition at line 178 of file tc_ioasicreg.h.
#define IOASIC_INTR_LANCE_READ_E 0x00010000 /* rz - DS */ |
Definition at line 170 of file tc_ioasicreg.h.
#define IOASIC_INTR_NRMOD_JUMPER 0x00000400 /* ro */ |
Definition at line 175 of file tc_ioasicreg.h.
#define IOASIC_INTR_NVR_JUMPER 0x00004000 /* ro */ |
Definition at line 173 of file tc_ioasicreg.h.
#define IOASIC_INTR_R1_DMA_OVRUN 0x10000000 /* rz */ |
Definition at line 158 of file tc_ioasicreg.h.
#define IOASIC_INTR_R1_HALF_PAGE 0x20000000 /* rz */ |
Definition at line 157 of file tc_ioasicreg.h.
#define IOASIC_INTR_R2_DMA_OVRUN 0x01000000 /* rz */ |
Definition at line 162 of file tc_ioasicreg.h.
#define IOASIC_INTR_R2_HALF_PAGE 0x02000000 /* rz */ |
Definition at line 161 of file tc_ioasicreg.h.
#define IOASIC_INTR_SCC_0 0x00000040 /* ro */ |
Definition at line 180 of file tc_ioasicreg.h.
#define IOASIC_INTR_SCC_1 0x00000080 /* ro */ |
Definition at line 179 of file tc_ioasicreg.h.
#define IOASIC_INTR_SCSI 0x00000200 /* ro - DS */ |
Definition at line 177 of file tc_ioasicreg.h.
#define IOASIC_INTR_SCSI_OVRUN 0x00040000 /* rz - DS */ |
Definition at line 168 of file tc_ioasicreg.h.
#define IOASIC_INTR_SCSI_PTR_LOAD 0x00080000 /* rz - DS */ |
Definition at line 167 of file tc_ioasicreg.h.
#define IOASIC_INTR_SCSI_READ_E 0x00020000 /* rz - DS */ |
Definition at line 169 of file tc_ioasicreg.h.
#define IOASIC_INTR_SEC_CON 0x00000200 /* ro */ |
Definition at line 176 of file tc_ioasicreg.h.
#define IOASIC_INTR_T1_PAGE_END 0x80000000 /* rz */ |
Definition at line 155 of file tc_ioasicreg.h.
#define IOASIC_INTR_T1_READ_E 0x40000000 /* rz */ |
Definition at line 156 of file tc_ioasicreg.h.
#define IOASIC_INTR_T2_PAGE_END 0x08000000 /* rz */ |
Definition at line 159 of file tc_ioasicreg.h.
#define IOASIC_INTR_T2_READ_E 0x04000000 /* rz */ |
Definition at line 160 of file tc_ioasicreg.h.
#define IOASIC_ISDN_R_DATA IOASIC_SLOT_1_START+0x150 |
Definition at line 118 of file tc_ioasicreg.h.
#define IOASIC_ISDN_R_DMAPTR IOASIC_SLOT_1_START+0x0a0 |
Definition at line 107 of file tc_ioasicreg.h.
#define IOASIC_ISDN_R_NEXTPTR IOASIC_SLOT_1_START+0x0b0 |
Definition at line 108 of file tc_ioasicreg.h.
#define IOASIC_ISDN_X_DATA IOASIC_SLOT_1_START+0x140 |
Definition at line 117 of file tc_ioasicreg.h.
#define IOASIC_ISDN_X_DMAPTR IOASIC_SLOT_1_START+0x080 |
Definition at line 105 of file tc_ioasicreg.h.
#define IOASIC_ISDN_X_NEXTPTR IOASIC_SLOT_1_START+0x090 |
Definition at line 106 of file tc_ioasicreg.h.
#define IOASIC_LANCE_DECODE IOASIC_SLOT_1_START+0x160 |
Definition at line 119 of file tc_ioasicreg.h.
#define IOASIC_LANCE_DMAPTR IOASIC_SLOT_1_START+0x020 |
Definition at line 99 of file tc_ioasicreg.h.
#define IOASIC_SCC0_DECODE IOASIC_SLOT_1_START+0x180 |
Definition at line 121 of file tc_ioasicreg.h.
#define IOASIC_SCC1_DECODE IOASIC_SLOT_1_START+0x190 |
Definition at line 122 of file tc_ioasicreg.h.
#define IOASIC_SCC_R1_DMAPTR IOASIC_SLOT_1_START+0x040 |
Definition at line 101 of file tc_ioasicreg.h.
#define IOASIC_SCC_R2_DMAPTR IOASIC_SLOT_1_START+0x060 |
Definition at line 103 of file tc_ioasicreg.h.
#define IOASIC_SCC_T1_DMAPTR IOASIC_SLOT_1_START+0x030 |
Definition at line 100 of file tc_ioasicreg.h.
#define IOASIC_SCC_T2_DMAPTR IOASIC_SLOT_1_START+0x050 |
Definition at line 102 of file tc_ioasicreg.h.
#define IOASIC_SCR_STATUS 0x00000004 |
Definition at line 195 of file tc_ioasicreg.h.
#define IOASIC_SCR_WORD 0x00000003 |
Definition at line 196 of file tc_ioasicreg.h.
#define IOASIC_SCSI_DECODE IOASIC_SLOT_1_START+0x170 |
Definition at line 120 of file tc_ioasicreg.h.
#define IOASIC_SCSI_DMAPTR IOASIC_SLOT_1_START+0x000 |
Definition at line 97 of file tc_ioasicreg.h.
#define IOASIC_SCSI_NEXTPTR IOASIC_SLOT_1_START+0x010 |
Definition at line 98 of file tc_ioasicreg.h.
#define IOASIC_SCSI_SCR IOASIC_SLOT_1_START+0x1b0 |
Definition at line 124 of file tc_ioasicreg.h.
#define IOASIC_SCSI_SDR0 IOASIC_SLOT_1_START+0x1c0 |
Definition at line 125 of file tc_ioasicreg.h.
#define IOASIC_SCSI_SDR1 IOASIC_SLOT_1_START+0x1d0 |
Definition at line 126 of file tc_ioasicreg.h.
#define IOASIC_SLOT_0_START 0x000000 |
Definition at line 75 of file tc_ioasicreg.h.
#define IOASIC_SLOT_10_START 0x280000 |
Definition at line 85 of file tc_ioasicreg.h.
#define IOASIC_SLOT_11_START 0x2c0000 |
Definition at line 86 of file tc_ioasicreg.h.
#define IOASIC_SLOT_12_START 0x300000 |
Definition at line 87 of file tc_ioasicreg.h.
#define IOASIC_SLOT_13_START 0x340000 |
Definition at line 88 of file tc_ioasicreg.h.
#define IOASIC_SLOT_14_START 0x380000 |
Definition at line 89 of file tc_ioasicreg.h.
#define IOASIC_SLOT_15_START 0x3c0000 |
Definition at line 90 of file tc_ioasicreg.h.
#define IOASIC_SLOT_1_START 0x040000 |
Definition at line 76 of file tc_ioasicreg.h.
#define IOASIC_SLOT_2_START 0x080000 |
Definition at line 77 of file tc_ioasicreg.h.
#define IOASIC_SLOT_3_START 0x0c0000 |
Definition at line 78 of file tc_ioasicreg.h.
#define IOASIC_SLOT_4_START 0x100000 |
Definition at line 79 of file tc_ioasicreg.h.
#define IOASIC_SLOT_5_START 0x140000 |
Definition at line 80 of file tc_ioasicreg.h.
#define IOASIC_SLOT_6_START 0x180000 |
Definition at line 81 of file tc_ioasicreg.h.
#define IOASIC_SLOT_7_START 0x1c0000 |
Definition at line 82 of file tc_ioasicreg.h.
#define IOASIC_SLOT_8_START 0x200000 |
Definition at line 83 of file tc_ioasicreg.h.
#define IOASIC_SLOT_9_START 0x240000 |
Definition at line 84 of file tc_ioasicreg.h.
#define IOASIC_SLOTS_END 0x3fffff |
Definition at line 91 of file tc_ioasicreg.h.
#define IOASIC_SYS_ETHER_ADDRESS | ( | base | ) | ((base) + IOASIC_SLOT_2_START) |
Definition at line 206 of file tc_ioasicreg.h.
#define IOASIC_SYS_LANCE | ( | base | ) | ((base) + IOASIC_SLOT_3_START) |
Definition at line 207 of file tc_ioasicreg.h.