Go to the source code of this file.
Classes | |
struct | sh_cpu_type_def |
struct | sh_cpu |
Macros | |
#define | SH_CPU_TYPE_DEFS |
#define | SH_N_IC_ARGS 2 |
#define | SH_INSTR_ALIGNMENT_SHIFT 1 |
#define | SH_IC_ENTRIES_SHIFT 11 |
#define | SH_IC_ENTRIES_PER_PAGE (1 << SH_IC_ENTRIES_SHIFT) |
#define | SH_PC_TO_IC_ENTRY(a) |
#define | SH_ADDR_TO_PAGENR(a) |
#define | SH_MAX_VPH_TLB_ENTRIES 128 |
#define | SH_N_GPRS 16 |
#define | SH_N_GPRS_BANKED 8 |
#define | SH_N_FPRS 16 |
#define | SH_N_ITLB_ENTRIES 4 |
#define | SH_N_UTLB_ENTRIES 64 |
#define | SH_INVALID_INSTR 0x00fb |
#define | SH_SR_T 0x00000001 /* True/false */ |
#define | SH_SR_S 0x00000002 /* Saturation */ |
#define | SH_SR_IMASK 0x000000f0 /* Interrupt mask */ |
#define | SH_SR_IMASK_SHIFT 4 |
#define | SH_SR_Q 0x00000100 /* State for Divide Step */ |
#define | SH_SR_M 0x00000200 /* State for Divide Step */ |
#define | SH_SR_FD 0x00008000 /* FPU Disable */ |
#define | SH_SR_BL 0x10000000 /* Exception/Interrupt Block */ |
#define | SH_SR_RB 0x20000000 /* Register Bank 0/1 */ |
#define | SH_SR_MD 0x40000000 /* Privileged Mode */ |
#define | SH_FPSCR_RM_MASK 0x00000003 /* Rounding Mode */ |
#define | SH_FPSCR_RM_NEAREST 0x0 /* Round to nearest */ |
#define | SH_FPSCR_RM_ZERO 0x1 /* Round to zero */ |
#define | SH_FPSCR_INEXACT 0x00000004 /* Inexact exception */ |
#define | SH_FPSCR_UNDERFLOW 0x00000008 /* Underflow exception */ |
#define | SH_FPSCR_OVERFLOW 0x00000010 /* Overflow exception */ |
#define | SH_FPSCR_DIV_BY_ZERO 0x00000020 /* Div by zero exception */ |
#define | SH_FPSCR_INVALID 0x00000040 /* Invalid exception */ |
#define | SH_FPSCR_EN_INEXACT 0x00000080 /* Inexact enable */ |
#define | SH_FPSCR_EN_UNDERFLOW 0x00000100 /* Underflow enable */ |
#define | SH_FPSCR_EN_OVERFLOW 0x00000200 /* Overflow enable */ |
#define | SH_FPSCR_EN_DIV_BY_ZERO 0x00000400 /* Div by zero enable */ |
#define | SH_FPSCR_EN_INVALID 0x00000800 /* Invalid enable */ |
#define | SH_FPSCR_CAUSE_INEXACT 0x00001000 /* Cause Inexact */ |
#define | SH_FPSCR_CAUSE_UNDERFLOW 0x00002000 /* Cause Underflow */ |
#define | SH_FPSCR_CAUSE_OVERFLOW 0x00004000 /* Cause Overflow */ |
#define | SH_FPSCR_CAUSE_DIVBY0 0x00008000 /* Cause Div by 0 */ |
#define | SH_FPSCR_CAUSE_INVALID 0x00010000 /* Cause Invalid */ |
#define | SH_FPSCR_CAUSE_ERROR 0x00020000 /* Cause Error */ |
#define | SH_FPSCR_DN_ZERO 0x00040000 /* Denormalization Mode */ |
#define | SH_FPSCR_PR 0x00080000 /* Double-Precision Mode */ |
#define | SH_FPSCR_SZ 0x00100000 /* Double-Precision Size */ |
#define | SH_FPSCR_FR 0x00200000 /* Register Bank Select */ |
#define | SH_INT_ASSERTED 0x10 |
#define | SH_INT_PRIO_MASK 0x0f |
Functions | |
void | sh_cpu_interrupt_assert (struct interrupt *interrupt) |
void | sh_cpu_interrupt_deassert (struct interrupt *interrupt) |
int | sh_cpu_instruction_has_delayslot (struct cpu *cpu, unsigned char *ib) |
int | sh_run_instr (struct cpu *cpu) |
void | sh_update_translation_table (struct cpu *cpu, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page) |
void | sh_invalidate_translation_caches (struct cpu *cpu, uint64_t, int) |
void | sh_invalidate_code_translation (struct cpu *cpu, uint64_t, int) |
void | sh_init_64bit_dummy_tables (struct cpu *cpu) |
int | sh_memory_rw (struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags) |
int | sh_cpu_family_init (struct cpu_family *) |
void | sh_update_interrupt_priorities (struct cpu *cpu) |
void | sh_update_sr (struct cpu *cpu, uint32_t new_sr) |
void | sh_exception (struct cpu *cpu, int expevt, int intevt, uint32_t vaddr) |
int | sh_translate_v2p (struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags) |
#define SH_ADDR_TO_PAGENR | ( | a | ) |
#define SH_CPU_TYPE_DEFS |
#define SH_FPSCR_CAUSE_DIVBY0 0x00008000 /* Cause Div by 0 */ |
#define SH_FPSCR_CAUSE_INEXACT 0x00001000 /* Cause Inexact */ |
#define SH_FPSCR_CAUSE_INVALID 0x00010000 /* Cause Invalid */ |
#define SH_FPSCR_CAUSE_OVERFLOW 0x00004000 /* Cause Overflow */ |
#define SH_FPSCR_CAUSE_UNDERFLOW 0x00002000 /* Cause Underflow */ |
#define SH_FPSCR_DIV_BY_ZERO 0x00000020 /* Div by zero exception */ |
#define SH_FPSCR_DN_ZERO 0x00040000 /* Denormalization Mode */ |
#define SH_FPSCR_EN_DIV_BY_ZERO 0x00000400 /* Div by zero enable */ |
#define SH_FPSCR_EN_INEXACT 0x00000080 /* Inexact enable */ |
#define SH_FPSCR_EN_INVALID 0x00000800 /* Invalid enable */ |
#define SH_FPSCR_EN_OVERFLOW 0x00000200 /* Overflow enable */ |
#define SH_FPSCR_EN_UNDERFLOW 0x00000100 /* Underflow enable */ |
#define SH_FPSCR_INEXACT 0x00000004 /* Inexact exception */ |
#define SH_FPSCR_INVALID 0x00000040 /* Invalid exception */ |
#define SH_FPSCR_OVERFLOW 0x00000010 /* Overflow exception */ |
#define SH_FPSCR_UNDERFLOW 0x00000008 /* Underflow exception */ |
#define SH_IC_ENTRIES_PER_PAGE (1 << SH_IC_ENTRIES_SHIFT) |
#define SH_PC_TO_IC_ENTRY | ( | a | ) |
#define SH_SR_BL 0x10000000 /* Exception/Interrupt Block */ |
int sh_cpu_family_init | ( | struct cpu_family * | ) |
int sh_cpu_instruction_has_delayslot | ( | struct cpu * | cpu, |
unsigned char * | ib | ||
) |
Definition at line 395 of file cpu_sh.cc.
References BE16_TO_HOST, cpu::byte_order, EMUL_BIG_ENDIAN, cpu::is_32bit, and LE16_TO_HOST.
void sh_cpu_interrupt_assert | ( | struct interrupt * | interrupt | ) |
Definition at line 304 of file cpu_sh.cc.
References cpu::cd, interrupt::extra, fatal(), if(), sh_cpu::int_level, sh_cpu::int_prio_and_pending, sh_cpu::int_to_assert, interrupt::line, cpu::sh, SH_INT_ASSERTED, and SH_INT_PRIO_MASK.
void sh_cpu_interrupt_deassert | ( | struct interrupt * | interrupt | ) |
Definition at line 331 of file cpu_sh.cc.
References cpu::cd, interrupt::extra, if(), sh_cpu::int_level, sh_cpu::int_prio_and_pending, sh_cpu::int_to_assert, interrupt::line, cpu::sh, SH_INT_ASSERTED, and SH_INT_PRIO_MASK.
void sh_exception | ( | struct cpu * | cpu, |
int | expevt, | ||
int | intevt, | ||
uint32_t | vaddr | ||
) |
Definition at line 632 of file cpu_sh.cc.
References cpu::cd, debug, cpu::delay_slot, EXCEPTION_IN_DELAY_SLOT, sh_cpu::expevt, EXPEVT_FPU_DISABLE, EXPEVT_RES_INST, EXPEVT_RESET_MANUAL, EXPEVT_RESET_POWER, EXPEVT_TLB_MISS_LD, EXPEVT_TLB_MISS_ST, EXPEVT_TLB_MOD, EXPEVT_TLB_PROT_LD, EXPEVT_TLB_PROT_ST, EXPEVT_TRAPA, fatal(), sh_cpu::intevt, cpu::is_halted, cpu::pc, sh_cpu::pteh, quiet_mode, sh_cpu::r, sh_cpu::sgr, cpu::sh, SH4_PTEH_VPN_MASK, sh_pc_to_pointers(), SH_SR_BL, SH_SR_FD, SH_SR_IMASK, SH_SR_MD, SH_SR_RB, sh_update_sr(), sh_cpu::spc, sh_cpu::sr, sh_cpu::ssr, sh_cpu::tea, and sh_cpu::vbr.
Referenced by DEVICE_ACCESS(), and X().
void sh_init_64bit_dummy_tables | ( | struct cpu * | cpu | ) |
void sh_invalidate_code_translation | ( | struct cpu * | cpu, |
uint64_t | , | ||
int | |||
) |
void sh_invalidate_translation_caches | ( | struct cpu * | cpu, |
uint64_t | , | ||
int | |||
) |
int sh_memory_rw | ( | struct cpu * | cpu, |
struct memory * | mem, | ||
uint64_t | vaddr, | ||
unsigned char * | data, | ||
size_t | len, | ||
int | writeflag, | ||
int | cache_flags | ||
) |
int sh_run_instr | ( | struct cpu * | cpu | ) |
int sh_translate_v2p | ( | struct cpu * | cpu, |
uint64_t | vaddr, | ||
uint64_t * | return_addr, | ||
int | flags | ||
) |
Definition at line 248 of file memory_sh.cc.
References cpu::cd, sh_cpu::mmucr, cpu::sh, SH4_MMUCR_AT, SH_SR_MD, and sh_cpu::sr.
void sh_update_interrupt_priorities | ( | struct cpu * | cpu | ) |
Definition at line 249 of file cpu_sh.cc.
References cpu::cd, sh_cpu::int_prio_and_pending, sh_cpu::intc_intpri08, sh_cpu::intc_ipra, cpu::sh, SH4_INTEVT_IRQ0, SH4_INTEVT_IRQ14, SH4_INTEVT_SCIF_ERI, SH4_INTEVT_SCIF_TXI, SH_INT_PRIO_MASK, SH_INTEVT_TMU0_TUNI0, SH_INTEVT_TMU1_TUNI1, and SH_INTEVT_TMU2_TUNI2.
void sh_update_sr | ( | struct cpu * | cpu, |
uint32_t | new_sr | ||
) |
Definition at line 585 of file cpu_sh.cc.
References cpu::cd, sh_cpu::r, sh_cpu::r_bank, cpu::sh, SH_N_GPRS_BANKED, SH_SR_RB, and sh_cpu::sr.
Referenced by sh_exception(), and X().
void sh_update_translation_table | ( | struct cpu * | cpu, |
uint64_t | vaddr_page, | ||
unsigned char * | host_page, | ||
int | writeflag, | ||
uint64_t | paddr_page | ||
) |