mips_cpuregs.h File Reference

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Macros
mips_cpuregs.h File Reference

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Macros

#define MIPS_KUSEG_START   0x0
 
#define MIPS_KSEG0_START   0x80000000
 
#define MIPS_KSEG1_START   0xa0000000
 
#define MIPS_KSEG2_START   0xc0000000
 
#define MIPS_MAX_MEM_ADDR   0xbe000000
 
#define MIPS_RESERVED_ADDR   0xbfc80000
 
#define MIPS_PHYS_MASK   0x1fffffff
 
#define MIPS_KSEG0_TO_PHYS(x)   ((unsigned)(x) & MIPS_PHYS_MASK)
 
#define MIPS_PHYS_TO_KSEG0(x)   ((unsigned)(x) | MIPS_KSEG0_START)
 
#define MIPS_KSEG1_TO_PHYS(x)   ((unsigned)(x) & MIPS_PHYS_MASK)
 
#define MIPS_PHYS_TO_KSEG1(x)   ((unsigned)(x) | MIPS_KSEG1_START)
 
#define MIPS3_VA_TO_CINDEX(x)   ((unsigned)(x) & 0xffffff | MIPS_KSEG0_START)
 
#define MIPS_PHYS_TO_XKPHYS(cca, x)   ((0x2ULL << 62) | ((unsigned long long)(cca) << 59) | (x))
 
#define MIPS_XKPHYS_TO_PHYS(x)   ((x) & 0x0effffffffffffffULL)
 
#define COP0_SYNC   /* nothing */
 
#define COP0_HAZARD_FPUENABLE   nop; nop; nop; nop;
 
#define MIPS_CR_BR_DELAY   0x80000000
 
#define MIPS_CR_COP_ERR   0x30000000
 
#define MIPS1_CR_EXC_CODE   0x0000003C /* four bits */
 
#define MIPS3_CR_EXC_CODE   0x0000007C /* five bits */
 
#define MIPS_CR_IP   0x0000FF00
 
#define MIPS_CR_EXC_CODE_SHIFT   2
 
#define MIPS_SR_COP_USABILITY   0xf0000000
 
#define MIPS_SR_COP_0_BIT   0x10000000
 
#define MIPS_SR_COP_1_BIT   0x20000000
 
#define MIPS_SR_MX   0x01000000 /* MIPS64 */
 
#define MIPS_SR_PX   0x00800000 /* MIPS64 */
 
#define MIPS_SR_BEV   0x00400000 /* Use boot exception vector */
 
#define MIPS_SR_TS   0x00200000
 
#define MIPS_SR_INT_IE   0x00000001
 
#define MIPS1_PARITY_ERR   0x00100000
 
#define MIPS1_CACHE_MISS   0x00080000
 
#define MIPS1_PARITY_ZERO   0x00040000
 
#define MIPS1_SWAP_CACHES   0x00020000
 
#define MIPS1_ISOL_CACHES   0x00010000
 
#define MIPS1_SR_KU_OLD   0x00000020 /* 2nd stacked KU/IE*/
 
#define MIPS1_SR_INT_ENA_OLD   0x00000010 /* 2nd stacked KU/IE*/
 
#define MIPS1_SR_KU_PREV   0x00000008 /* 1st stacked KU/IE*/
 
#define MIPS1_SR_INT_ENA_PREV   0x00000004 /* 1st stacked KU/IE*/
 
#define MIPS1_SR_KU_CUR   0x00000002 /* current KU */
 
#define MIPS_SR_PARITY_ERR   MIPS1_PARITY_ERR
 
#define MIPS_SR_CACHE_MISS   MIPS1_CACHE_MISS
 
#define MIPS_SR_PARITY_ZERO   MIPS1_PARITY_ZERO
 
#define MIPS_SR_SWAP_CACHES   MIPS1_SWAP_CACHES
 
#define MIPS_SR_ISOL_CACHES   MIPS1_ISOL_CACHES
 
#define MIPS_SR_KU_OLD   MIPS1_SR_KU_OLD
 
#define MIPS_SR_INT_ENA_OLD   MIPS1_SR_INT_ENA_OLD
 
#define MIPS_SR_KU_PREV   MIPS1_SR_KU_PREV
 
#define MIPS_SR_KU_CUR   MIPS1_SR_KU_CUR
 
#define MIPS_SR_INT_ENA_PREV   MIPS1_SR_INT_ENA_PREV
 
#define MIPS3_SR_XX   0x80000000
 
#define MIPS3_SR_RP   0x08000000
 
#define MIPS3_SR_FR   0x04000000
 
#define MIPS3_SR_RE   0x02000000
 
#define MIPS3_SR_DIAG_DL   0x01000000 /* QED 52xx */
 
#define MIPS3_SR_DIAG_IL   0x00800000 /* QED 52xx */
 
#define MIPS3_SR_SR   0x00100000
 
#define MIPS3_SR_EIE   0x00100000 /* TX79/R5900 */
 
#define MIPS3_SR_NMI   0x00080000 /* MIPS32/64 */
 
#define MIPS3_SR_DIAG_CH   0x00040000
 
#define MIPS3_SR_DIAG_CE   0x00020000
 
#define MIPS3_SR_DIAG_PE   0x00010000
 
#define MIPS3_SR_KX   0x00000080
 
#define MIPS3_SR_SX   0x00000040
 
#define MIPS3_SR_UX   0x00000020
 
#define MIPS3_SR_KSU_MASK   0x00000018
 
#define MIPS3_SR_KSU_USER   0x00000010
 
#define MIPS3_SR_KSU_SUPER   0x00000008
 
#define MIPS3_SR_KSU_KERNEL   0x00000000
 
#define MIPS3_SR_ERL   0x00000004
 
#define MIPS3_SR_EXL   0x00000002
 
#define MIPS_SR_SOFT_RESET   MIPS3_SR_SOFT_RESET
 
#define MIPS_SR_DIAG_CH   MIPS3_SR_DIAG_CH
 
#define MIPS_SR_DIAG_CE   MIPS3_SR_DIAG_CE
 
#define MIPS_SR_DIAG_PE   MIPS3_SR_DIAG_PE
 
#define MIPS_SR_KX   MIPS3_SR_KX
 
#define MIPS_SR_SX   MIPS3_SR_SX
 
#define MIPS_SR_UX   MIPS3_SR_UX
 
#define MIPS_SR_KSU_MASK   MIPS3_SR_KSU_MASK
 
#define MIPS_SR_KSU_USER   MIPS3_SR_KSU_USER
 
#define MIPS_SR_KSU_SUPER   MIPS3_SR_KSU_SUPER
 
#define MIPS_SR_KSU_KERNEL   MIPS3_SR_KSU_KERNEL
 
#define MIPS_SR_ERL   MIPS3_SR_ERL
 
#define MIPS_SR_EXL   MIPS3_SR_EXL
 
#define MIPS_INT_MASK   0xff00
 
#define MIPS_INT_MASK_5   0x8000
 
#define MIPS_INT_MASK_4   0x4000
 
#define MIPS_INT_MASK_3   0x2000
 
#define MIPS_INT_MASK_2   0x1000
 
#define MIPS_INT_MASK_1   0x0800
 
#define MIPS_INT_MASK_0   0x0400
 
#define MIPS_HARD_INT_MASK   0xfc00
 
#define MIPS_SOFT_INT_MASK_1   0x0200
 
#define MIPS_SOFT_INT_MASK_0   0x0100
 
#define MIPS3_INT_MASK   (MIPS_INT_MASK & ~MIPS_INT_MASK_5)
 
#define MIPS3_HARD_INT_MASK   (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5)
 
#define MIPS1_CNTXT_PTE_BASE   0xFFE00000
 
#define MIPS1_CNTXT_BAD_VPN   0x001FFFFC
 
#define MIPS3_CNTXT_PTE_BASE   0xFF800000
 
#define MIPS3_CNTXT_BAD_VPN2   0x007FFFF0
 
#define MIPS3_CONFIG_K0_MASK   0x00000007
 
#define MIPS3_CONFIG_CU   0x00000008
 
#define MIPS3_CONFIG_DB   0x00000010 /* Primary D-cache line size */
 
#define MIPS3_CONFIG_IB   0x00000020 /* Primary I-cache line size */
 
#define MIPS3_CONFIG_CACHE_L1_LSIZE(config, bit)   (((config) & (bit)) ? 32 : 16)
 
#define MIPS3_CONFIG_DC_MASK   0x000001c0 /* Primary D-cache size */
 
#define MIPS3_CONFIG_DC_SHIFT   6
 
#define MIPS3_CONFIG_IC_MASK   0x00000e00 /* Primary I-cache size */
 
#define MIPS3_CONFIG_IC_SHIFT   9
 
#define MIPS3_CONFIG_C_DEFBASE   0x1000 /* default base 2^12 */
 
#define MIPS3_CONFIG_CS   0x00001000
 
#define MIPS3_CONFIG_C_4100BASE   0x0400 /* base is 2^10 if CS=1 */
 
#define MIPS3_CONFIG_CACHE_SIZE(config, mask, base, shift)   ((base) << (((config) & (mask)) >> (shift)))
 
#define MIPS3_CONFIG_SE   0x00001000
 
#define MIPS3_CONFIG_EB   0x00002000
 
#define MIPS3_CONFIG_EM   0x00004000
 
#define MIPS3_CONFIG_BE   0x00008000
 
#define MIPS3_CONFIG_SM   0x00010000
 
#define MIPS3_CONFIG_SC   0x00020000
 
#define MIPS3_CONFIG_EW_MASK   0x000c0000
 
#define MIPS3_CONFIG_EW_SHIFT   18
 
#define MIPS3_CONFIG_SW   0x00100000
 
#define MIPS3_CONFIG_SS   0x00200000
 
#define MIPS3_CONFIG_SB_MASK   0x00c00000
 
#define MIPS3_CONFIG_SB_SHIFT   22
 
#define MIPS3_CONFIG_CACHE_L2_LSIZE(config)   (0x10 << (((config) & MIPS3_CONFIG_SB_MASK) >> MIPS3_CONFIG_SB_SHIFT))
 
#define MIPS3_CONFIG_EP_MASK   0x0f000000
 
#define MIPS3_CONFIG_EP_SHIFT   24
 
#define MIPS3_CONFIG_EC_MASK   0x70000000
 
#define MIPS3_CONFIG_EC_SHIFT   28
 
#define MIPS3_CONFIG_CM   0x80000000
 
#define MIPS4_CONFIG_K0_MASK   MIPS3_CONFIG_K0_MASK
 
#define MIPS4_CONFIG_DN_MASK   0x00000018 /* Device number */
 
#define MIPS4_CONFIG_CT   0x00000020 /* CohPrcReqTar */
 
#define MIPS4_CONFIG_PE   0x00000040 /* PreElmReq */
 
#define MIPS4_CONFIG_PM_MASK   0x00000180 /* PreReqMax */
 
#define MIPS4_CONFIG_EC_MASK   0x00001e00 /* SysClkDiv */
 
#define MIPS4_CONFIG_SB   0x00002000 /* SCBlkSize */
 
#define MIPS4_CONFIG_SK   0x00004000 /* SCColEn */
 
#define MIPS4_CONFIG_BE   0x00008000 /* MemEnd */
 
#define MIPS4_CONFIG_SS_MASK   0x00070000 /* SCSize */
 
#define MIPS4_CONFIG_SC_MASK   0x00380000 /* SCClkDiv */
 
#define MIPS4_CONFIG_RESERVED   0x03c00000 /* Reserved wired 0 */
 
#define MIPS4_CONFIG_DC_MASK   0x1c000000 /* Primary D-Cache size */
 
#define MIPS4_CONFIG_IC_MASK   0xe0000000 /* Primary I-Cache size */
 
#define MIPS4_CONFIG_DC_SHIFT   26
 
#define MIPS4_CONFIG_IC_SHIFT   29
 
#define MIPS4_CONFIG_CACHE_SIZE(config, mask, base, shift)   ((base) << (((config) & (mask)) >> (shift)))
 
#define MIPS4_CONFIG_CACHE_L2_LSIZE(config)   (((config) & MIPS4_CONFIG_SB) ? 128 : 64)
 
#define MIPS_RESET_EXC_VEC   0xBFC00000
 
#define MIPS_UTLB_MISS_EXC_VEC   0x80000000
 
#define MIPS1_GEN_EXC_VEC   0x80000080
 
#define MIPS3_XTLB_MISS_EXC_VEC   0x80000080
 
#define MIPS3_CACHE_ERR_EXC_VEC   0x80000100
 
#define MIPS3_GEN_EXC_VEC   0x80000180
 
#define MIPS_R5900_COUNTER_EXC_VEC   0x80000080
 
#define MIPS_R5900_DEBUG_EXC_VEC   0x80000100
 
#define MIPS3_INTR_EXC_VEC   0x80000200
 
#define MIPS_BIT(n)   n
 
#define MIPS_COP_0_TLB_INDEX   MIPS_BIT(0)
 
#define MIPS_COP_0_TLB_RANDOM   MIPS_BIT(1)
 
#define MIPS_COP_0_TLB_CONTEXT   MIPS_BIT(4)
 
#define MIPS_COP_0_BAD_VADDR   MIPS_BIT(8)
 
#define MIPS_COP_0_TLB_HI   MIPS_BIT(10)
 
#define MIPS_COP_0_STATUS   MIPS_BIT(12)
 
#define MIPS_COP_0_CAUSE   MIPS_BIT(13)
 
#define MIPS_COP_0_EXC_PC   MIPS_BIT(14)
 
#define MIPS_COP_0_PRID   MIPS_BIT(15)
 
#define MIPS_COP_0_TLB_LOW   MIPS_BIT(2)
 
#define MIPS_COP_0_TLB_LO0   MIPS_BIT(2)
 
#define MIPS_COP_0_TLB_LO1   MIPS_BIT(3)
 
#define MIPS_COP_0_TLB_PG_MASK   MIPS_BIT(5)
 
#define MIPS_COP_0_TLB_WIRED   MIPS_BIT(6)
 
#define MIPS_COP_0_COUNT   MIPS_BIT(9)
 
#define MIPS_COP_0_COMPARE   MIPS_BIT(11)
 
#define MIPS_COP_0_CONFIG   MIPS_BIT(16)
 
#define MIPS_COP_0_LLADDR   MIPS_BIT(17)
 
#define MIPS_COP_0_WATCH_LO   MIPS_BIT(18)
 
#define MIPS_COP_0_WATCH_HI   MIPS_BIT(19)
 
#define MIPS_COP_0_TLB_XCONTEXT   MIPS_BIT(20)
 
#define MIPS_COP_0_ECC   MIPS_BIT(26)
 
#define MIPS_COP_0_CACHE_ERR   MIPS_BIT(27)
 
#define MIPS_COP_0_TAG_LO   MIPS_BIT(28)
 
#define MIPS_COP_0_TAG_HI   MIPS_BIT(29)
 
#define MIPS_COP_0_ERROR_PC   MIPS_BIT(30)
 
#define MIPS_COP_0_DEBUG   MIPS_BIT(23)
 
#define MIPS_COP_0_DEPC   MIPS_BIT(24)
 
#define MIPS_COP_0_PERFCNT   MIPS_BIT(25)
 
#define MIPS_COP_0_DATA_LO   MIPS_BIT(28)
 
#define MIPS_COP_0_DATA_HI   MIPS_BIT(29)
 
#define MIPS_COP_0_DESAVE   MIPS_BIT(31)
 
#define MIPS_BREAK_INSTR   0x0000000d
 
#define MIPS_BREAK_VAL_MASK   0x03ff0000
 
#define MIPS_BREAK_VAL_SHIFT   16
 
#define MIPS_BREAK_KDB_VAL   512
 
#define MIPS_BREAK_SSTEP_VAL   513
 
#define MIPS_BREAK_BRKPT_VAL   514
 
#define MIPS_BREAK_SOVER_VAL   515
 
#define MIPS_BREAK_KDB
 
#define MIPS_BREAK_SSTEP
 
#define MIPS_BREAK_BRKPT
 
#define MIPS_BREAK_SOVER
 
#define MIPS_MIN_CACHE_SIZE   (16 * 1024)
 
#define MIPS_MAX_CACHE_SIZE   (256 * 1024)
 
#define MIPS3_MAX_PCACHE_SIZE   (32 * 1024) /* max. primary cache size */
 
#define MIPS_FPU_ID   $0
 
#define MIPS_FPU_CSR   $31
 
#define MIPS_FPU_ROUNDING_BITS   0x00000003
 
#define MIPS_FPU_ROUND_RN   0x00000000
 
#define MIPS_FPU_ROUND_RZ   0x00000001
 
#define MIPS_FPU_ROUND_RP   0x00000002
 
#define MIPS_FPU_ROUND_RM   0x00000003
 
#define MIPS_FPU_STICKY_BITS   0x0000007c
 
#define MIPS_FPU_STICKY_INEXACT   0x00000004
 
#define MIPS_FPU_STICKY_UNDERFLOW   0x00000008
 
#define MIPS_FPU_STICKY_OVERFLOW   0x00000010
 
#define MIPS_FPU_STICKY_DIV0   0x00000020
 
#define MIPS_FPU_STICKY_INVALID   0x00000040
 
#define MIPS_FPU_ENABLE_BITS   0x00000f80
 
#define MIPS_FPU_ENABLE_INEXACT   0x00000080
 
#define MIPS_FPU_ENABLE_UNDERFLOW   0x00000100
 
#define MIPS_FPU_ENABLE_OVERFLOW   0x00000200
 
#define MIPS_FPU_ENABLE_DIV0   0x00000400
 
#define MIPS_FPU_ENABLE_INVALID   0x00000800
 
#define MIPS_FPU_EXCEPTION_BITS   0x0003f000
 
#define MIPS_FPU_EXCEPTION_INEXACT   0x00001000
 
#define MIPS_FPU_EXCEPTION_UNDERFLOW   0x00002000
 
#define MIPS_FPU_EXCEPTION_OVERFLOW   0x00004000
 
#define MIPS_FPU_EXCEPTION_DIV0   0x00008000
 
#define MIPS_FPU_EXCEPTION_INVALID   0x00010000
 
#define MIPS_FPU_EXCEPTION_UNIMPL   0x00020000
 
#define MIPS_FPU_COND_BIT   0x00800000
 
#define MIPS_FPU_FLUSH_BIT   0x01000000 /* r4k, MBZ on r3k */
 
#define MIPS1_FPC_MBZ_BITS   0xff7c0000
 
#define MIPS3_FPC_MBZ_BITS   0xfe7c0000
 
#define MIPS_OPCODE_SHIFT   26
 
#define MIPS_OPCODE_C1   0x11
 
#define MIPS1_TLB_PFN   0xfffff000
 
#define MIPS1_TLB_NON_CACHEABLE_BIT   0x00000800
 
#define MIPS1_TLB_DIRTY_BIT   0x00000400
 
#define MIPS1_TLB_VALID_BIT   0x00000200
 
#define MIPS1_TLB_GLOBAL_BIT   0x00000100
 
#define MIPS3_TLB_PFN   0x3fffffc0
 
#define MIPS3_TLB_ATTR_MASK   0x00000038
 
#define MIPS3_TLB_ATTR_SHIFT   3
 
#define MIPS3_TLB_DIRTY_BIT   0x00000004
 
#define MIPS3_TLB_VALID_BIT   0x00000002
 
#define MIPS3_TLB_GLOBAL_BIT   0x00000001
 
#define MIPS1_TLB_PHYS_PAGE_SHIFT   12
 
#define MIPS3_TLB_PHYS_PAGE_SHIFT   6
 
#define MIPS1_TLB_PF_NUM   MIPS1_TLB_PFN
 
#define MIPS3_TLB_PF_NUM   MIPS3_TLB_PFN
 
#define MIPS1_TLB_MOD_BIT   MIPS1_TLB_DIRTY_BIT
 
#define MIPS3_TLB_MOD_BIT   MIPS3_TLB_DIRTY_BIT
 
#define MIPS3_TLB_ATTR_WT   0 /* IDT */
 
#define MIPS3_TLB_ATTR_WT_WRITEALLOCATE   1 /* IDT */
 
#define MIPS3_TLB_ATTR_UNCACHED   2 /* R4000/R4400, IDT */
 
#define MIPS3_TLB_ATTR_WB_NONCOHERENT   3 /* R4000/R4400, IDT */
 
#define MIPS3_TLB_ATTR_WB_EXCLUSIVE   4 /* R4000/R4400 */
 
#define MIPS3_TLB_ATTR_WB_SHARABLE   5 /* R4000/R4400 */
 
#define MIPS3_TLB_ATTR_WB_UPDATE   6 /* R4000/R4400 */
 
#define MIPS4_TLB_ATTR_UNCACHED_ACCELERATED   7 /* R10000 */
 
#define MIPS1_TLB_VPN   0xfffff000
 
#define MIPS1_TLB_PID   0x00000fc0
 
#define MIPS1_TLB_PID_SHIFT   6
 
#define MIPS3_TLB_VPN2   0xffffe000
 
#define MIPS3_TLB_ASID   0x000000ff
 
#define MIPS1_TLB_VIRT_PAGE_NUM   MIPS1_TLB_VPN
 
#define MIPS3_TLB_VIRT_PAGE_NUM   MIPS3_TLB_VPN2
 
#define MIPS3_TLB_PID   MIPS3_TLB_ASID
 
#define MIPS_TLB_VIRT_PAGE_SHIFT   12
 
#define MIPS1_TLB_INDEX_SHIFT   8
 
#define MIPS1_TLB_FIRST_RAND_ENTRY   8
 
#define MIPS3_TLB_WIRED_UPAGES   1
 
#define MIPS1_TLB_NUM_PIDS   64
 
#define MIPS3_TLB_NUM_ASIDS   256
 
#define MIPS_TLB_PID_SHIFT   ((MIPS_HAS_R4K_MMU) ? 0 : MIPS1_TLB_PID_SHIFT)
 
#define MIPS_TLB_NUM_PIDS   ((MIPS_HAS_R4K_MMU) ? MIPS3_TLB_NUM_ASIDS : MIPS1_TLB_NUM_PIDS)
 
#define MIPS_R2000   0x01 /* MIPS R2000 ISA I */
 
#define MIPS_R3000   0x02 /* MIPS R3000 ISA I */
 
#define MIPS_R6000   0x03 /* MIPS R6000 ISA II */
 
#define MIPS_R4000   0x04 /* MIPS R4000/R4400 ISA III */
 
#define MIPS_R3LSI   0x05 /* LSI Logic R3000 derivative ISA I */
 
#define MIPS_R6000A   0x06 /* MIPS R6000A ISA II */
 
#define MIPS_R3IDT   0x07 /* IDT R3041 or RC36100 ISA I */
 
#define MIPS_R10000   0x09 /* MIPS R10000 ISA IV */
 
#define MIPS_R4200   0x0a /* NEC VR4200 ISA III */
 
#define MIPS_R4300   0x0b /* NEC VR4300 ISA III */
 
#define MIPS_R4100   0x0c /* NEC VR4100 ISA III */
 
#define MIPS_R12000   0x0e /* MIPS R12000 ISA IV */
 
#define MIPS_R14000   0x0f /* MIPS R14000 ISA IV */
 
#define MIPS_R8000   0x10 /* MIPS R8000 Blackbird/TFP ISA IV */
 
#define MIPS_RC32300   0x18 /* IDT RC32334,332,355 ISA 32 */
 
#define MIPS_R4600   0x20 /* QED R4600 Orion ISA III */
 
#define MIPS_R4700   0x21 /* QED R4700 Orion ISA III */
 
#define MIPS_R3SONY   0x21 /* Sony R3000 based ISA I */
 
#define MIPS_R4650   0x22 /* QED R4650 ISA III */
 
#define MIPS_TX3900   0x22 /* Toshiba TX39 family ISA I */
 
#define MIPS_R5000   0x23 /* MIPS R5000 ISA IV */
 
#define MIPS_R3NKK   0x23 /* NKK R3000 based ISA I */
 
#define MIPS_RC32364   0x26 /* IDT RC32364 ISA 32 */
 
#define MIPS_RM7000   0x27 /* QED RM7000 ISA IV */
 
#define MIPS_RM5200   0x28 /* QED RM5200s ISA IV */
 
#define MIPS_TX4900   0x2d /* Toshiba TX49 family ISA III */
 
#define MIPS_R5900   0x2e /* Toshiba R5900 (EECore) ISA --- */
 
#define MIPS_RC64470   0x30 /* IDT RC64474/RC64475 ISA III */
 
#define MIPS_TX7900   0x38 /* Toshiba TX79 ISA III+*/
 
#define MIPS_R5400   0x54 /* NEC VR5400 ISA IV */
 
#define MIPS_R5500   0x55 /* NEC VR5500 ISA IV */
 
#define MIPS_REV_R3000   0x20
 
#define MIPS_REV_R3000A   0x30
 
#define MIPS_REV_TX3912   0x10
 
#define MIPS_REV_TX3922   0x30
 
#define MIPS_REV_TX3927   0x40
 
#define MIPS_REV_R4000_A   0x00
 
#define MIPS_REV_R4000_B   0x22
 
#define MIPS_REV_R4000_C   0x30
 
#define MIPS_REV_R4400_A   0x40
 
#define MIPS_REV_R4400_B   0x50
 
#define MIPS_REV_R4400_C   0x60
 
#define MIPS_REV_TX4927   0x22
 
#define MIPS_4Kc   0x80 /* MIPS 4Kc ISA 32 */
 
#define MIPS_5Kc   0x81 /* MIPS 5Kc ISA 64 */
 
#define MIPS_20Kc   0x82 /* MIPS 20Kc ISA 64 */
 
#define MIPS_4Kmp   0x83 /* MIPS 4Km/4Kp ISA 32 */
 
#define MIPS_4KEc   0x84 /* MIPS 4KEc ISA 32 */
 
#define MIPS_4KEmp   0x85 /* MIPS 4KEm/4KEp ISA 32 */
 
#define MIPS_4KSc   0x86 /* MIPS 4KSc ISA 32 */
 
#define MIPS_M4K   0x87 /* MIPS M4K ISA 32 Rel 2 */
 
#define MIPS_25Kf   0x88 /* MIPS 25Kf ISA 64 */
 
#define MIPS_5KE   0x89 /* MIPS 5KE ISA 64 Rel 2 */
 
#define MIPS_4KEc_R2   0x90 /* MIPS 4KEc_R2 ISA 32 Rel 2 */
 
#define MIPS_4KEmp_R2   0x91 /* MIPS 4KEm/4KEp_R2 ISA 32 Rel 2 */
 
#define MIPS_4KSd   0x92 /* MIPS 4KSd ISA 32 Rel 2 */
 
#define MIPS_24K   0x93 /* MIPS 24K ? */
 
#define MIPS_34K   0x95 /* MIPS 34K ? */
 
#define MIPS_24KE   0x96 /* MIPS 24KE ? */
 
#define MIPS_74K   0x97 /* MIPS 74K ? */
 
#define MIPS_AU_REV1   0x01 /* Alchemy Au1000 (Rev 1) ISA 32 */
 
#define MIPS_AU_REV2   0x02 /* Alchemy Au1000 (Rev 2) ISA 32 */
 
#define MIPS_AU1000   0x00
 
#define MIPS_AU1500   0x01
 
#define MIPS_AU1100   0x02
 
#define MIPS_AU1550   0x03
 
#define MIPS_SB1   0x01 /* SiByte SB1 ISA 64 */
 
#define MIPS_SR7100   0x04 /* SandCraft SR7100 ISA 64 */
 
#define MIPS_SOFT   0x00 /* Software emulation ISA I */
 
#define MIPS_R2360   0x01 /* MIPS R2360 FPC ISA I */
 
#define MIPS_R2010   0x02 /* MIPS R2010 FPC ISA I */
 
#define MIPS_R3010   0x03 /* MIPS R3010 FPC ISA I */
 
#define MIPS_R6010   0x04 /* MIPS R6010 FPC ISA II */
 
#define MIPS_R4010   0x05 /* MIPS R4010 FPC ISA II */
 
#define MIPS_R31LSI   0x06 /* LSI Logic derivate ISA I */
 
#define MIPS_R3TOSH   0x22 /* Toshiba R3000 based FPU ISA I */
 

Macro Definition Documentation

◆ COP0_HAZARD_FPUENABLE

#define COP0_HAZARD_FPUENABLE   nop; nop; nop; nop;

Definition at line 104 of file mips_cpuregs.h.

◆ COP0_SYNC

#define COP0_SYNC   /* nothing */

Definition at line 103 of file mips_cpuregs.h.

◆ MIPS1_CACHE_MISS

#define MIPS1_CACHE_MISS   0x00080000

Definition at line 178 of file mips_cpuregs.h.

◆ MIPS1_CNTXT_BAD_VPN

#define MIPS1_CNTXT_BAD_VPN   0x001FFFFC

Definition at line 281 of file mips_cpuregs.h.

◆ MIPS1_CNTXT_PTE_BASE

#define MIPS1_CNTXT_PTE_BASE   0xFFE00000

Definition at line 280 of file mips_cpuregs.h.

◆ MIPS1_CR_EXC_CODE

#define MIPS1_CR_EXC_CODE   0x0000003C /* four bits */

Definition at line 122 of file mips_cpuregs.h.

◆ MIPS1_FPC_MBZ_BITS

#define MIPS1_FPC_MBZ_BITS   0xff7c0000

Definition at line 581 of file mips_cpuregs.h.

◆ MIPS1_GEN_EXC_VEC

#define MIPS1_GEN_EXC_VEC   0x80000080

Definition at line 404 of file mips_cpuregs.h.

◆ MIPS1_ISOL_CACHES

#define MIPS1_ISOL_CACHES   0x00010000

Definition at line 181 of file mips_cpuregs.h.

◆ MIPS1_PARITY_ERR

#define MIPS1_PARITY_ERR   0x00100000

Definition at line 177 of file mips_cpuregs.h.

◆ MIPS1_PARITY_ZERO

#define MIPS1_PARITY_ZERO   0x00040000

Definition at line 179 of file mips_cpuregs.h.

◆ MIPS1_SR_INT_ENA_OLD

#define MIPS1_SR_INT_ENA_OLD   0x00000010 /* 2nd stacked KU/IE*/

Definition at line 184 of file mips_cpuregs.h.

◆ MIPS1_SR_INT_ENA_PREV

#define MIPS1_SR_INT_ENA_PREV   0x00000004 /* 1st stacked KU/IE*/

Definition at line 186 of file mips_cpuregs.h.

◆ MIPS1_SR_KU_CUR

#define MIPS1_SR_KU_CUR   0x00000002 /* current KU */

Definition at line 187 of file mips_cpuregs.h.

◆ MIPS1_SR_KU_OLD

#define MIPS1_SR_KU_OLD   0x00000020 /* 2nd stacked KU/IE*/

Definition at line 183 of file mips_cpuregs.h.

◆ MIPS1_SR_KU_PREV

#define MIPS1_SR_KU_PREV   0x00000008 /* 1st stacked KU/IE*/

Definition at line 185 of file mips_cpuregs.h.

◆ MIPS1_SWAP_CACHES

#define MIPS1_SWAP_CACHES   0x00020000

Definition at line 180 of file mips_cpuregs.h.

◆ MIPS1_TLB_DIRTY_BIT

#define MIPS1_TLB_DIRTY_BIT   0x00000400

Definition at line 597 of file mips_cpuregs.h.

◆ MIPS1_TLB_FIRST_RAND_ENTRY

#define MIPS1_TLB_FIRST_RAND_ENTRY   8

Definition at line 659 of file mips_cpuregs.h.

◆ MIPS1_TLB_GLOBAL_BIT

#define MIPS1_TLB_GLOBAL_BIT   0x00000100

Definition at line 599 of file mips_cpuregs.h.

◆ MIPS1_TLB_INDEX_SHIFT

#define MIPS1_TLB_INDEX_SHIFT   8

Definition at line 654 of file mips_cpuregs.h.

◆ MIPS1_TLB_MOD_BIT

#define MIPS1_TLB_MOD_BIT   MIPS1_TLB_DIRTY_BIT

Definition at line 612 of file mips_cpuregs.h.

◆ MIPS1_TLB_NON_CACHEABLE_BIT

#define MIPS1_TLB_NON_CACHEABLE_BIT   0x00000800

Definition at line 596 of file mips_cpuregs.h.

◆ MIPS1_TLB_NUM_PIDS

#define MIPS1_TLB_NUM_PIDS   64

Definition at line 665 of file mips_cpuregs.h.

◆ MIPS1_TLB_PF_NUM

#define MIPS1_TLB_PF_NUM   MIPS1_TLB_PFN

Definition at line 610 of file mips_cpuregs.h.

◆ MIPS1_TLB_PFN

#define MIPS1_TLB_PFN   0xfffff000

Definition at line 595 of file mips_cpuregs.h.

◆ MIPS1_TLB_PHYS_PAGE_SHIFT

#define MIPS1_TLB_PHYS_PAGE_SHIFT   12

Definition at line 608 of file mips_cpuregs.h.

◆ MIPS1_TLB_PID

#define MIPS1_TLB_PID   0x00000fc0

Definition at line 640 of file mips_cpuregs.h.

◆ MIPS1_TLB_PID_SHIFT

#define MIPS1_TLB_PID_SHIFT   6

Definition at line 641 of file mips_cpuregs.h.

◆ MIPS1_TLB_VALID_BIT

#define MIPS1_TLB_VALID_BIT   0x00000200

Definition at line 598 of file mips_cpuregs.h.

◆ MIPS1_TLB_VIRT_PAGE_NUM

#define MIPS1_TLB_VIRT_PAGE_NUM   MIPS1_TLB_VPN

Definition at line 646 of file mips_cpuregs.h.

◆ MIPS1_TLB_VPN

#define MIPS1_TLB_VPN   0xfffff000

Definition at line 639 of file mips_cpuregs.h.

◆ MIPS3_CACHE_ERR_EXC_VEC

#define MIPS3_CACHE_ERR_EXC_VEC   0x80000100

Definition at line 410 of file mips_cpuregs.h.

◆ MIPS3_CNTXT_BAD_VPN2

#define MIPS3_CNTXT_BAD_VPN2   0x007FFFF0

Definition at line 284 of file mips_cpuregs.h.

◆ MIPS3_CNTXT_PTE_BASE

#define MIPS3_CNTXT_PTE_BASE   0xFF800000

Definition at line 283 of file mips_cpuregs.h.

◆ MIPS3_CONFIG_BE

#define MIPS3_CONFIG_BE   0x00008000

Definition at line 329 of file mips_cpuregs.h.

◆ MIPS3_CONFIG_C_4100BASE

#define MIPS3_CONFIG_C_4100BASE   0x0400 /* base is 2^10 if CS=1 */

Definition at line 315 of file mips_cpuregs.h.

◆ MIPS3_CONFIG_C_DEFBASE

#define MIPS3_CONFIG_C_DEFBASE   0x1000 /* default base 2^12 */

Definition at line 311 of file mips_cpuregs.h.

◆ MIPS3_CONFIG_CACHE_L1_LSIZE

#define MIPS3_CONFIG_CACHE_L1_LSIZE (   config,
  bit 
)    (((config) & (bit)) ? 32 : 16)

Definition at line 304 of file mips_cpuregs.h.

◆ MIPS3_CONFIG_CACHE_L2_LSIZE

#define MIPS3_CONFIG_CACHE_L2_LSIZE (   config)    (0x10 << (((config) & MIPS3_CONFIG_SB_MASK) >> MIPS3_CONFIG_SB_SHIFT))

Definition at line 350 of file mips_cpuregs.h.

◆ MIPS3_CONFIG_CACHE_SIZE

#define MIPS3_CONFIG_CACHE_SIZE (   config,
  mask,
  base,
  shift 
)    ((base) << (((config) & (mask)) >> (shift)))

Definition at line 316 of file mips_cpuregs.h.

◆ MIPS3_CONFIG_CM

#define MIPS3_CONFIG_CM   0x80000000

Definition at line 362 of file mips_cpuregs.h.

◆ MIPS3_CONFIG_CS

#define MIPS3_CONFIG_CS   0x00001000

Definition at line 314 of file mips_cpuregs.h.

◆ MIPS3_CONFIG_CU

#define MIPS3_CONFIG_CU   0x00000008

Definition at line 300 of file mips_cpuregs.h.

◆ MIPS3_CONFIG_DB

#define MIPS3_CONFIG_DB   0x00000010 /* Primary D-cache line size */

Definition at line 302 of file mips_cpuregs.h.

◆ MIPS3_CONFIG_DC_MASK

#define MIPS3_CONFIG_DC_MASK   0x000001c0 /* Primary D-cache size */

Definition at line 307 of file mips_cpuregs.h.

◆ MIPS3_CONFIG_DC_SHIFT

#define MIPS3_CONFIG_DC_SHIFT   6

Definition at line 308 of file mips_cpuregs.h.

◆ MIPS3_CONFIG_EB

#define MIPS3_CONFIG_EB   0x00002000

Definition at line 323 of file mips_cpuregs.h.

◆ MIPS3_CONFIG_EC_MASK

#define MIPS3_CONFIG_EC_MASK   0x70000000

Definition at line 358 of file mips_cpuregs.h.

◆ MIPS3_CONFIG_EC_SHIFT

#define MIPS3_CONFIG_EC_SHIFT   28

Definition at line 359 of file mips_cpuregs.h.

◆ MIPS3_CONFIG_EM

#define MIPS3_CONFIG_EM   0x00004000

Definition at line 326 of file mips_cpuregs.h.

◆ MIPS3_CONFIG_EP_MASK

#define MIPS3_CONFIG_EP_MASK   0x0f000000

Definition at line 354 of file mips_cpuregs.h.

◆ MIPS3_CONFIG_EP_SHIFT

#define MIPS3_CONFIG_EP_SHIFT   24

Definition at line 355 of file mips_cpuregs.h.

◆ MIPS3_CONFIG_EW_MASK

#define MIPS3_CONFIG_EW_MASK   0x000c0000

Definition at line 338 of file mips_cpuregs.h.

◆ MIPS3_CONFIG_EW_SHIFT

#define MIPS3_CONFIG_EW_SHIFT   18

Definition at line 339 of file mips_cpuregs.h.

◆ MIPS3_CONFIG_IB

#define MIPS3_CONFIG_IB   0x00000020 /* Primary I-cache line size */

Definition at line 303 of file mips_cpuregs.h.

◆ MIPS3_CONFIG_IC_MASK

#define MIPS3_CONFIG_IC_MASK   0x00000e00 /* Primary I-cache size */

Definition at line 309 of file mips_cpuregs.h.

◆ MIPS3_CONFIG_IC_SHIFT

#define MIPS3_CONFIG_IC_SHIFT   9

Definition at line 310 of file mips_cpuregs.h.

◆ MIPS3_CONFIG_K0_MASK

#define MIPS3_CONFIG_K0_MASK   0x00000007

Definition at line 293 of file mips_cpuregs.h.

◆ MIPS3_CONFIG_SB_MASK

#define MIPS3_CONFIG_SB_MASK   0x00c00000

Definition at line 348 of file mips_cpuregs.h.

◆ MIPS3_CONFIG_SB_SHIFT

#define MIPS3_CONFIG_SB_SHIFT   22

Definition at line 349 of file mips_cpuregs.h.

◆ MIPS3_CONFIG_SC

#define MIPS3_CONFIG_SC   0x00020000

Definition at line 335 of file mips_cpuregs.h.

◆ MIPS3_CONFIG_SE

#define MIPS3_CONFIG_SE   0x00001000

Definition at line 320 of file mips_cpuregs.h.

◆ MIPS3_CONFIG_SM

#define MIPS3_CONFIG_SM   0x00010000

Definition at line 332 of file mips_cpuregs.h.

◆ MIPS3_CONFIG_SS

#define MIPS3_CONFIG_SS   0x00200000

Definition at line 345 of file mips_cpuregs.h.

◆ MIPS3_CONFIG_SW

#define MIPS3_CONFIG_SW   0x00100000

Definition at line 342 of file mips_cpuregs.h.

◆ MIPS3_CR_EXC_CODE

#define MIPS3_CR_EXC_CODE   0x0000007C /* five bits */

Definition at line 123 of file mips_cpuregs.h.

◆ MIPS3_FPC_MBZ_BITS

#define MIPS3_FPC_MBZ_BITS   0xfe7c0000

Definition at line 582 of file mips_cpuregs.h.

◆ MIPS3_GEN_EXC_VEC

#define MIPS3_GEN_EXC_VEC   0x80000180

Definition at line 411 of file mips_cpuregs.h.

◆ MIPS3_HARD_INT_MASK

#define MIPS3_HARD_INT_MASK   (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5)

Definition at line 274 of file mips_cpuregs.h.

◆ MIPS3_INT_MASK

#define MIPS3_INT_MASK   (MIPS_INT_MASK & ~MIPS_INT_MASK_5)

Definition at line 273 of file mips_cpuregs.h.

◆ MIPS3_INTR_EXC_VEC

#define MIPS3_INTR_EXC_VEC   0x80000200

Definition at line 422 of file mips_cpuregs.h.

◆ MIPS3_MAX_PCACHE_SIZE

#define MIPS3_MAX_PCACHE_SIZE   (32 * 1024) /* max. primary cache size */

Definition at line 544 of file mips_cpuregs.h.

◆ MIPS3_SR_DIAG_CE

#define MIPS3_SR_DIAG_CE   0x00020000

Definition at line 217 of file mips_cpuregs.h.

◆ MIPS3_SR_DIAG_CH

#define MIPS3_SR_DIAG_CH   0x00040000

Definition at line 216 of file mips_cpuregs.h.

◆ MIPS3_SR_DIAG_DL

#define MIPS3_SR_DIAG_DL   0x01000000 /* QED 52xx */

Definition at line 211 of file mips_cpuregs.h.

◆ MIPS3_SR_DIAG_IL

#define MIPS3_SR_DIAG_IL   0x00800000 /* QED 52xx */

Definition at line 212 of file mips_cpuregs.h.

◆ MIPS3_SR_DIAG_PE

#define MIPS3_SR_DIAG_PE   0x00010000

Definition at line 218 of file mips_cpuregs.h.

◆ MIPS3_SR_EIE

#define MIPS3_SR_EIE   0x00100000 /* TX79/R5900 */

Definition at line 214 of file mips_cpuregs.h.

◆ MIPS3_SR_ERL

#define MIPS3_SR_ERL   0x00000004

Definition at line 226 of file mips_cpuregs.h.

◆ MIPS3_SR_EXL

#define MIPS3_SR_EXL   0x00000002

Definition at line 227 of file mips_cpuregs.h.

◆ MIPS3_SR_FR

#define MIPS3_SR_FR   0x04000000

Definition at line 208 of file mips_cpuregs.h.

◆ MIPS3_SR_KSU_KERNEL

#define MIPS3_SR_KSU_KERNEL   0x00000000

Definition at line 225 of file mips_cpuregs.h.

◆ MIPS3_SR_KSU_MASK

#define MIPS3_SR_KSU_MASK   0x00000018

Definition at line 222 of file mips_cpuregs.h.

◆ MIPS3_SR_KSU_SUPER

#define MIPS3_SR_KSU_SUPER   0x00000008

Definition at line 224 of file mips_cpuregs.h.

◆ MIPS3_SR_KSU_USER

#define MIPS3_SR_KSU_USER   0x00000010

Definition at line 223 of file mips_cpuregs.h.

◆ MIPS3_SR_KX

#define MIPS3_SR_KX   0x00000080

Definition at line 219 of file mips_cpuregs.h.

◆ MIPS3_SR_NMI

#define MIPS3_SR_NMI   0x00080000 /* MIPS32/64 */

Definition at line 215 of file mips_cpuregs.h.

◆ MIPS3_SR_RE

#define MIPS3_SR_RE   0x02000000

Definition at line 209 of file mips_cpuregs.h.

◆ MIPS3_SR_RP

#define MIPS3_SR_RP   0x08000000

Definition at line 207 of file mips_cpuregs.h.

◆ MIPS3_SR_SR

#define MIPS3_SR_SR   0x00100000

Definition at line 213 of file mips_cpuregs.h.

◆ MIPS3_SR_SX

#define MIPS3_SR_SX   0x00000040

Definition at line 220 of file mips_cpuregs.h.

◆ MIPS3_SR_UX

#define MIPS3_SR_UX   0x00000020

Definition at line 221 of file mips_cpuregs.h.

◆ MIPS3_SR_XX

#define MIPS3_SR_XX   0x80000000

Definition at line 206 of file mips_cpuregs.h.

◆ MIPS3_TLB_ASID

#define MIPS3_TLB_ASID   0x000000ff

Definition at line 644 of file mips_cpuregs.h.

◆ MIPS3_TLB_ATTR_MASK

#define MIPS3_TLB_ATTR_MASK   0x00000038

Definition at line 602 of file mips_cpuregs.h.

◆ MIPS3_TLB_ATTR_SHIFT

#define MIPS3_TLB_ATTR_SHIFT   3

Definition at line 603 of file mips_cpuregs.h.

◆ MIPS3_TLB_ATTR_UNCACHED

#define MIPS3_TLB_ATTR_UNCACHED   2 /* R4000/R4400, IDT */

Definition at line 628 of file mips_cpuregs.h.

◆ MIPS3_TLB_ATTR_WB_EXCLUSIVE

#define MIPS3_TLB_ATTR_WB_EXCLUSIVE   4 /* R4000/R4400 */

Definition at line 630 of file mips_cpuregs.h.

◆ MIPS3_TLB_ATTR_WB_NONCOHERENT

#define MIPS3_TLB_ATTR_WB_NONCOHERENT   3 /* R4000/R4400, IDT */

Definition at line 629 of file mips_cpuregs.h.

◆ MIPS3_TLB_ATTR_WB_SHARABLE

#define MIPS3_TLB_ATTR_WB_SHARABLE   5 /* R4000/R4400 */

Definition at line 631 of file mips_cpuregs.h.

◆ MIPS3_TLB_ATTR_WB_UPDATE

#define MIPS3_TLB_ATTR_WB_UPDATE   6 /* R4000/R4400 */

Definition at line 632 of file mips_cpuregs.h.

◆ MIPS3_TLB_ATTR_WT

#define MIPS3_TLB_ATTR_WT   0 /* IDT */

Definition at line 626 of file mips_cpuregs.h.

◆ MIPS3_TLB_ATTR_WT_WRITEALLOCATE

#define MIPS3_TLB_ATTR_WT_WRITEALLOCATE   1 /* IDT */

Definition at line 627 of file mips_cpuregs.h.

◆ MIPS3_TLB_DIRTY_BIT

#define MIPS3_TLB_DIRTY_BIT   0x00000004

Definition at line 604 of file mips_cpuregs.h.

◆ MIPS3_TLB_GLOBAL_BIT

#define MIPS3_TLB_GLOBAL_BIT   0x00000001

Definition at line 606 of file mips_cpuregs.h.

◆ MIPS3_TLB_MOD_BIT

#define MIPS3_TLB_MOD_BIT   MIPS3_TLB_DIRTY_BIT

Definition at line 613 of file mips_cpuregs.h.

◆ MIPS3_TLB_NUM_ASIDS

#define MIPS3_TLB_NUM_ASIDS   256

Definition at line 666 of file mips_cpuregs.h.

◆ MIPS3_TLB_PF_NUM

#define MIPS3_TLB_PF_NUM   MIPS3_TLB_PFN

Definition at line 611 of file mips_cpuregs.h.

◆ MIPS3_TLB_PFN

#define MIPS3_TLB_PFN   0x3fffffc0

Definition at line 601 of file mips_cpuregs.h.

◆ MIPS3_TLB_PHYS_PAGE_SHIFT

#define MIPS3_TLB_PHYS_PAGE_SHIFT   6

Definition at line 609 of file mips_cpuregs.h.

◆ MIPS3_TLB_PID

#define MIPS3_TLB_PID   MIPS3_TLB_ASID

Definition at line 648 of file mips_cpuregs.h.

◆ MIPS3_TLB_VALID_BIT

#define MIPS3_TLB_VALID_BIT   0x00000002

Definition at line 605 of file mips_cpuregs.h.

◆ MIPS3_TLB_VIRT_PAGE_NUM

#define MIPS3_TLB_VIRT_PAGE_NUM   MIPS3_TLB_VPN2

Definition at line 647 of file mips_cpuregs.h.

◆ MIPS3_TLB_VPN2

#define MIPS3_TLB_VPN2   0xffffe000

Definition at line 643 of file mips_cpuregs.h.

◆ MIPS3_TLB_WIRED_UPAGES

#define MIPS3_TLB_WIRED_UPAGES   1

Definition at line 660 of file mips_cpuregs.h.

◆ MIPS3_VA_TO_CINDEX

#define MIPS3_VA_TO_CINDEX (   x)    ((unsigned)(x) & 0xffffff | MIPS_KSEG0_START)

Definition at line 95 of file mips_cpuregs.h.

◆ MIPS3_XTLB_MISS_EXC_VEC

#define MIPS3_XTLB_MISS_EXC_VEC   0x80000080

Definition at line 409 of file mips_cpuregs.h.

◆ MIPS4_CONFIG_BE

#define MIPS4_CONFIG_BE   0x00008000 /* MemEnd */

Definition at line 377 of file mips_cpuregs.h.

◆ MIPS4_CONFIG_CACHE_L2_LSIZE

#define MIPS4_CONFIG_CACHE_L2_LSIZE (   config)    (((config) & MIPS4_CONFIG_SB) ? 128 : 64)

Definition at line 390 of file mips_cpuregs.h.

◆ MIPS4_CONFIG_CACHE_SIZE

#define MIPS4_CONFIG_CACHE_SIZE (   config,
  mask,
  base,
  shift 
)    ((base) << (((config) & (mask)) >> (shift)))

Definition at line 387 of file mips_cpuregs.h.

◆ MIPS4_CONFIG_CT

#define MIPS4_CONFIG_CT   0x00000020 /* CohPrcReqTar */

Definition at line 371 of file mips_cpuregs.h.

◆ MIPS4_CONFIG_DC_MASK

#define MIPS4_CONFIG_DC_MASK   0x1c000000 /* Primary D-Cache size */

Definition at line 381 of file mips_cpuregs.h.

◆ MIPS4_CONFIG_DC_SHIFT

#define MIPS4_CONFIG_DC_SHIFT   26

Definition at line 384 of file mips_cpuregs.h.

◆ MIPS4_CONFIG_DN_MASK

#define MIPS4_CONFIG_DN_MASK   0x00000018 /* Device number */

Definition at line 370 of file mips_cpuregs.h.

◆ MIPS4_CONFIG_EC_MASK

#define MIPS4_CONFIG_EC_MASK   0x00001e00 /* SysClkDiv */

Definition at line 374 of file mips_cpuregs.h.

◆ MIPS4_CONFIG_IC_MASK

#define MIPS4_CONFIG_IC_MASK   0xe0000000 /* Primary I-Cache size */

Definition at line 382 of file mips_cpuregs.h.

◆ MIPS4_CONFIG_IC_SHIFT

#define MIPS4_CONFIG_IC_SHIFT   29

Definition at line 385 of file mips_cpuregs.h.

◆ MIPS4_CONFIG_K0_MASK

#define MIPS4_CONFIG_K0_MASK   MIPS3_CONFIG_K0_MASK

Definition at line 369 of file mips_cpuregs.h.

◆ MIPS4_CONFIG_PE

#define MIPS4_CONFIG_PE   0x00000040 /* PreElmReq */

Definition at line 372 of file mips_cpuregs.h.

◆ MIPS4_CONFIG_PM_MASK

#define MIPS4_CONFIG_PM_MASK   0x00000180 /* PreReqMax */

Definition at line 373 of file mips_cpuregs.h.

◆ MIPS4_CONFIG_RESERVED

#define MIPS4_CONFIG_RESERVED   0x03c00000 /* Reserved wired 0 */

Definition at line 380 of file mips_cpuregs.h.

◆ MIPS4_CONFIG_SB

#define MIPS4_CONFIG_SB   0x00002000 /* SCBlkSize */

Definition at line 375 of file mips_cpuregs.h.

◆ MIPS4_CONFIG_SC_MASK

#define MIPS4_CONFIG_SC_MASK   0x00380000 /* SCClkDiv */

Definition at line 379 of file mips_cpuregs.h.

◆ MIPS4_CONFIG_SK

#define MIPS4_CONFIG_SK   0x00004000 /* SCColEn */

Definition at line 376 of file mips_cpuregs.h.

◆ MIPS4_CONFIG_SS_MASK

#define MIPS4_CONFIG_SS_MASK   0x00070000 /* SCSize */

Definition at line 378 of file mips_cpuregs.h.

◆ MIPS4_TLB_ATTR_UNCACHED_ACCELERATED

#define MIPS4_TLB_ATTR_UNCACHED_ACCELERATED   7 /* R10000 */

Definition at line 633 of file mips_cpuregs.h.

◆ MIPS_20Kc

#define MIPS_20Kc   0x82 /* MIPS 20Kc ISA 64 */

Definition at line 759 of file mips_cpuregs.h.

◆ MIPS_24K

#define MIPS_24K   0x93 /* MIPS 24K ? */

Definition at line 770 of file mips_cpuregs.h.

◆ MIPS_24KE

#define MIPS_24KE   0x96 /* MIPS 24KE ? */

Definition at line 772 of file mips_cpuregs.h.

◆ MIPS_25Kf

#define MIPS_25Kf   0x88 /* MIPS 25Kf ISA 64 */

Definition at line 765 of file mips_cpuregs.h.

◆ MIPS_34K

#define MIPS_34K   0x95 /* MIPS 34K ? */

Definition at line 771 of file mips_cpuregs.h.

◆ MIPS_4Kc

#define MIPS_4Kc   0x80 /* MIPS 4Kc ISA 32 */

Definition at line 757 of file mips_cpuregs.h.

◆ MIPS_4KEc

#define MIPS_4KEc   0x84 /* MIPS 4KEc ISA 32 */

Definition at line 761 of file mips_cpuregs.h.

◆ MIPS_4KEc_R2

#define MIPS_4KEc_R2   0x90 /* MIPS 4KEc_R2 ISA 32 Rel 2 */

Definition at line 767 of file mips_cpuregs.h.

◆ MIPS_4KEmp

#define MIPS_4KEmp   0x85 /* MIPS 4KEm/4KEp ISA 32 */

Definition at line 762 of file mips_cpuregs.h.

◆ MIPS_4KEmp_R2

#define MIPS_4KEmp_R2   0x91 /* MIPS 4KEm/4KEp_R2 ISA 32 Rel 2 */

Definition at line 768 of file mips_cpuregs.h.

◆ MIPS_4Kmp

#define MIPS_4Kmp   0x83 /* MIPS 4Km/4Kp ISA 32 */

Definition at line 760 of file mips_cpuregs.h.

◆ MIPS_4KSc

#define MIPS_4KSc   0x86 /* MIPS 4KSc ISA 32 */

Definition at line 763 of file mips_cpuregs.h.

◆ MIPS_4KSd

#define MIPS_4KSd   0x92 /* MIPS 4KSd ISA 32 Rel 2 */

Definition at line 769 of file mips_cpuregs.h.

◆ MIPS_5Kc

#define MIPS_5Kc   0x81 /* MIPS 5Kc ISA 64 */

Definition at line 758 of file mips_cpuregs.h.

◆ MIPS_5KE

#define MIPS_5KE   0x89 /* MIPS 5KE ISA 64 Rel 2 */

Definition at line 766 of file mips_cpuregs.h.

◆ MIPS_74K

#define MIPS_74K   0x97 /* MIPS 74K ? */

Definition at line 773 of file mips_cpuregs.h.

◆ MIPS_AU1000

#define MIPS_AU1000   0x00

Definition at line 783 of file mips_cpuregs.h.

◆ MIPS_AU1100

#define MIPS_AU1100   0x02

Definition at line 785 of file mips_cpuregs.h.

◆ MIPS_AU1500

#define MIPS_AU1500   0x01

Definition at line 784 of file mips_cpuregs.h.

◆ MIPS_AU1550

#define MIPS_AU1550   0x03

Definition at line 786 of file mips_cpuregs.h.

◆ MIPS_AU_REV1

#define MIPS_AU_REV1   0x01 /* Alchemy Au1000 (Rev 1) ISA 32 */

Definition at line 780 of file mips_cpuregs.h.

◆ MIPS_AU_REV2

#define MIPS_AU_REV2   0x02 /* Alchemy Au1000 (Rev 2) ISA 32 */

Definition at line 781 of file mips_cpuregs.h.

◆ MIPS_BIT

#define MIPS_BIT (   n)    n

Definition at line 472 of file mips_cpuregs.h.

◆ MIPS_BREAK_BRKPT

#define MIPS_BREAK_BRKPT
Value:

Definition at line 534 of file mips_cpuregs.h.

◆ MIPS_BREAK_BRKPT_VAL

#define MIPS_BREAK_BRKPT_VAL   514

Definition at line 528 of file mips_cpuregs.h.

◆ MIPS_BREAK_INSTR

#define MIPS_BREAK_INSTR   0x0000000d

Definition at line 523 of file mips_cpuregs.h.

◆ MIPS_BREAK_KDB

#define MIPS_BREAK_KDB
Value:

Definition at line 530 of file mips_cpuregs.h.

◆ MIPS_BREAK_KDB_VAL

#define MIPS_BREAK_KDB_VAL   512

Definition at line 526 of file mips_cpuregs.h.

◆ MIPS_BREAK_SOVER

#define MIPS_BREAK_SOVER
Value:

Definition at line 536 of file mips_cpuregs.h.

◆ MIPS_BREAK_SOVER_VAL

#define MIPS_BREAK_SOVER_VAL   515

Definition at line 529 of file mips_cpuregs.h.

◆ MIPS_BREAK_SSTEP

#define MIPS_BREAK_SSTEP
Value:

Definition at line 532 of file mips_cpuregs.h.

◆ MIPS_BREAK_SSTEP_VAL

#define MIPS_BREAK_SSTEP_VAL   513

Definition at line 527 of file mips_cpuregs.h.

◆ MIPS_BREAK_VAL_MASK

#define MIPS_BREAK_VAL_MASK   0x03ff0000

Definition at line 524 of file mips_cpuregs.h.

◆ MIPS_BREAK_VAL_SHIFT

#define MIPS_BREAK_VAL_SHIFT   16

Definition at line 525 of file mips_cpuregs.h.

◆ MIPS_COP_0_BAD_VADDR

#define MIPS_COP_0_BAD_VADDR   MIPS_BIT(8)

Definition at line 480 of file mips_cpuregs.h.

◆ MIPS_COP_0_CACHE_ERR

#define MIPS_COP_0_CACHE_ERR   MIPS_BIT(27)

Definition at line 507 of file mips_cpuregs.h.

◆ MIPS_COP_0_CAUSE

#define MIPS_COP_0_CAUSE   MIPS_BIT(13)

Definition at line 483 of file mips_cpuregs.h.

◆ MIPS_COP_0_COMPARE

#define MIPS_COP_0_COMPARE   MIPS_BIT(11)

Definition at line 499 of file mips_cpuregs.h.

◆ MIPS_COP_0_CONFIG

#define MIPS_COP_0_CONFIG   MIPS_BIT(16)

Definition at line 501 of file mips_cpuregs.h.

◆ MIPS_COP_0_COUNT

#define MIPS_COP_0_COUNT   MIPS_BIT(9)

Definition at line 498 of file mips_cpuregs.h.

◆ MIPS_COP_0_DATA_HI

#define MIPS_COP_0_DATA_HI   MIPS_BIT(29)

Definition at line 517 of file mips_cpuregs.h.

◆ MIPS_COP_0_DATA_LO

#define MIPS_COP_0_DATA_LO   MIPS_BIT(28)

Definition at line 516 of file mips_cpuregs.h.

◆ MIPS_COP_0_DEBUG

#define MIPS_COP_0_DEBUG   MIPS_BIT(23)

Definition at line 513 of file mips_cpuregs.h.

◆ MIPS_COP_0_DEPC

#define MIPS_COP_0_DEPC   MIPS_BIT(24)

Definition at line 514 of file mips_cpuregs.h.

◆ MIPS_COP_0_DESAVE

#define MIPS_COP_0_DESAVE   MIPS_BIT(31)

Definition at line 518 of file mips_cpuregs.h.

◆ MIPS_COP_0_ECC

#define MIPS_COP_0_ECC   MIPS_BIT(26)

Definition at line 506 of file mips_cpuregs.h.

◆ MIPS_COP_0_ERROR_PC

#define MIPS_COP_0_ERROR_PC   MIPS_BIT(30)

Definition at line 510 of file mips_cpuregs.h.

◆ MIPS_COP_0_EXC_PC

#define MIPS_COP_0_EXC_PC   MIPS_BIT(14)

Definition at line 484 of file mips_cpuregs.h.

◆ MIPS_COP_0_LLADDR

#define MIPS_COP_0_LLADDR   MIPS_BIT(17)

Definition at line 502 of file mips_cpuregs.h.

◆ MIPS_COP_0_PERFCNT

#define MIPS_COP_0_PERFCNT   MIPS_BIT(25)

Definition at line 515 of file mips_cpuregs.h.

◆ MIPS_COP_0_PRID

#define MIPS_COP_0_PRID   MIPS_BIT(15)

Definition at line 485 of file mips_cpuregs.h.

◆ MIPS_COP_0_STATUS

#define MIPS_COP_0_STATUS   MIPS_BIT(12)

Definition at line 482 of file mips_cpuregs.h.

◆ MIPS_COP_0_TAG_HI

#define MIPS_COP_0_TAG_HI   MIPS_BIT(29)

Definition at line 509 of file mips_cpuregs.h.

◆ MIPS_COP_0_TAG_LO

#define MIPS_COP_0_TAG_LO   MIPS_BIT(28)

Definition at line 508 of file mips_cpuregs.h.

◆ MIPS_COP_0_TLB_CONTEXT

#define MIPS_COP_0_TLB_CONTEXT   MIPS_BIT(4)

Definition at line 478 of file mips_cpuregs.h.

◆ MIPS_COP_0_TLB_HI

#define MIPS_COP_0_TLB_HI   MIPS_BIT(10)

Definition at line 481 of file mips_cpuregs.h.

◆ MIPS_COP_0_TLB_INDEX

#define MIPS_COP_0_TLB_INDEX   MIPS_BIT(0)

Definition at line 474 of file mips_cpuregs.h.

◆ MIPS_COP_0_TLB_LO0

#define MIPS_COP_0_TLB_LO0   MIPS_BIT(2)

Definition at line 492 of file mips_cpuregs.h.

◆ MIPS_COP_0_TLB_LO1

#define MIPS_COP_0_TLB_LO1   MIPS_BIT(3)

Definition at line 493 of file mips_cpuregs.h.

◆ MIPS_COP_0_TLB_LOW

#define MIPS_COP_0_TLB_LOW   MIPS_BIT(2)

Definition at line 489 of file mips_cpuregs.h.

◆ MIPS_COP_0_TLB_PG_MASK

#define MIPS_COP_0_TLB_PG_MASK   MIPS_BIT(5)

Definition at line 495 of file mips_cpuregs.h.

◆ MIPS_COP_0_TLB_RANDOM

#define MIPS_COP_0_TLB_RANDOM   MIPS_BIT(1)

Definition at line 475 of file mips_cpuregs.h.

◆ MIPS_COP_0_TLB_WIRED

#define MIPS_COP_0_TLB_WIRED   MIPS_BIT(6)

Definition at line 496 of file mips_cpuregs.h.

◆ MIPS_COP_0_TLB_XCONTEXT

#define MIPS_COP_0_TLB_XCONTEXT   MIPS_BIT(20)

Definition at line 505 of file mips_cpuregs.h.

◆ MIPS_COP_0_WATCH_HI

#define MIPS_COP_0_WATCH_HI   MIPS_BIT(19)

Definition at line 504 of file mips_cpuregs.h.

◆ MIPS_COP_0_WATCH_LO

#define MIPS_COP_0_WATCH_LO   MIPS_BIT(18)

Definition at line 503 of file mips_cpuregs.h.

◆ MIPS_CR_BR_DELAY

#define MIPS_CR_BR_DELAY   0x80000000

Definition at line 120 of file mips_cpuregs.h.

◆ MIPS_CR_COP_ERR

#define MIPS_CR_COP_ERR   0x30000000

Definition at line 121 of file mips_cpuregs.h.

◆ MIPS_CR_EXC_CODE_SHIFT

#define MIPS_CR_EXC_CODE_SHIFT   2

Definition at line 125 of file mips_cpuregs.h.

◆ MIPS_CR_IP

#define MIPS_CR_IP   0x0000FF00

Definition at line 124 of file mips_cpuregs.h.

◆ MIPS_FPU_COND_BIT

#define MIPS_FPU_COND_BIT   0x00800000

Definition at line 579 of file mips_cpuregs.h.

◆ MIPS_FPU_CSR

#define MIPS_FPU_CSR   $31

Definition at line 550 of file mips_cpuregs.h.

◆ MIPS_FPU_ENABLE_BITS

#define MIPS_FPU_ENABLE_BITS   0x00000f80

Definition at line 566 of file mips_cpuregs.h.

◆ MIPS_FPU_ENABLE_DIV0

#define MIPS_FPU_ENABLE_DIV0   0x00000400

Definition at line 570 of file mips_cpuregs.h.

◆ MIPS_FPU_ENABLE_INEXACT

#define MIPS_FPU_ENABLE_INEXACT   0x00000080

Definition at line 567 of file mips_cpuregs.h.

◆ MIPS_FPU_ENABLE_INVALID

#define MIPS_FPU_ENABLE_INVALID   0x00000800

Definition at line 571 of file mips_cpuregs.h.

◆ MIPS_FPU_ENABLE_OVERFLOW

#define MIPS_FPU_ENABLE_OVERFLOW   0x00000200

Definition at line 569 of file mips_cpuregs.h.

◆ MIPS_FPU_ENABLE_UNDERFLOW

#define MIPS_FPU_ENABLE_UNDERFLOW   0x00000100

Definition at line 568 of file mips_cpuregs.h.

◆ MIPS_FPU_EXCEPTION_BITS

#define MIPS_FPU_EXCEPTION_BITS   0x0003f000

Definition at line 572 of file mips_cpuregs.h.

◆ MIPS_FPU_EXCEPTION_DIV0

#define MIPS_FPU_EXCEPTION_DIV0   0x00008000

Definition at line 576 of file mips_cpuregs.h.

◆ MIPS_FPU_EXCEPTION_INEXACT

#define MIPS_FPU_EXCEPTION_INEXACT   0x00001000

Definition at line 573 of file mips_cpuregs.h.

◆ MIPS_FPU_EXCEPTION_INVALID

#define MIPS_FPU_EXCEPTION_INVALID   0x00010000

Definition at line 577 of file mips_cpuregs.h.

◆ MIPS_FPU_EXCEPTION_OVERFLOW

#define MIPS_FPU_EXCEPTION_OVERFLOW   0x00004000

Definition at line 575 of file mips_cpuregs.h.

◆ MIPS_FPU_EXCEPTION_UNDERFLOW

#define MIPS_FPU_EXCEPTION_UNDERFLOW   0x00002000

Definition at line 574 of file mips_cpuregs.h.

◆ MIPS_FPU_EXCEPTION_UNIMPL

#define MIPS_FPU_EXCEPTION_UNIMPL   0x00020000

Definition at line 578 of file mips_cpuregs.h.

◆ MIPS_FPU_FLUSH_BIT

#define MIPS_FPU_FLUSH_BIT   0x01000000 /* r4k, MBZ on r3k */

Definition at line 580 of file mips_cpuregs.h.

◆ MIPS_FPU_ID

#define MIPS_FPU_ID   $0

Definition at line 549 of file mips_cpuregs.h.

◆ MIPS_FPU_ROUND_RM

#define MIPS_FPU_ROUND_RM   0x00000003

Definition at line 559 of file mips_cpuregs.h.

◆ MIPS_FPU_ROUND_RN

#define MIPS_FPU_ROUND_RN   0x00000000

Definition at line 556 of file mips_cpuregs.h.

◆ MIPS_FPU_ROUND_RP

#define MIPS_FPU_ROUND_RP   0x00000002

Definition at line 558 of file mips_cpuregs.h.

◆ MIPS_FPU_ROUND_RZ

#define MIPS_FPU_ROUND_RZ   0x00000001

Definition at line 557 of file mips_cpuregs.h.

◆ MIPS_FPU_ROUNDING_BITS

#define MIPS_FPU_ROUNDING_BITS   0x00000003

Definition at line 555 of file mips_cpuregs.h.

◆ MIPS_FPU_STICKY_BITS

#define MIPS_FPU_STICKY_BITS   0x0000007c

Definition at line 560 of file mips_cpuregs.h.

◆ MIPS_FPU_STICKY_DIV0

#define MIPS_FPU_STICKY_DIV0   0x00000020

Definition at line 564 of file mips_cpuregs.h.

◆ MIPS_FPU_STICKY_INEXACT

#define MIPS_FPU_STICKY_INEXACT   0x00000004

Definition at line 561 of file mips_cpuregs.h.

◆ MIPS_FPU_STICKY_INVALID

#define MIPS_FPU_STICKY_INVALID   0x00000040

Definition at line 565 of file mips_cpuregs.h.

◆ MIPS_FPU_STICKY_OVERFLOW

#define MIPS_FPU_STICKY_OVERFLOW   0x00000010

Definition at line 563 of file mips_cpuregs.h.

◆ MIPS_FPU_STICKY_UNDERFLOW

#define MIPS_FPU_STICKY_UNDERFLOW   0x00000008

Definition at line 562 of file mips_cpuregs.h.

◆ MIPS_HARD_INT_MASK

#define MIPS_HARD_INT_MASK   0xfc00

Definition at line 261 of file mips_cpuregs.h.

◆ MIPS_INT_MASK

#define MIPS_INT_MASK   0xff00

Definition at line 254 of file mips_cpuregs.h.

◆ MIPS_INT_MASK_0

#define MIPS_INT_MASK_0   0x0400

Definition at line 260 of file mips_cpuregs.h.

◆ MIPS_INT_MASK_1

#define MIPS_INT_MASK_1   0x0800

Definition at line 259 of file mips_cpuregs.h.

◆ MIPS_INT_MASK_2

#define MIPS_INT_MASK_2   0x1000

Definition at line 258 of file mips_cpuregs.h.

◆ MIPS_INT_MASK_3

#define MIPS_INT_MASK_3   0x2000

Definition at line 257 of file mips_cpuregs.h.

◆ MIPS_INT_MASK_4

#define MIPS_INT_MASK_4   0x4000

Definition at line 256 of file mips_cpuregs.h.

◆ MIPS_INT_MASK_5

#define MIPS_INT_MASK_5   0x8000

Definition at line 255 of file mips_cpuregs.h.

◆ MIPS_KSEG0_START

#define MIPS_KSEG0_START   0x80000000

Definition at line 81 of file mips_cpuregs.h.

◆ MIPS_KSEG0_TO_PHYS

#define MIPS_KSEG0_TO_PHYS (   x)    ((unsigned)(x) & MIPS_PHYS_MASK)

Definition at line 89 of file mips_cpuregs.h.

◆ MIPS_KSEG1_START

#define MIPS_KSEG1_START   0xa0000000

Definition at line 82 of file mips_cpuregs.h.

◆ MIPS_KSEG1_TO_PHYS

#define MIPS_KSEG1_TO_PHYS (   x)    ((unsigned)(x) & MIPS_PHYS_MASK)

Definition at line 91 of file mips_cpuregs.h.

◆ MIPS_KSEG2_START

#define MIPS_KSEG2_START   0xc0000000

Definition at line 83 of file mips_cpuregs.h.

◆ MIPS_KUSEG_START

#define MIPS_KUSEG_START   0x0

Definition at line 80 of file mips_cpuregs.h.

◆ MIPS_M4K

#define MIPS_M4K   0x87 /* MIPS M4K ISA 32 Rel 2 */

Definition at line 764 of file mips_cpuregs.h.

◆ MIPS_MAX_CACHE_SIZE

#define MIPS_MAX_CACHE_SIZE   (256 * 1024)

Definition at line 543 of file mips_cpuregs.h.

◆ MIPS_MAX_MEM_ADDR

#define MIPS_MAX_MEM_ADDR   0xbe000000

Definition at line 84 of file mips_cpuregs.h.

◆ MIPS_MIN_CACHE_SIZE

#define MIPS_MIN_CACHE_SIZE   (16 * 1024)

Definition at line 542 of file mips_cpuregs.h.

◆ MIPS_OPCODE_C1

#define MIPS_OPCODE_C1   0x11

Definition at line 589 of file mips_cpuregs.h.

◆ MIPS_OPCODE_SHIFT

#define MIPS_OPCODE_SHIFT   26

Definition at line 588 of file mips_cpuregs.h.

◆ MIPS_PHYS_MASK

#define MIPS_PHYS_MASK   0x1fffffff

Definition at line 87 of file mips_cpuregs.h.

◆ MIPS_PHYS_TO_KSEG0

#define MIPS_PHYS_TO_KSEG0 (   x)    ((unsigned)(x) | MIPS_KSEG0_START)

Definition at line 90 of file mips_cpuregs.h.

◆ MIPS_PHYS_TO_KSEG1

#define MIPS_PHYS_TO_KSEG1 (   x)    ((unsigned)(x) | MIPS_KSEG1_START)

Definition at line 92 of file mips_cpuregs.h.

◆ MIPS_PHYS_TO_XKPHYS

#define MIPS_PHYS_TO_XKPHYS (   cca,
 
)    ((0x2ULL << 62) | ((unsigned long long)(cca) << 59) | (x))

Definition at line 98 of file mips_cpuregs.h.

◆ MIPS_R10000

#define MIPS_R10000   0x09 /* MIPS R10000 ISA IV */

Definition at line 705 of file mips_cpuregs.h.

◆ MIPS_R12000

#define MIPS_R12000   0x0e /* MIPS R12000 ISA IV */

Definition at line 709 of file mips_cpuregs.h.

◆ MIPS_R14000

#define MIPS_R14000   0x0f /* MIPS R14000 ISA IV */

Definition at line 710 of file mips_cpuregs.h.

◆ MIPS_R2000

#define MIPS_R2000   0x01 /* MIPS R2000 ISA I */

Definition at line 698 of file mips_cpuregs.h.

◆ MIPS_R2010

#define MIPS_R2010   0x02 /* MIPS R2010 FPC ISA I */

Definition at line 803 of file mips_cpuregs.h.

◆ MIPS_R2360

#define MIPS_R2360   0x01 /* MIPS R2360 FPC ISA I */

Definition at line 802 of file mips_cpuregs.h.

◆ MIPS_R3000

#define MIPS_R3000   0x02 /* MIPS R3000 ISA I */

Definition at line 699 of file mips_cpuregs.h.

◆ MIPS_R3010

#define MIPS_R3010   0x03 /* MIPS R3010 FPC ISA I */

Definition at line 804 of file mips_cpuregs.h.

◆ MIPS_R31LSI

#define MIPS_R31LSI   0x06 /* LSI Logic derivate ISA I */

Definition at line 807 of file mips_cpuregs.h.

◆ MIPS_R3IDT

#define MIPS_R3IDT   0x07 /* IDT R3041 or RC36100 ISA I */

Definition at line 704 of file mips_cpuregs.h.

◆ MIPS_R3LSI

#define MIPS_R3LSI   0x05 /* LSI Logic R3000 derivative ISA I */

Definition at line 702 of file mips_cpuregs.h.

◆ MIPS_R3NKK

#define MIPS_R3NKK   0x23 /* NKK R3000 based ISA I */

Definition at line 719 of file mips_cpuregs.h.

◆ MIPS_R3SONY

#define MIPS_R3SONY   0x21 /* Sony R3000 based ISA I */

Definition at line 715 of file mips_cpuregs.h.

◆ MIPS_R3TOSH

#define MIPS_R3TOSH   0x22 /* Toshiba R3000 based FPU ISA I */

Definition at line 808 of file mips_cpuregs.h.

◆ MIPS_R4000

#define MIPS_R4000   0x04 /* MIPS R4000/R4400 ISA III */

Definition at line 701 of file mips_cpuregs.h.

◆ MIPS_R4010

#define MIPS_R4010   0x05 /* MIPS R4010 FPC ISA II */

Definition at line 806 of file mips_cpuregs.h.

◆ MIPS_R4100

#define MIPS_R4100   0x0c /* NEC VR4100 ISA III */

Definition at line 708 of file mips_cpuregs.h.

◆ MIPS_R4200

#define MIPS_R4200   0x0a /* NEC VR4200 ISA III */

Definition at line 706 of file mips_cpuregs.h.

◆ MIPS_R4300

#define MIPS_R4300   0x0b /* NEC VR4300 ISA III */

Definition at line 707 of file mips_cpuregs.h.

◆ MIPS_R4600

#define MIPS_R4600   0x20 /* QED R4600 Orion ISA III */

Definition at line 713 of file mips_cpuregs.h.

◆ MIPS_R4650

#define MIPS_R4650   0x22 /* QED R4650 ISA III */

Definition at line 716 of file mips_cpuregs.h.

◆ MIPS_R4700

#define MIPS_R4700   0x21 /* QED R4700 Orion ISA III */

Definition at line 714 of file mips_cpuregs.h.

◆ MIPS_R5000

#define MIPS_R5000   0x23 /* MIPS R5000 ISA IV */

Definition at line 718 of file mips_cpuregs.h.

◆ MIPS_R5400

#define MIPS_R5400   0x54 /* NEC VR5400 ISA IV */

Definition at line 727 of file mips_cpuregs.h.

◆ MIPS_R5500

#define MIPS_R5500   0x55 /* NEC VR5500 ISA IV */

Definition at line 728 of file mips_cpuregs.h.

◆ MIPS_R5900

#define MIPS_R5900   0x2e /* Toshiba R5900 (EECore) ISA --- */

Definition at line 724 of file mips_cpuregs.h.

◆ MIPS_R5900_COUNTER_EXC_VEC

#define MIPS_R5900_COUNTER_EXC_VEC   0x80000080

Definition at line 416 of file mips_cpuregs.h.

◆ MIPS_R5900_DEBUG_EXC_VEC

#define MIPS_R5900_DEBUG_EXC_VEC   0x80000100

Definition at line 417 of file mips_cpuregs.h.

◆ MIPS_R6000

#define MIPS_R6000   0x03 /* MIPS R6000 ISA II */

Definition at line 700 of file mips_cpuregs.h.

◆ MIPS_R6000A

#define MIPS_R6000A   0x06 /* MIPS R6000A ISA II */

Definition at line 703 of file mips_cpuregs.h.

◆ MIPS_R6010

#define MIPS_R6010   0x04 /* MIPS R6010 FPC ISA II */

Definition at line 805 of file mips_cpuregs.h.

◆ MIPS_R8000

#define MIPS_R8000   0x10 /* MIPS R8000 Blackbird/TFP ISA IV */

Definition at line 711 of file mips_cpuregs.h.

◆ MIPS_RC32300

#define MIPS_RC32300   0x18 /* IDT RC32334,332,355 ISA 32 */

Definition at line 712 of file mips_cpuregs.h.

◆ MIPS_RC32364

#define MIPS_RC32364   0x26 /* IDT RC32364 ISA 32 */

Definition at line 720 of file mips_cpuregs.h.

◆ MIPS_RC64470

#define MIPS_RC64470   0x30 /* IDT RC64474/RC64475 ISA III */

Definition at line 725 of file mips_cpuregs.h.

◆ MIPS_RESERVED_ADDR

#define MIPS_RESERVED_ADDR   0xbfc80000

Definition at line 85 of file mips_cpuregs.h.

◆ MIPS_RESET_EXC_VEC

#define MIPS_RESET_EXC_VEC   0xBFC00000

Definition at line 398 of file mips_cpuregs.h.

◆ MIPS_REV_R3000

#define MIPS_REV_R3000   0x20

Definition at line 735 of file mips_cpuregs.h.

◆ MIPS_REV_R3000A

#define MIPS_REV_R3000A   0x30

Definition at line 736 of file mips_cpuregs.h.

◆ MIPS_REV_R4000_A

#define MIPS_REV_R4000_A   0x00

Definition at line 744 of file mips_cpuregs.h.

◆ MIPS_REV_R4000_B

#define MIPS_REV_R4000_B   0x22

Definition at line 745 of file mips_cpuregs.h.

◆ MIPS_REV_R4000_C

#define MIPS_REV_R4000_C   0x30

Definition at line 746 of file mips_cpuregs.h.

◆ MIPS_REV_R4400_A

#define MIPS_REV_R4400_A   0x40

Definition at line 747 of file mips_cpuregs.h.

◆ MIPS_REV_R4400_B

#define MIPS_REV_R4400_B   0x50

Definition at line 748 of file mips_cpuregs.h.

◆ MIPS_REV_R4400_C

#define MIPS_REV_R4400_C   0x60

Definition at line 749 of file mips_cpuregs.h.

◆ MIPS_REV_TX3912

#define MIPS_REV_TX3912   0x10

Definition at line 739 of file mips_cpuregs.h.

◆ MIPS_REV_TX3922

#define MIPS_REV_TX3922   0x30

Definition at line 740 of file mips_cpuregs.h.

◆ MIPS_REV_TX3927

#define MIPS_REV_TX3927   0x40

Definition at line 741 of file mips_cpuregs.h.

◆ MIPS_REV_TX4927

#define MIPS_REV_TX4927   0x22

Definition at line 752 of file mips_cpuregs.h.

◆ MIPS_RM5200

#define MIPS_RM5200   0x28 /* QED RM5200s ISA IV */

Definition at line 722 of file mips_cpuregs.h.

◆ MIPS_RM7000

#define MIPS_RM7000   0x27 /* QED RM7000 ISA IV */

Definition at line 721 of file mips_cpuregs.h.

◆ MIPS_SB1

#define MIPS_SB1   0x01 /* SiByte SB1 ISA 64 */

Definition at line 791 of file mips_cpuregs.h.

◆ MIPS_SOFT

#define MIPS_SOFT   0x00 /* Software emulation ISA I */

Definition at line 801 of file mips_cpuregs.h.

◆ MIPS_SOFT_INT_MASK_0

#define MIPS_SOFT_INT_MASK_0   0x0100

Definition at line 263 of file mips_cpuregs.h.

◆ MIPS_SOFT_INT_MASK_1

#define MIPS_SOFT_INT_MASK_1   0x0200

Definition at line 262 of file mips_cpuregs.h.

◆ MIPS_SR7100

#define MIPS_SR7100   0x04 /* SandCraft SR7100 ISA 64 */

Definition at line 796 of file mips_cpuregs.h.

◆ MIPS_SR_BEV

#define MIPS_SR_BEV   0x00400000 /* Use boot exception vector */

Definition at line 150 of file mips_cpuregs.h.

◆ MIPS_SR_CACHE_MISS

#define MIPS_SR_CACHE_MISS   MIPS1_CACHE_MISS

Definition at line 191 of file mips_cpuregs.h.

◆ MIPS_SR_COP_0_BIT

#define MIPS_SR_COP_0_BIT   0x10000000

Definition at line 143 of file mips_cpuregs.h.

◆ MIPS_SR_COP_1_BIT

#define MIPS_SR_COP_1_BIT   0x20000000

Definition at line 144 of file mips_cpuregs.h.

◆ MIPS_SR_COP_USABILITY

#define MIPS_SR_COP_USABILITY   0xf0000000

Definition at line 142 of file mips_cpuregs.h.

◆ MIPS_SR_DIAG_CE

#define MIPS_SR_DIAG_CE   MIPS3_SR_DIAG_CE

Definition at line 236 of file mips_cpuregs.h.

◆ MIPS_SR_DIAG_CH

#define MIPS_SR_DIAG_CH   MIPS3_SR_DIAG_CH

Definition at line 235 of file mips_cpuregs.h.

◆ MIPS_SR_DIAG_PE

#define MIPS_SR_DIAG_PE   MIPS3_SR_DIAG_PE

Definition at line 237 of file mips_cpuregs.h.

◆ MIPS_SR_ERL

#define MIPS_SR_ERL   MIPS3_SR_ERL

Definition at line 246 of file mips_cpuregs.h.

◆ MIPS_SR_EXL

#define MIPS_SR_EXL   MIPS3_SR_EXL

Definition at line 247 of file mips_cpuregs.h.

◆ MIPS_SR_INT_ENA_OLD

#define MIPS_SR_INT_ENA_OLD   MIPS1_SR_INT_ENA_OLD

Definition at line 197 of file mips_cpuregs.h.

◆ MIPS_SR_INT_ENA_PREV

#define MIPS_SR_INT_ENA_PREV   MIPS1_SR_INT_ENA_PREV

Definition at line 200 of file mips_cpuregs.h.

◆ MIPS_SR_INT_IE

#define MIPS_SR_INT_IE   0x00000001

Definition at line 155 of file mips_cpuregs.h.

◆ MIPS_SR_ISOL_CACHES

#define MIPS_SR_ISOL_CACHES   MIPS1_ISOL_CACHES

Definition at line 194 of file mips_cpuregs.h.

◆ MIPS_SR_KSU_KERNEL

#define MIPS_SR_KSU_KERNEL   MIPS3_SR_KSU_KERNEL

Definition at line 245 of file mips_cpuregs.h.

◆ MIPS_SR_KSU_MASK

#define MIPS_SR_KSU_MASK   MIPS3_SR_KSU_MASK

Definition at line 242 of file mips_cpuregs.h.

◆ MIPS_SR_KSU_SUPER

#define MIPS_SR_KSU_SUPER   MIPS3_SR_KSU_SUPER

Definition at line 244 of file mips_cpuregs.h.

◆ MIPS_SR_KSU_USER

#define MIPS_SR_KSU_USER   MIPS3_SR_KSU_USER

Definition at line 243 of file mips_cpuregs.h.

◆ MIPS_SR_KU_CUR

#define MIPS_SR_KU_CUR   MIPS1_SR_KU_CUR

Definition at line 199 of file mips_cpuregs.h.

◆ MIPS_SR_KU_OLD

#define MIPS_SR_KU_OLD   MIPS1_SR_KU_OLD

Definition at line 196 of file mips_cpuregs.h.

◆ MIPS_SR_KU_PREV

#define MIPS_SR_KU_PREV   MIPS1_SR_KU_PREV

Definition at line 198 of file mips_cpuregs.h.

◆ MIPS_SR_KX

#define MIPS_SR_KX   MIPS3_SR_KX

Definition at line 238 of file mips_cpuregs.h.

◆ MIPS_SR_MX

#define MIPS_SR_MX   0x01000000 /* MIPS64 */

Definition at line 148 of file mips_cpuregs.h.

◆ MIPS_SR_PARITY_ERR

#define MIPS_SR_PARITY_ERR   MIPS1_PARITY_ERR

Definition at line 190 of file mips_cpuregs.h.

◆ MIPS_SR_PARITY_ZERO

#define MIPS_SR_PARITY_ZERO   MIPS1_PARITY_ZERO

Definition at line 192 of file mips_cpuregs.h.

◆ MIPS_SR_PX

#define MIPS_SR_PX   0x00800000 /* MIPS64 */

Definition at line 149 of file mips_cpuregs.h.

◆ MIPS_SR_SOFT_RESET

#define MIPS_SR_SOFT_RESET   MIPS3_SR_SOFT_RESET

Definition at line 234 of file mips_cpuregs.h.

◆ MIPS_SR_SWAP_CACHES

#define MIPS_SR_SWAP_CACHES   MIPS1_SWAP_CACHES

Definition at line 193 of file mips_cpuregs.h.

◆ MIPS_SR_SX

#define MIPS_SR_SX   MIPS3_SR_SX

Definition at line 239 of file mips_cpuregs.h.

◆ MIPS_SR_TS

#define MIPS_SR_TS   0x00200000

Definition at line 151 of file mips_cpuregs.h.

◆ MIPS_SR_UX

#define MIPS_SR_UX   MIPS3_SR_UX

Definition at line 240 of file mips_cpuregs.h.

◆ MIPS_TLB_NUM_PIDS

#define MIPS_TLB_NUM_PIDS   ((MIPS_HAS_R4K_MMU) ? MIPS3_TLB_NUM_ASIDS : MIPS1_TLB_NUM_PIDS)

Definition at line 691 of file mips_cpuregs.h.

◆ MIPS_TLB_PID_SHIFT

#define MIPS_TLB_PID_SHIFT   ((MIPS_HAS_R4K_MMU) ? 0 : MIPS1_TLB_PID_SHIFT)

Definition at line 688 of file mips_cpuregs.h.

◆ MIPS_TLB_VIRT_PAGE_SHIFT

#define MIPS_TLB_VIRT_PAGE_SHIFT   12

Definition at line 649 of file mips_cpuregs.h.

◆ MIPS_TX3900

#define MIPS_TX3900   0x22 /* Toshiba TX39 family ISA I */

Definition at line 717 of file mips_cpuregs.h.

◆ MIPS_TX4900

#define MIPS_TX4900   0x2d /* Toshiba TX49 family ISA III */

Definition at line 723 of file mips_cpuregs.h.

◆ MIPS_TX7900

#define MIPS_TX7900   0x38 /* Toshiba TX79 ISA III+*/

Definition at line 726 of file mips_cpuregs.h.

◆ MIPS_UTLB_MISS_EXC_VEC

#define MIPS_UTLB_MISS_EXC_VEC   0x80000000

Definition at line 399 of file mips_cpuregs.h.

◆ MIPS_XKPHYS_TO_PHYS

#define MIPS_XKPHYS_TO_PHYS (   x)    ((x) & 0x0effffffffffffffULL)

Definition at line 100 of file mips_cpuregs.h.

MIPS_BREAK_BRKPT_VAL
#define MIPS_BREAK_BRKPT_VAL
Definition: mips_cpuregs.h:527
MIPS_BREAK_INSTR
#define MIPS_BREAK_INSTR
Definition: mips_cpuregs.h:522
MIPS_BREAK_KDB_VAL
#define MIPS_BREAK_KDB_VAL
Definition: mips_cpuregs.h:525
MIPS_BREAK_SSTEP_VAL
#define MIPS_BREAK_SSTEP_VAL
Definition: mips_cpuregs.h:526
MIPS_BREAK_VAL_SHIFT
#define MIPS_BREAK_VAL_SHIFT
Definition: mips_cpuregs.h:524
MIPS_BREAK_SOVER_VAL
#define MIPS_BREAK_SOVER_VAL
Definition: mips_cpuregs.h:528

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