rtl81x9reg.h File Reference

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rtl81x9reg.h File Reference

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Classes

struct  rl_desc
 
struct  rl_stats
 
struct  rl_type
 
struct  rl_mii_frame
 

Macros

#define RL_IDR0   0x0000 /* ID register 0 (station addr) */
 
#define RL_IDR1   0x0001 /* Must use 32-bit accesses (?) */
 
#define RL_IDR2   0x0002
 
#define RL_IDR3   0x0003
 
#define RL_IDR4   0x0004
 
#define RL_IDR5   0x0005
 
#define RL_MAR0   0x0008 /* Multicast hash table */
 
#define RL_MAR1   0x0009
 
#define RL_MAR2   0x000A
 
#define RL_MAR3   0x000B
 
#define RL_MAR4   0x000C
 
#define RL_MAR5   0x000D
 
#define RL_MAR6   0x000E
 
#define RL_MAR7   0x000F
 
#define RL_TXSTAT0   0x0010 /* status of TX descriptor 0 */
 
#define RL_TXSTAT1   0x0014 /* status of TX descriptor 1 */
 
#define RL_TXSTAT2   0x0018 /* status of TX descriptor 2 */
 
#define RL_TXSTAT3   0x001C /* status of TX descriptor 3 */
 
#define RL_TXADDR0   0x0020 /* address of TX descriptor 0 */
 
#define RL_TXADDR1   0x0024 /* address of TX descriptor 1 */
 
#define RL_TXADDR2   0x0028 /* address of TX descriptor 2 */
 
#define RL_TXADDR3   0x002C /* address of TX descriptor 3 */
 
#define RL_RXADDR   0x0030 /* RX ring start address */
 
#define RL_RX_EARLY_BYTES   0x0034 /* RX early byte count */
 
#define RL_RX_EARLY_STAT   0x0036 /* RX early status */
 
#define RL_COMMAND   0x0037 /* command register */
 
#define RL_CURRXADDR   0x0038 /* current address of packet read */
 
#define RL_CURRXBUF   0x003A /* current RX buffer address */
 
#define RL_IMR   0x003C /* interrupt mask register */
 
#define RL_ISR   0x003E /* interrupt status register */
 
#define RL_TXCFG   0x0040 /* transmit config */
 
#define RL_RXCFG   0x0044 /* receive config */
 
#define RL_TIMERCNT   0x0048 /* timer count register */
 
#define RL_MISSEDPKT   0x004C /* missed packet counter */
 
#define RL_EECMD   0x0050 /* EEPROM command register */
 
#define RL_CFG0   0x0051 /* config register #0 */
 
#define RL_CFG1   0x0052 /* config register #1 */
 
#define RL_MEDIASTAT   0x0058 /* media status register (8139) */
 
#define RL_MII   0x005A /* 8129 chip only */
 
#define RL_HALTCLK   0x005B
 
#define RL_MULTIINTR   0x005C /* multiple interrupt */
 
#define RL_PCIREV   0x005E /* PCI revision value */
 
#define RL_TXSTAT_ALL   0x0060 /* TX status of all descriptors */
 
#define RL_BMCR   0x0062 /* PHY basic mode control */
 
#define RL_BMSR   0x0064 /* PHY basic mode status */
 
#define RL_ANAR   0x0066 /* PHY autoneg advert */
 
#define RL_LPAR   0x0068 /* PHY link partner ability */
 
#define RL_ANER   0x006A /* PHY autoneg expansion */
 
#define RL_DISCCNT   0x006C /* disconnect counter */
 
#define RL_FALSECAR   0x006E /* false carrier counter */
 
#define RL_NWAYTST   0x0070 /* NWAY test register */
 
#define RL_RX_ER   0x0072 /* RX_ER counter */
 
#define RL_CSCFG   0x0074 /* CS configuration register */
 
#define RL_DUMPSTATS_LO   0x0010 /* counter dump command register */
 
#define RL_DUMPSTATS_HI   0x0014 /* counter dump command register */
 
#define RL_TXLIST_ADDR_LO   0x0020 /* 64 bits, 256 byte alignment */
 
#define RL_TXLIST_ADDR_HI   0x0024 /* 64 bits, 256 byte alignment */
 
#define RL_TXLIST_ADDR_HPRIO_LO   0x0028 /* 64 bits, 256 byte aligned */
 
#define RL_TXLIST_ADDR_HPRIO_HI   0x002C /* 64 bits, 256 byte aligned */
 
#define RL_CFG2   0x0053
 
#define RL_TIMERINT   0x0054 /* interrupt on timer expire */
 
#define RL_TXSTART   0x00D9 /* 8 bits */
 
#define RL_CPLUS_CMD   0x00E0 /* 16 bits */
 
#define RL_RXLIST_ADDR_LO   0x00E4 /* 64 bits, 256 byte alignment */
 
#define RL_RXLIST_ADDR_HI   0x00E8 /* 64 bits, 256 byte alignment */
 
#define RL_EARLY_TX_THRESH   0x00EC /* 8 bits */
 
#define RL_TIMERINT_8169   0x0058 /* different offset than 8139 */
 
#define RL_PHYAR   0x0060
 
#define RL_TBICSR   0x0064
 
#define RL_TBI_ANAR   0x0068
 
#define RL_TBI_LPAR   0x006A
 
#define RL_GMEDIASTAT   0x006C /* 8 bits */
 
#define RL_MAXRXPKTLEN   0x00DA /* 16 bits, chip multiplies by 8 */
 
#define RL_GTXSTART   0x0038 /* 16 bits */
 
#define RL_TXCFG_CLRABRT   0x00000001 /* retransmit aborted pkt */
 
#define RL_TXCFG_MAXDMA   0x00000700 /* max DMA burst size */
 
#define RL_TXCFG_CRCAPPEND   0x00010000 /* CRC append (0 = yes) */
 
#define RL_TXCFG_LOOPBKTST   0x00060000 /* loopback test */
 
#define RL_TXCFG_IFG2   0x00080000 /* 8169 only */
 
#define RL_TXCFG_IFG   0x03000000 /* interframe gap */
 
#define RL_TXCFG_HWREV   0x7C800000
 
#define RL_LOOPTEST_OFF   0x00000000
 
#define RL_LOOPTEST_ON   0x00020000
 
#define RL_LOOPTEST_ON_CPLUS   0x00060000
 
#define RL_HWREV_8169   0x00000000
 
#define RL_HWREV_8110S   0x00800000
 
#define RL_HWREV_8169S   0x04000000
 
#define RL_HWREV_8169_8110SB   0x10000000
 
#define RL_HWREV_8169_8110SC   0x18000000
 
#define RL_HWREV_8168_SPIN1   0x30000000
 
#define RL_HWREV_8100E_SPIN1   0x30800000
 
#define RL_HWREV_8101E   0x34000000
 
#define RL_HWREV_8168_SPIN2   0x38000000
 
#define RL_HWREV_8100E_SPIN2   0x38800000
 
#define RL_HWREV_8139   0x60000000
 
#define RL_HWREV_8139A   0x70000000
 
#define RL_HWREV_8139AG   0x70800000
 
#define RL_HWREV_8139B   0x78000000
 
#define RL_HWREV_8130   0x7C000000
 
#define RL_HWREV_8139C   0x74000000
 
#define RL_HWREV_8139D   0x74400000
 
#define RL_HWREV_8139CPLUS   0x74800000
 
#define RL_HWREV_8101   0x74c00000
 
#define RL_HWREV_8100   0x78800000
 
#define RL_TXDMA_16BYTES   0x00000000
 
#define RL_TXDMA_32BYTES   0x00000100
 
#define RL_TXDMA_64BYTES   0x00000200
 
#define RL_TXDMA_128BYTES   0x00000300
 
#define RL_TXDMA_256BYTES   0x00000400
 
#define RL_TXDMA_512BYTES   0x00000500
 
#define RL_TXDMA_1024BYTES   0x00000600
 
#define RL_TXDMA_2048BYTES   0x00000700
 
#define RL_TXSTAT_LENMASK   0x00001FFF
 
#define RL_TXSTAT_OWN   0x00002000
 
#define RL_TXSTAT_TX_UNDERRUN   0x00004000
 
#define RL_TXSTAT_TX_OK   0x00008000
 
#define RL_TXSTAT_EARLY_THRESH   0x003F0000
 
#define RL_TXSTAT_COLLCNT   0x0F000000
 
#define RL_TXSTAT_CARR_HBEAT   0x10000000
 
#define RL_TXSTAT_OUTOFWIN   0x20000000
 
#define RL_TXSTAT_TXABRT   0x40000000
 
#define RL_TXSTAT_CARRLOSS   0x80000000
 
#define RL_ISR_RX_OK   0x0001
 
#define RL_ISR_RX_ERR   0x0002
 
#define RL_ISR_TX_OK   0x0004
 
#define RL_ISR_TX_ERR   0x0008
 
#define RL_ISR_RX_OVERRUN   0x0010
 
#define RL_ISR_PKT_UNDERRUN   0x0020
 
#define RL_ISR_LINKCHG   0x0020 /* 8169 only */
 
#define RL_ISR_FIFO_OFLOW   0x0040 /* 8139 only */
 
#define RL_ISR_TX_DESC_UNAVAIL   0x0080 /* C+ only */
 
#define RL_ISR_SWI   0x0100 /* C+ only */
 
#define RL_ISR_CABLE_LEN_CHGD   0x2000
 
#define RL_ISR_PCS_TIMEOUT   0x4000 /* 8129 only */
 
#define RL_ISR_TIMEOUT_EXPIRED   0x4000
 
#define RL_ISR_SYSTEM_ERR   0x8000
 
#define RL_INTRS
 
#define RL_INTRS_CPLUS
 
#define RL_MEDIASTAT_RXPAUSE   0x01
 
#define RL_MEDIASTAT_TXPAUSE   0x02
 
#define RL_MEDIASTAT_LINK   0x04
 
#define RL_MEDIASTAT_SPEED10   0x08
 
#define RL_MEDIASTAT_RXFLOWCTL   0x40 /* duplex mode */
 
#define RL_MEDIASTAT_TXFLOWCTL   0x80 /* duplex mode */
 
#define RL_RXCFG_RX_ALLPHYS   0x00000001 /* accept all nodes */
 
#define RL_RXCFG_RX_INDIV   0x00000002 /* match filter */
 
#define RL_RXCFG_RX_MULTI   0x00000004 /* accept all multicast */
 
#define RL_RXCFG_RX_BROAD   0x00000008 /* accept all broadcast */
 
#define RL_RXCFG_RX_RUNT   0x00000010
 
#define RL_RXCFG_RX_ERRPKT   0x00000020
 
#define RL_RXCFG_WRAP   0x00000080
 
#define RL_RXCFG_MAXDMA   0x00000700
 
#define RL_RXCFG_BURSZ   0x00001800
 
#define RL_RXCFG_FIFOTHRESH   0x0000E000
 
#define RL_RXCFG_EARLYTHRESH   0x07000000
 
#define RL_RXDMA_16BYTES   0x00000000
 
#define RL_RXDMA_32BYTES   0x00000100
 
#define RL_RXDMA_64BYTES   0x00000200
 
#define RL_RXDMA_128BYTES   0x00000300
 
#define RL_RXDMA_256BYTES   0x00000400
 
#define RL_RXDMA_512BYTES   0x00000500
 
#define RL_RXDMA_1024BYTES   0x00000600
 
#define RL_RXDMA_UNLIMITED   0x00000700
 
#define RL_RXBUF_8   0x00000000
 
#define RL_RXBUF_16   0x00000800
 
#define RL_RXBUF_32   0x00001000
 
#define RL_RXBUF_64   0x00001800
 
#define RL_RXFIFO_16BYTES   0x00000000
 
#define RL_RXFIFO_32BYTES   0x00002000
 
#define RL_RXFIFO_64BYTES   0x00004000
 
#define RL_RXFIFO_128BYTES   0x00006000
 
#define RL_RXFIFO_256BYTES   0x00008000
 
#define RL_RXFIFO_512BYTES   0x0000A000
 
#define RL_RXFIFO_1024BYTES   0x0000C000
 
#define RL_RXFIFO_NOTHRESH   0x0000E000
 
#define RL_RXSTAT_RXOK   0x00000001
 
#define RL_RXSTAT_ALIGNERR   0x00000002
 
#define RL_RXSTAT_CRCERR   0x00000004
 
#define RL_RXSTAT_GIANT   0x00000008
 
#define RL_RXSTAT_RUNT   0x00000010
 
#define RL_RXSTAT_BADSYM   0x00000020
 
#define RL_RXSTAT_BROAD   0x00002000
 
#define RL_RXSTAT_INDIV   0x00004000
 
#define RL_RXSTAT_MULTI   0x00008000
 
#define RL_RXSTAT_LENMASK   0xFFFF0000
 
#define RL_RXSTAT_UNFINISHED   0xFFF0 /* DMA still in progress */
 
#define RL_CMD_EMPTY_RXBUF   0x0001
 
#define RL_CMD_TX_ENB   0x0004
 
#define RL_CMD_RX_ENB   0x0008
 
#define RL_CMD_RESET   0x0010
 
#define RL_EE_DATAOUT   0x01 /* Data out */
 
#define RL_EE_DATAIN   0x02 /* Data in */
 
#define RL_EE_CLK   0x04 /* clock */
 
#define RL_EE_SEL   0x08 /* chip select */
 
#define RL_EE_MODE   (0x40|0x80)
 
#define RL_EEMODE_OFF   0x00
 
#define RL_EEMODE_AUTOLOAD   0x40
 
#define RL_EEMODE_PROGRAM   0x80
 
#define RL_EEMODE_WRITECFG   (0x80|0x40)
 
#define RL_9346_WRITE   0x5
 
#define RL_9346_READ   0x6
 
#define RL_9346_ERASE   0x7
 
#define RL_9346_EWEN   0x4
 
#define RL_9346_EWEN_ADDR   0x30
 
#define RL_9456_EWDS   0x4
 
#define RL_9346_EWDS_ADDR   0x00
 
#define RL_EECMD_WRITE   0x5 /* 0101b */
 
#define RL_EECMD_READ   0x6 /* 0110b */
 
#define RL_EECMD_ERASE   0x7 /* 0111b */
 
#define RL_EECMD_LEN   4
 
#define RL_EEADDR_LEN0   6 /* 9346 */
 
#define RL_EEADDR_LEN1   8 /* 9356 */
 
#define RL_EECMD_READ_6BIT   0x180 /* XXX */
 
#define RL_EECMD_READ_8BIT   0x600 /* EECMD_READ above maybe wrong? */
 
#define RL_EE_ID   0x00
 
#define RL_EE_PCI_VID   0x01
 
#define RL_EE_PCI_DID   0x02
 
#define RL_EE_EADDR   0x07
 
#define RL_MII_CLK   0x01
 
#define RL_MII_DATAIN   0x02
 
#define RL_MII_DATAOUT   0x04
 
#define RL_MII_DIR   0x80 /* 0 == input, 1 == output */
 
#define RL_CFG0_ROM0   0x01
 
#define RL_CFG0_ROM1   0x02
 
#define RL_CFG0_ROM2   0x04
 
#define RL_CFG0_PL0   0x08
 
#define RL_CFG0_PL1   0x10
 
#define RL_CFG0_10MBPS   0x20 /* 10 Mbps internal mode */
 
#define RL_CFG0_PCS   0x40
 
#define RL_CFG0_SCR   0x80
 
#define RL_CFG1_PWRDWN   0x01
 
#define RL_CFG1_SLEEP   0x02
 
#define RL_CFG1_IOMAP   0x04
 
#define RL_CFG1_MEMMAP   0x08
 
#define RL_CFG1_RSVD   0x10
 
#define RL_CFG1_DRVLOAD   0x20
 
#define RL_CFG1_LED0   0x40
 
#define RL_CFG1_FULLDUPLEX   0x40 /* 8129 only */
 
#define RL_CFG1_LED1   0x80
 
#define RL_DUMPSTATS_START   0x00000008
 
#define RL_TXSTART_SWI   0x01 /* generate TX interrupt */
 
#define RL_TXSTART_START   0x40 /* start normal queue transmit */
 
#define RL_TXSTART_HPRIO_START   0x80 /* start hi prio queue transmit */
 
#define RL_CFG2_BUSFREQ   0x07
 
#define RL_CFG2_BUSWIDTH   0x08
 
#define RL_CFG2_AUXPWRSTS   0x10
 
#define RL_BUSFREQ_33MHZ   0x00
 
#define RL_BUSFREQ_66MHZ   0x01
 
#define RL_BUSWIDTH_32BITS   0x00
 
#define RL_BUSWIDTH_64BITS   0x08
 
#define RL_CPLUSCMD_TXENB   0x0001 /* enable C+ transmit mode */
 
#define RL_CPLUSCMD_RXENB   0x0002 /* enable C+ receive mode */
 
#define RL_CPLUSCMD_PCI_MRW   0x0008 /* enable PCI multi-read/write */
 
#define RL_CPLUSCMD_PCI_DAC   0x0010 /* PCI dual-address cycle only */
 
#define RL_CPLUSCMD_RXCSUM_ENB   0x0020 /* enable RX checksum offload */
 
#define RL_CPLUSCMD_VLANSTRIP   0x0040 /* enable VLAN tag stripping */
 
#define RL_EARLYTXTHRESH_CNT   0x003F /* byte count times 8 */
 
#define RL_PHYAR_PHYDATA   0x0000FFFF
 
#define RL_PHYAR_PHYREG   0x001F0000
 
#define RL_PHYAR_BUSY   0x80000000
 
#define RL_GMEDIASTAT_FDX   0x01 /* full duplex */
 
#define RL_GMEDIASTAT_LINK   0x02 /* link up */
 
#define RL_GMEDIASTAT_10MBPS   0x04 /* 10mps link */
 
#define RL_GMEDIASTAT_100MBPS   0x08 /* 100mbps link */
 
#define RL_GMEDIASTAT_1000MBPS   0x10 /* gigE link */
 
#define RL_GMEDIASTAT_RXFLOW   0x20 /* RX flow control on */
 
#define RL_GMEDIASTAT_TXFLOW   0x40 /* TX flow control on */
 
#define RL_GMEDIASTAT_TBI   0x80 /* TBI enabled */
 
#define RL_RX_BUF_SZ   RL_RXBUF_64
 
#define RL_RXBUFLEN   (1 << ((RL_RX_BUF_SZ >> 11) + 13))
 
#define RL_TX_LIST_CNT   4
 
#define RL_MIN_FRAMELEN   60
 
#define RL_TXTHRESH(x)   ((x) << 11)
 
#define RL_TX_THRESH_INIT   96
 
#define RL_RX_FIFOTHRESH   RL_RXFIFO_256BYTES
 
#define RL_RX_MAXDMA   RL_RXDMA_UNLIMITED
 
#define RL_TX_MAXDMA   RL_TXDMA_2048BYTES
 
#define RL_RXCFG_CONFIG   (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ)
 
#define RL_TXCFG_CONFIG   (RL_TXCFG_IFG|RL_TX_MAXDMA)
 
#define RL_TDESC_CMD_FRAGLEN   0x0000FFFF
 
#define RL_TDESC_CMD_TCPCSUM   0x00010000 /* TCP checksum enable */
 
#define RL_TDESC_CMD_UDPCSUM   0x00020000 /* UDP checksum enable */
 
#define RL_TDESC_CMD_IPCSUM   0x00040000 /* IP header checksum enable */
 
#define RL_TDESC_CMD_MSSVAL   0x07FF0000 /* Large send MSS value */
 
#define RL_TDESC_CMD_LGSEND   0x08000000 /* TCP large send enb */
 
#define RL_TDESC_CMD_EOF   0x10000000 /* end of frame marker */
 
#define RL_TDESC_CMD_SOF   0x20000000 /* start of frame marker */
 
#define RL_TDESC_CMD_EOR   0x40000000 /* end of ring marker */
 
#define RL_TDESC_CMD_OWN   0x80000000 /* chip owns descriptor */
 
#define RL_TDESC_VLANCTL_TAG   0x00020000 /* Insert VLAN tag */
 
#define RL_TDESC_VLANCTL_DATA   0x0000FFFF /* TAG data */
 
#define RL_TDESC_STAT_COLCNT   0x000F0000 /* collision count */
 
#define RL_TDESC_STAT_EXCESSCOL   0x00100000 /* excessive collisions */
 
#define RL_TDESC_STAT_LINKFAIL   0x00200000 /* link faulure */
 
#define RL_TDESC_STAT_OWINCOL   0x00400000 /* out-of-window collision */
 
#define RL_TDESC_STAT_TXERRSUM   0x00800000 /* transmit error summary */
 
#define RL_TDESC_STAT_UNDERRUN   0x02000000 /* TX underrun occured */
 
#define RL_TDESC_STAT_OWN   0x80000000
 
#define RL_RDESC_CMD_EOR   0x40000000
 
#define RL_RDESC_CMD_OWN   0x80000000
 
#define RL_RDESC_CMD_BUFLEN   0x00001FFF
 
#define RL_RDESC_STAT_OWN   0x80000000
 
#define RL_RDESC_STAT_EOR   0x40000000
 
#define RL_RDESC_STAT_SOF   0x20000000
 
#define RL_RDESC_STAT_EOF   0x10000000
 
#define RL_RDESC_STAT_FRALIGN   0x08000000 /* frame alignment error */
 
#define RL_RDESC_STAT_MCAST   0x04000000 /* multicast pkt received */
 
#define RL_RDESC_STAT_UCAST   0x02000000 /* unicast pkt received */
 
#define RL_RDESC_STAT_BCAST   0x01000000 /* broadcast pkt received */
 
#define RL_RDESC_STAT_BUFOFLOW   0x00800000 /* out of buffer space */
 
#define RL_RDESC_STAT_FIFOOFLOW   0x00400000 /* FIFO overrun */
 
#define RL_RDESC_STAT_GIANT   0x00200000 /* pkt > 4096 bytes */
 
#define RL_RDESC_STAT_RXERRSUM   0x00100000 /* RX error summary */
 
#define RL_RDESC_STAT_RUNT   0x00080000 /* runt packet received */
 
#define RL_RDESC_STAT_CRCERR   0x00040000 /* CRC error */
 
#define RL_RDESC_STAT_PROTOID   0x00030000 /* Protocol type */
 
#define RL_RDESC_STAT_IPSUMBAD   0x00008000 /* IP header checksum bad */
 
#define RL_RDESC_STAT_UDPSUMBAD   0x00004000 /* UDP checksum bad */
 
#define RL_RDESC_STAT_TCPSUMBAD   0x00002000 /* TCP checksum bad */
 
#define RL_RDESC_STAT_FRAGLEN   0x00001FFF /* RX'ed frame/frag len */
 
#define RL_RDESC_STAT_GFRAGLEN   0x00003FFF /* RX'ed frame/frag len */
 
#define RL_RDESC_STAT_ERRS
 
#define RL_RDESC_VLANCTL_TAG
 
#define RL_RDESC_VLANCTL_DATA   0x0000FFFF /* TAG data */
 
#define RL_PROTOID_NONIP   0x00000000
 
#define RL_PROTOID_TCPIP   0x00010000
 
#define RL_PROTOID_UDPIP   0x00020000
 
#define RL_PROTOID_IP   0x00030000
 
#define RL_TCPPKT(x)
 
#define RL_UDPPKT(x)
 
#define RL_RX_DESC_CNT   64
 
#define RL_TX_DESC_CNT_8139   64
 
#define RL_TX_DESC_CNT_8169   1024
 
#define RL_TX_QLEN   64
 
#define RL_NTXDESC_RSVD   4
 
#define RL_RX_LIST_SZ   (RL_RX_DESC_CNT * sizeof(struct rl_desc))
 
#define RL_RING_ALIGN   256
 
#define RL_PKTSZ(x)   ((x)/* >> 3*/)
 
#define RE_ETHER_ALIGN   0
 
#define RE_RX_DESC_BUFLEN   MCLBYTES
 
#define RL_TX_DESC_CNT(sc)   ((sc)->rl_ldata.rl_tx_desc_cnt)
 
#define RL_TX_LIST_SZ(sc)   (RL_TX_DESC_CNT(sc) * sizeof(struct rl_desc))
 
#define RL_NEXT_TX_DESC(sc, x)   (((x) + 1) % RL_TX_DESC_CNT(sc))
 
#define RL_NEXT_RX_DESC(sc, x)   (((x) + 1) % RL_RX_DESC_CNT)
 
#define RL_NEXT_TXQ(sc, x)   (((x) + 1) % RL_TX_QLEN)
 
#define RL_TXDESCSYNC(sc, idx, ops)
 
#define RL_RXDESCSYNC(sc, idx, ops)
 
#define RL_ADDR_LO(y)   ((u_int64_t) (y) & 0xFFFFFFFF)
 
#define RL_ADDR_HI(y)   ((u_int64_t) (y) >> 32)
 
#define RL_JUMBO_FRAMELEN   7440
 
#define RL_JUMBO_MTU   (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
 
#define MAX_NUM_MULTICAST_ADDRESSES   128
 
#define RL_INC(x)   (x = (x + 1) % RL_TX_LIST_CNT)
 
#define RL_CUR_TXADDR(x)   ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0)
 
#define RL_CUR_TXSTAT(x)   ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0)
 
#define RL_CUR_TXMBUF(x)   (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx])
 
#define RL_CUR_TXMAP(x)   (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx])
 
#define RL_LAST_TXADDR(x)   ((x->rl_cdata.last_tx * 4) + RL_TXADDR0)
 
#define RL_LAST_TXSTAT(x)   ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0)
 
#define RL_LAST_TXMBUF(x)   (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx])
 
#define RL_LAST_TXMAP(x)   (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx])
 
#define RL_MII_STARTDELIM   0x01
 
#define RL_MII_READOP   0x02
 
#define RL_MII_WRITEOP   0x01
 
#define RL_MII_TURNAROUND   0x02
 
#define RL_UNKNOWN   0
 
#define RL_8129   1
 
#define RL_8139   2
 
#define RL_8139CPLUS   3
 
#define RL_8169   4
 
#define RL_ISCPLUS(x)
 
#define RL_IP4CSUMTX_MINLEN   28
 
#define RL_IP4CSUMTX_PADLEN   (ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN)
 
#define RL_RX_DMAMEM_SZ   (RL_RX_LIST_SZ + RL_IP4CSUMTX_PADLEN)
 
#define RL_TXPADOFF   RL_RX_LIST_SZ
 
#define RL_TXPADDADDR(sc)   ((sc)->rl_ldata.rl_rx_list_map->dm_segs[0].ds_addr + RL_TXPADOFF)
 
#define RL_ATTACHED   0x00000001 /* attach has succeeded */
 
#define RL_ENABLED   0x00000002 /* chip is enabled */
 
#define RL_IS_ENABLED(sc)   ((sc)->sc_flags & RL_ENABLED)
 
#define CSR_WRITE_RAW_4(sc, csr, val)   bus_space_write_raw_region_4(sc->rl_btag, sc->rl_bhandle, csr, val, 4)
 
#define CSR_WRITE_4(sc, csr, val)   bus_space_write_4(sc->rl_btag, sc->rl_bhandle, csr, val)
 
#define CSR_WRITE_2(sc, csr, val)   bus_space_write_2(sc->rl_btag, sc->rl_bhandle, csr, val)
 
#define CSR_WRITE_1(sc, csr, val)   bus_space_write_1(sc->rl_btag, sc->rl_bhandle, csr, val)
 
#define CSR_READ_4(sc, csr)   bus_space_read_4(sc->rl_btag, sc->rl_bhandle, csr)
 
#define CSR_READ_2(sc, csr)   bus_space_read_2(sc->rl_btag, sc->rl_bhandle, csr)
 
#define CSR_READ_1(sc, csr)   bus_space_read_1(sc->rl_btag, sc->rl_bhandle, csr)
 
#define CSR_SETBIT_1(sc, offset, val)   CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val))
 
#define CSR_CLRBIT_1(sc, offset, val)   CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val))
 
#define CSR_SETBIT_2(sc, offset, val)   CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val))
 
#define CSR_CLRBIT_2(sc, offset, val)   CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val))
 
#define CSR_SETBIT_4(sc, offset, val)   CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val))
 
#define CSR_CLRBIT_4(sc, offset, val)   CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val))
 
#define RL_TIMEOUT   1000
 
#define RT_VENDORID   0x10EC
 
#define RT_DEVICEID_8129   0x8129
 
#define RT_DEVICEID_8101E   0x8136
 
#define RT_DEVICEID_8138   0x8138
 
#define RT_DEVICEID_8139   0x8139
 
#define RT_DEVICEID_8169SC   0x8167
 
#define RT_DEVICEID_8168   0x8168
 
#define RT_DEVICEID_8169   0x8169
 
#define RT_DEVICEID_8100   0x8100
 
#define ACCTON_VENDORID   0x1113
 
#define ACCTON_DEVICEID_5030   0x1211
 
#define DELTA_VENDORID   0x1500
 
#define DELTA_DEVICEID_8139   0x1360
 
#define ADDTRON_VENDORID   0x4033
 
#define ADDTRON_DEVICEID_8139   0x1360
 
#define DLINK_VENDORID   0x1186
 
#define DLINK_DEVICEID_8139   0x1300
 
#define DLINK_DEVICEID_8139_2   0x1340
 
#define ABOCOM_DEVICEID_8139   0xab06
 
#define RL_PCI_VENDOR_ID   0x00
 
#define RL_PCI_DEVICE_ID   0x02
 
#define RL_PCI_COMMAND   0x04
 
#define RL_PCI_STATUS   0x06
 
#define RL_PCI_CLASSCODE   0x09
 
#define RL_PCI_LATENCY_TIMER   0x0D
 
#define RL_PCI_HEADER_TYPE   0x0E
 
#define RL_PCI_LOIO   0x10
 
#define RL_PCI_LOMEM   0x14
 
#define RL_PCI_BIOSROM   0x30
 
#define RL_PCI_INTLINE   0x3C
 
#define RL_PCI_INTPIN   0x3D
 
#define RL_PCI_MINGNT   0x3E
 
#define RL_PCI_MINLAT   0x0F
 
#define RL_PCI_RESETOPT   0x48
 
#define RL_PCI_EEPROM_DATA   0x4C
 
#define RL_PCI_CAPID   0x50 /* 8 bits */
 
#define RL_PCI_NEXTPTR   0x51 /* 8 bits */
 
#define RL_PCI_PWRMGMTCAP   0x52 /* 16 bits */
 
#define RL_PCI_PWRMGMTCTRL   0x54 /* 16 bits */
 
#define RL_PSTATE_MASK   0x0003
 
#define RL_PSTATE_D0   0x0000
 
#define RL_PSTATE_D1   0x0002
 
#define RL_PSTATE_D2   0x0002
 
#define RL_PSTATE_D3   0x0003
 
#define RL_PME_EN   0x0010
 
#define RL_PME_STATUS   0x8000
 

Macro Definition Documentation

◆ ABOCOM_DEVICEID_8139

#define ABOCOM_DEVICEID_8139   0xab06

Definition at line 867 of file rtl81x9reg.h.

◆ ACCTON_DEVICEID_5030

#define ACCTON_DEVICEID_5030   0x1211

Definition at line 837 of file rtl81x9reg.h.

◆ ACCTON_VENDORID

#define ACCTON_VENDORID   0x1113

Definition at line 832 of file rtl81x9reg.h.

◆ ADDTRON_DEVICEID_8139

#define ADDTRON_DEVICEID_8139   0x1360

Definition at line 857 of file rtl81x9reg.h.

◆ ADDTRON_VENDORID

#define ADDTRON_VENDORID   0x4033

Definition at line 852 of file rtl81x9reg.h.

◆ CSR_CLRBIT_1

#define CSR_CLRBIT_1 (   sc,
  offset,
  val 
)    CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val))

Definition at line 793 of file rtl81x9reg.h.

◆ CSR_CLRBIT_2

#define CSR_CLRBIT_2 (   sc,
  offset,
  val 
)    CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val))

Definition at line 799 of file rtl81x9reg.h.

◆ CSR_CLRBIT_4

#define CSR_CLRBIT_4 (   sc,
  offset,
  val 
)    CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val))

Definition at line 805 of file rtl81x9reg.h.

◆ CSR_READ_1

#define CSR_READ_1 (   sc,
  csr 
)    bus_space_read_1(sc->rl_btag, sc->rl_bhandle, csr)

Definition at line 787 of file rtl81x9reg.h.

◆ CSR_READ_2

#define CSR_READ_2 (   sc,
  csr 
)    bus_space_read_2(sc->rl_btag, sc->rl_bhandle, csr)

Definition at line 785 of file rtl81x9reg.h.

◆ CSR_READ_4

#define CSR_READ_4 (   sc,
  csr 
)    bus_space_read_4(sc->rl_btag, sc->rl_bhandle, csr)

Definition at line 783 of file rtl81x9reg.h.

◆ CSR_SETBIT_1

#define CSR_SETBIT_1 (   sc,
  offset,
  val 
)    CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val))

Definition at line 790 of file rtl81x9reg.h.

◆ CSR_SETBIT_2

#define CSR_SETBIT_2 (   sc,
  offset,
  val 
)    CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val))

Definition at line 796 of file rtl81x9reg.h.

◆ CSR_SETBIT_4

#define CSR_SETBIT_4 (   sc,
  offset,
  val 
)    CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val))

Definition at line 802 of file rtl81x9reg.h.

◆ CSR_WRITE_1

#define CSR_WRITE_1 (   sc,
  csr,
  val 
)    bus_space_write_1(sc->rl_btag, sc->rl_bhandle, csr, val)

Definition at line 780 of file rtl81x9reg.h.

◆ CSR_WRITE_2

#define CSR_WRITE_2 (   sc,
  csr,
  val 
)    bus_space_write_2(sc->rl_btag, sc->rl_bhandle, csr, val)

Definition at line 778 of file rtl81x9reg.h.

◆ CSR_WRITE_4

#define CSR_WRITE_4 (   sc,
  csr,
  val 
)    bus_space_write_4(sc->rl_btag, sc->rl_bhandle, csr, val)

Definition at line 776 of file rtl81x9reg.h.

◆ CSR_WRITE_RAW_4

#define CSR_WRITE_RAW_4 (   sc,
  csr,
  val 
)    bus_space_write_raw_region_4(sc->rl_btag, sc->rl_bhandle, csr, val, 4)

Definition at line 774 of file rtl81x9reg.h.

◆ DELTA_DEVICEID_8139

#define DELTA_DEVICEID_8139   0x1360

Definition at line 847 of file rtl81x9reg.h.

◆ DELTA_VENDORID

#define DELTA_VENDORID   0x1500

Definition at line 842 of file rtl81x9reg.h.

◆ DLINK_DEVICEID_8139

#define DLINK_DEVICEID_8139   0x1300

Definition at line 863 of file rtl81x9reg.h.

◆ DLINK_DEVICEID_8139_2

#define DLINK_DEVICEID_8139_2   0x1340

Definition at line 864 of file rtl81x9reg.h.

◆ DLINK_VENDORID

#define DLINK_VENDORID   0x1186

Definition at line 860 of file rtl81x9reg.h.

◆ MAX_NUM_MULTICAST_ADDRESSES

#define MAX_NUM_MULTICAST_ADDRESSES   128

Definition at line 640 of file rtl81x9reg.h.

◆ RE_ETHER_ALIGN

#define RE_ETHER_ALIGN   0

Definition at line 605 of file rtl81x9reg.h.

◆ RE_RX_DESC_BUFLEN

#define RE_RX_DESC_BUFLEN   MCLBYTES

Definition at line 606 of file rtl81x9reg.h.

◆ RL_8129

#define RL_8129   1

Definition at line 675 of file rtl81x9reg.h.

◆ RL_8139

#define RL_8139   2

Definition at line 676 of file rtl81x9reg.h.

◆ RL_8139CPLUS

#define RL_8139CPLUS   3

Definition at line 677 of file rtl81x9reg.h.

◆ RL_8169

#define RL_8169   4

Definition at line 678 of file rtl81x9reg.h.

◆ RL_9346_ERASE

#define RL_9346_ERASE   0x7

Definition at line 318 of file rtl81x9reg.h.

◆ RL_9346_EWDS_ADDR

#define RL_9346_EWDS_ADDR   0x00

Definition at line 322 of file rtl81x9reg.h.

◆ RL_9346_EWEN

#define RL_9346_EWEN   0x4

Definition at line 319 of file rtl81x9reg.h.

◆ RL_9346_EWEN_ADDR

#define RL_9346_EWEN_ADDR   0x30

Definition at line 320 of file rtl81x9reg.h.

◆ RL_9346_READ

#define RL_9346_READ   0x6

Definition at line 317 of file rtl81x9reg.h.

◆ RL_9346_WRITE

#define RL_9346_WRITE   0x5

Definition at line 316 of file rtl81x9reg.h.

◆ RL_9456_EWDS

#define RL_9456_EWDS   0x4

Definition at line 321 of file rtl81x9reg.h.

◆ RL_ADDR_HI

#define RL_ADDR_HI (   y)    ((u_int64_t) (y) >> 32)

Definition at line 634 of file rtl81x9reg.h.

◆ RL_ADDR_LO

#define RL_ADDR_LO (   y)    ((u_int64_t) (y) & 0xFFFFFFFF)

Definition at line 633 of file rtl81x9reg.h.

◆ RL_ANAR

#define RL_ANAR   0x0066 /* PHY autoneg advert */

Definition at line 98 of file rtl81x9reg.h.

◆ RL_ANER

#define RL_ANER   0x006A /* PHY autoneg expansion */

Definition at line 100 of file rtl81x9reg.h.

◆ RL_ATTACHED

#define RL_ATTACHED   0x00000001 /* attach has succeeded */

Definition at line 767 of file rtl81x9reg.h.

◆ RL_BMCR

#define RL_BMCR   0x0062 /* PHY basic mode control */

Definition at line 96 of file rtl81x9reg.h.

◆ RL_BMSR

#define RL_BMSR   0x0064 /* PHY basic mode status */

Definition at line 97 of file rtl81x9reg.h.

◆ RL_BUSFREQ_33MHZ

#define RL_BUSFREQ_33MHZ   0x00

Definition at line 395 of file rtl81x9reg.h.

◆ RL_BUSFREQ_66MHZ

#define RL_BUSFREQ_66MHZ   0x01

Definition at line 396 of file rtl81x9reg.h.

◆ RL_BUSWIDTH_32BITS

#define RL_BUSWIDTH_32BITS   0x00

Definition at line 398 of file rtl81x9reg.h.

◆ RL_BUSWIDTH_64BITS

#define RL_BUSWIDTH_64BITS   0x08

Definition at line 399 of file rtl81x9reg.h.

◆ RL_CFG0

#define RL_CFG0   0x0051 /* config register #0 */

Definition at line 83 of file rtl81x9reg.h.

◆ RL_CFG0_10MBPS

#define RL_CFG0_10MBPS   0x20 /* 10 Mbps internal mode */

Definition at line 357 of file rtl81x9reg.h.

◆ RL_CFG0_PCS

#define RL_CFG0_PCS   0x40

Definition at line 358 of file rtl81x9reg.h.

◆ RL_CFG0_PL0

#define RL_CFG0_PL0   0x08

Definition at line 355 of file rtl81x9reg.h.

◆ RL_CFG0_PL1

#define RL_CFG0_PL1   0x10

Definition at line 356 of file rtl81x9reg.h.

◆ RL_CFG0_ROM0

#define RL_CFG0_ROM0   0x01

Definition at line 352 of file rtl81x9reg.h.

◆ RL_CFG0_ROM1

#define RL_CFG0_ROM1   0x02

Definition at line 353 of file rtl81x9reg.h.

◆ RL_CFG0_ROM2

#define RL_CFG0_ROM2   0x04

Definition at line 354 of file rtl81x9reg.h.

◆ RL_CFG0_SCR

#define RL_CFG0_SCR   0x80

Definition at line 359 of file rtl81x9reg.h.

◆ RL_CFG1

#define RL_CFG1   0x0052 /* config register #1 */

Definition at line 84 of file rtl81x9reg.h.

◆ RL_CFG1_DRVLOAD

#define RL_CFG1_DRVLOAD   0x20

Definition at line 369 of file rtl81x9reg.h.

◆ RL_CFG1_FULLDUPLEX

#define RL_CFG1_FULLDUPLEX   0x40 /* 8129 only */

Definition at line 371 of file rtl81x9reg.h.

◆ RL_CFG1_IOMAP

#define RL_CFG1_IOMAP   0x04

Definition at line 366 of file rtl81x9reg.h.

◆ RL_CFG1_LED0

#define RL_CFG1_LED0   0x40

Definition at line 370 of file rtl81x9reg.h.

◆ RL_CFG1_LED1

#define RL_CFG1_LED1   0x80

Definition at line 372 of file rtl81x9reg.h.

◆ RL_CFG1_MEMMAP

#define RL_CFG1_MEMMAP   0x08

Definition at line 367 of file rtl81x9reg.h.

◆ RL_CFG1_PWRDWN

#define RL_CFG1_PWRDWN   0x01

Definition at line 364 of file rtl81x9reg.h.

◆ RL_CFG1_RSVD

#define RL_CFG1_RSVD   0x10

Definition at line 368 of file rtl81x9reg.h.

◆ RL_CFG1_SLEEP

#define RL_CFG1_SLEEP   0x02

Definition at line 365 of file rtl81x9reg.h.

◆ RL_CFG2

#define RL_CFG2   0x0053

Definition at line 119 of file rtl81x9reg.h.

◆ RL_CFG2_AUXPWRSTS

#define RL_CFG2_AUXPWRSTS   0x10

Definition at line 393 of file rtl81x9reg.h.

◆ RL_CFG2_BUSFREQ

#define RL_CFG2_BUSFREQ   0x07

Definition at line 391 of file rtl81x9reg.h.

◆ RL_CFG2_BUSWIDTH

#define RL_CFG2_BUSWIDTH   0x08

Definition at line 392 of file rtl81x9reg.h.

◆ RL_CMD_EMPTY_RXBUF

#define RL_CMD_EMPTY_RXBUF   0x0001

Definition at line 295 of file rtl81x9reg.h.

◆ RL_CMD_RESET

#define RL_CMD_RESET   0x0010

Definition at line 298 of file rtl81x9reg.h.

◆ RL_CMD_RX_ENB

#define RL_CMD_RX_ENB   0x0008

Definition at line 297 of file rtl81x9reg.h.

◆ RL_CMD_TX_ENB

#define RL_CMD_TX_ENB   0x0004

Definition at line 296 of file rtl81x9reg.h.

◆ RL_COMMAND

#define RL_COMMAND   0x0037 /* command register */

Definition at line 73 of file rtl81x9reg.h.

◆ RL_CPLUS_CMD

#define RL_CPLUS_CMD   0x00E0 /* 16 bits */

Definition at line 122 of file rtl81x9reg.h.

◆ RL_CPLUSCMD_PCI_DAC

#define RL_CPLUSCMD_PCI_DAC   0x0010 /* PCI dual-address cycle only */

Definition at line 406 of file rtl81x9reg.h.

◆ RL_CPLUSCMD_PCI_MRW

#define RL_CPLUSCMD_PCI_MRW   0x0008 /* enable PCI multi-read/write */

Definition at line 405 of file rtl81x9reg.h.

◆ RL_CPLUSCMD_RXCSUM_ENB

#define RL_CPLUSCMD_RXCSUM_ENB   0x0020 /* enable RX checksum offload */

Definition at line 407 of file rtl81x9reg.h.

◆ RL_CPLUSCMD_RXENB

#define RL_CPLUSCMD_RXENB   0x0002 /* enable C+ receive mode */

Definition at line 404 of file rtl81x9reg.h.

◆ RL_CPLUSCMD_TXENB

#define RL_CPLUSCMD_TXENB   0x0001 /* enable C+ transmit mode */

Definition at line 403 of file rtl81x9reg.h.

◆ RL_CPLUSCMD_VLANSTRIP

#define RL_CPLUSCMD_VLANSTRIP   0x0040 /* enable VLAN tag stripping */

Definition at line 408 of file rtl81x9reg.h.

◆ RL_CSCFG

#define RL_CSCFG   0x0074 /* CS configuration register */

Definition at line 106 of file rtl81x9reg.h.

◆ RL_CUR_TXADDR

#define RL_CUR_TXADDR (   x)    ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0)

Definition at line 643 of file rtl81x9reg.h.

◆ RL_CUR_TXMAP

#define RL_CUR_TXMAP (   x)    (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx])

Definition at line 646 of file rtl81x9reg.h.

◆ RL_CUR_TXMBUF

#define RL_CUR_TXMBUF (   x)    (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx])

Definition at line 645 of file rtl81x9reg.h.

◆ RL_CUR_TXSTAT

#define RL_CUR_TXSTAT (   x)    ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0)

Definition at line 644 of file rtl81x9reg.h.

◆ RL_CURRXADDR

#define RL_CURRXADDR   0x0038 /* current address of packet read */

Definition at line 74 of file rtl81x9reg.h.

◆ RL_CURRXBUF

#define RL_CURRXBUF   0x003A /* current RX buffer address */

Definition at line 75 of file rtl81x9reg.h.

◆ RL_DISCCNT

#define RL_DISCCNT   0x006C /* disconnect counter */

Definition at line 102 of file rtl81x9reg.h.

◆ RL_DUMPSTATS_HI

#define RL_DUMPSTATS_HI   0x0014 /* counter dump command register */

Definition at line 114 of file rtl81x9reg.h.

◆ RL_DUMPSTATS_LO

#define RL_DUMPSTATS_LO   0x0010 /* counter dump command register */

Definition at line 113 of file rtl81x9reg.h.

◆ RL_DUMPSTATS_START

#define RL_DUMPSTATS_START   0x00000008

Definition at line 380 of file rtl81x9reg.h.

◆ RL_EARLY_TX_THRESH

#define RL_EARLY_TX_THRESH   0x00EC /* 8 bits */

Definition at line 125 of file rtl81x9reg.h.

◆ RL_EARLYTXTHRESH_CNT

#define RL_EARLYTXTHRESH_CNT   0x003F /* byte count times 8 */

Definition at line 412 of file rtl81x9reg.h.

◆ RL_EE_CLK

#define RL_EE_CLK   0x04 /* clock */

Definition at line 305 of file rtl81x9reg.h.

◆ RL_EE_DATAIN

#define RL_EE_DATAIN   0x02 /* Data in */

Definition at line 304 of file rtl81x9reg.h.

◆ RL_EE_DATAOUT

#define RL_EE_DATAOUT   0x01 /* Data out */

Definition at line 303 of file rtl81x9reg.h.

◆ RL_EE_EADDR

#define RL_EE_EADDR   0x07

Definition at line 339 of file rtl81x9reg.h.

◆ RL_EE_ID

#define RL_EE_ID   0x00

Definition at line 335 of file rtl81x9reg.h.

◆ RL_EE_MODE

#define RL_EE_MODE   (0x40|0x80)

Definition at line 307 of file rtl81x9reg.h.

◆ RL_EE_PCI_DID

#define RL_EE_PCI_DID   0x02

Definition at line 337 of file rtl81x9reg.h.

◆ RL_EE_PCI_VID

#define RL_EE_PCI_VID   0x01

Definition at line 336 of file rtl81x9reg.h.

◆ RL_EE_SEL

#define RL_EE_SEL   0x08 /* chip select */

Definition at line 306 of file rtl81x9reg.h.

◆ RL_EEADDR_LEN0

#define RL_EEADDR_LEN0   6 /* 9346 */

Definition at line 329 of file rtl81x9reg.h.

◆ RL_EEADDR_LEN1

#define RL_EEADDR_LEN1   8 /* 9356 */

Definition at line 330 of file rtl81x9reg.h.

◆ RL_EECMD

#define RL_EECMD   0x0050 /* EEPROM command register */

Definition at line 82 of file rtl81x9reg.h.

◆ RL_EECMD_ERASE

#define RL_EECMD_ERASE   0x7 /* 0111b */

Definition at line 326 of file rtl81x9reg.h.

◆ RL_EECMD_LEN

#define RL_EECMD_LEN   4

Definition at line 327 of file rtl81x9reg.h.

◆ RL_EECMD_READ

#define RL_EECMD_READ   0x6 /* 0110b */

Definition at line 325 of file rtl81x9reg.h.

◆ RL_EECMD_READ_6BIT

#define RL_EECMD_READ_6BIT   0x180 /* XXX */

Definition at line 332 of file rtl81x9reg.h.

◆ RL_EECMD_READ_8BIT

#define RL_EECMD_READ_8BIT   0x600 /* EECMD_READ above maybe wrong? */

Definition at line 333 of file rtl81x9reg.h.

◆ RL_EECMD_WRITE

#define RL_EECMD_WRITE   0x5 /* 0101b */

Definition at line 324 of file rtl81x9reg.h.

◆ RL_EEMODE_AUTOLOAD

#define RL_EEMODE_AUTOLOAD   0x40

Definition at line 310 of file rtl81x9reg.h.

◆ RL_EEMODE_OFF

#define RL_EEMODE_OFF   0x00

Definition at line 309 of file rtl81x9reg.h.

◆ RL_EEMODE_PROGRAM

#define RL_EEMODE_PROGRAM   0x80

Definition at line 311 of file rtl81x9reg.h.

◆ RL_EEMODE_WRITECFG

#define RL_EEMODE_WRITECFG   (0x80|0x40)

Definition at line 312 of file rtl81x9reg.h.

◆ RL_ENABLED

#define RL_ENABLED   0x00000002 /* chip is enabled */

Definition at line 768 of file rtl81x9reg.h.

◆ RL_FALSECAR

#define RL_FALSECAR   0x006E /* false carrier counter */

Definition at line 103 of file rtl81x9reg.h.

◆ RL_GMEDIASTAT

#define RL_GMEDIASTAT   0x006C /* 8 bits */

Definition at line 135 of file rtl81x9reg.h.

◆ RL_GMEDIASTAT_1000MBPS

#define RL_GMEDIASTAT_1000MBPS   0x10 /* gigE link */

Definition at line 429 of file rtl81x9reg.h.

◆ RL_GMEDIASTAT_100MBPS

#define RL_GMEDIASTAT_100MBPS   0x08 /* 100mbps link */

Definition at line 428 of file rtl81x9reg.h.

◆ RL_GMEDIASTAT_10MBPS

#define RL_GMEDIASTAT_10MBPS   0x04 /* 10mps link */

Definition at line 427 of file rtl81x9reg.h.

◆ RL_GMEDIASTAT_FDX

#define RL_GMEDIASTAT_FDX   0x01 /* full duplex */

Definition at line 425 of file rtl81x9reg.h.

◆ RL_GMEDIASTAT_LINK

#define RL_GMEDIASTAT_LINK   0x02 /* link up */

Definition at line 426 of file rtl81x9reg.h.

◆ RL_GMEDIASTAT_RXFLOW

#define RL_GMEDIASTAT_RXFLOW   0x20 /* RX flow control on */

Definition at line 430 of file rtl81x9reg.h.

◆ RL_GMEDIASTAT_TBI

#define RL_GMEDIASTAT_TBI   0x80 /* TBI enabled */

Definition at line 432 of file rtl81x9reg.h.

◆ RL_GMEDIASTAT_TXFLOW

#define RL_GMEDIASTAT_TXFLOW   0x40 /* TX flow control on */

Definition at line 431 of file rtl81x9reg.h.

◆ RL_GTXSTART

#define RL_GTXSTART   0x0038 /* 16 bits */

Definition at line 137 of file rtl81x9reg.h.

◆ RL_HALTCLK

#define RL_HALTCLK   0x005B

Definition at line 89 of file rtl81x9reg.h.

◆ RL_HWREV_8100

#define RL_HWREV_8100   0x78800000

Definition at line 174 of file rtl81x9reg.h.

◆ RL_HWREV_8100E_SPIN1

#define RL_HWREV_8100E_SPIN1   0x30800000

Definition at line 161 of file rtl81x9reg.h.

◆ RL_HWREV_8100E_SPIN2

#define RL_HWREV_8100E_SPIN2   0x38800000

Definition at line 164 of file rtl81x9reg.h.

◆ RL_HWREV_8101

#define RL_HWREV_8101   0x74c00000

Definition at line 173 of file rtl81x9reg.h.

◆ RL_HWREV_8101E

#define RL_HWREV_8101E   0x34000000

Definition at line 162 of file rtl81x9reg.h.

◆ RL_HWREV_8110S

#define RL_HWREV_8110S   0x00800000

Definition at line 156 of file rtl81x9reg.h.

◆ RL_HWREV_8130

#define RL_HWREV_8130   0x7C000000

Definition at line 169 of file rtl81x9reg.h.

◆ RL_HWREV_8139

#define RL_HWREV_8139   0x60000000

Definition at line 165 of file rtl81x9reg.h.

◆ RL_HWREV_8139A

#define RL_HWREV_8139A   0x70000000

Definition at line 166 of file rtl81x9reg.h.

◆ RL_HWREV_8139AG

#define RL_HWREV_8139AG   0x70800000

Definition at line 167 of file rtl81x9reg.h.

◆ RL_HWREV_8139B

#define RL_HWREV_8139B   0x78000000

Definition at line 168 of file rtl81x9reg.h.

◆ RL_HWREV_8139C

#define RL_HWREV_8139C   0x74000000

Definition at line 170 of file rtl81x9reg.h.

◆ RL_HWREV_8139CPLUS

#define RL_HWREV_8139CPLUS   0x74800000

Definition at line 172 of file rtl81x9reg.h.

◆ RL_HWREV_8139D

#define RL_HWREV_8139D   0x74400000

Definition at line 171 of file rtl81x9reg.h.

◆ RL_HWREV_8168_SPIN1

#define RL_HWREV_8168_SPIN1   0x30000000

Definition at line 160 of file rtl81x9reg.h.

◆ RL_HWREV_8168_SPIN2

#define RL_HWREV_8168_SPIN2   0x38000000

Definition at line 163 of file rtl81x9reg.h.

◆ RL_HWREV_8169

#define RL_HWREV_8169   0x00000000

Definition at line 155 of file rtl81x9reg.h.

◆ RL_HWREV_8169_8110SB

#define RL_HWREV_8169_8110SB   0x10000000

Definition at line 158 of file rtl81x9reg.h.

◆ RL_HWREV_8169_8110SC

#define RL_HWREV_8169_8110SC   0x18000000

Definition at line 159 of file rtl81x9reg.h.

◆ RL_HWREV_8169S

#define RL_HWREV_8169S   0x04000000

Definition at line 157 of file rtl81x9reg.h.

◆ RL_IDR0

#define RL_IDR0   0x0000 /* ID register 0 (station addr) */

Definition at line 44 of file rtl81x9reg.h.

◆ RL_IDR1

#define RL_IDR1   0x0001 /* Must use 32-bit accesses (?) */

Definition at line 45 of file rtl81x9reg.h.

◆ RL_IDR2

#define RL_IDR2   0x0002

Definition at line 46 of file rtl81x9reg.h.

◆ RL_IDR3

#define RL_IDR3   0x0003

Definition at line 47 of file rtl81x9reg.h.

◆ RL_IDR4

#define RL_IDR4   0x0004

Definition at line 48 of file rtl81x9reg.h.

◆ RL_IDR5

#define RL_IDR5   0x0005

Definition at line 49 of file rtl81x9reg.h.

◆ RL_IMR

#define RL_IMR   0x003C /* interrupt mask register */

Definition at line 76 of file rtl81x9reg.h.

◆ RL_INC

#define RL_INC (   x)    (x = (x + 1) % RL_TX_LIST_CNT)

Definition at line 642 of file rtl81x9reg.h.

◆ RL_INTRS

#define RL_INTRS
Value:

Definition at line 217 of file rtl81x9reg.h.

◆ RL_INTRS_CPLUS

#define RL_INTRS_CPLUS
Value:

Definition at line 222 of file rtl81x9reg.h.

◆ RL_IP4CSUMTX_MINLEN

#define RL_IP4CSUMTX_MINLEN   28

Definition at line 753 of file rtl81x9reg.h.

◆ RL_IP4CSUMTX_PADLEN

#define RL_IP4CSUMTX_PADLEN   (ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN)

Definition at line 754 of file rtl81x9reg.h.

◆ RL_IS_ENABLED

#define RL_IS_ENABLED (   sc)    ((sc)->sc_flags & RL_ENABLED)

Definition at line 769 of file rtl81x9reg.h.

◆ RL_ISCPLUS

#define RL_ISCPLUS (   x)
Value:
((x)->rl_type == RL_8139CPLUS || \
(x)->rl_type == RL_8169)

Definition at line 680 of file rtl81x9reg.h.

◆ RL_ISR

#define RL_ISR   0x003E /* interrupt status register */

Definition at line 77 of file rtl81x9reg.h.

◆ RL_ISR_CABLE_LEN_CHGD

#define RL_ISR_CABLE_LEN_CHGD   0x2000

Definition at line 212 of file rtl81x9reg.h.

◆ RL_ISR_FIFO_OFLOW

#define RL_ISR_FIFO_OFLOW   0x0040 /* 8139 only */

Definition at line 209 of file rtl81x9reg.h.

◆ RL_ISR_LINKCHG

#define RL_ISR_LINKCHG   0x0020 /* 8169 only */

Definition at line 208 of file rtl81x9reg.h.

◆ RL_ISR_PCS_TIMEOUT

#define RL_ISR_PCS_TIMEOUT   0x4000 /* 8129 only */

Definition at line 213 of file rtl81x9reg.h.

◆ RL_ISR_PKT_UNDERRUN

#define RL_ISR_PKT_UNDERRUN   0x0020

Definition at line 207 of file rtl81x9reg.h.

◆ RL_ISR_RX_ERR

#define RL_ISR_RX_ERR   0x0002

Definition at line 203 of file rtl81x9reg.h.

◆ RL_ISR_RX_OK

#define RL_ISR_RX_OK   0x0001

Definition at line 202 of file rtl81x9reg.h.

◆ RL_ISR_RX_OVERRUN

#define RL_ISR_RX_OVERRUN   0x0010

Definition at line 206 of file rtl81x9reg.h.

◆ RL_ISR_SWI

#define RL_ISR_SWI   0x0100 /* C+ only */

Definition at line 211 of file rtl81x9reg.h.

◆ RL_ISR_SYSTEM_ERR

#define RL_ISR_SYSTEM_ERR   0x8000

Definition at line 215 of file rtl81x9reg.h.

◆ RL_ISR_TIMEOUT_EXPIRED

#define RL_ISR_TIMEOUT_EXPIRED   0x4000

Definition at line 214 of file rtl81x9reg.h.

◆ RL_ISR_TX_DESC_UNAVAIL

#define RL_ISR_TX_DESC_UNAVAIL   0x0080 /* C+ only */

Definition at line 210 of file rtl81x9reg.h.

◆ RL_ISR_TX_ERR

#define RL_ISR_TX_ERR   0x0008

Definition at line 205 of file rtl81x9reg.h.

◆ RL_ISR_TX_OK

#define RL_ISR_TX_OK   0x0004

Definition at line 204 of file rtl81x9reg.h.

◆ RL_JUMBO_FRAMELEN

#define RL_JUMBO_FRAMELEN   7440

Definition at line 637 of file rtl81x9reg.h.

◆ RL_JUMBO_MTU

#define RL_JUMBO_MTU   (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)

Definition at line 638 of file rtl81x9reg.h.

◆ RL_LAST_TXADDR

#define RL_LAST_TXADDR (   x)    ((x->rl_cdata.last_tx * 4) + RL_TXADDR0)

Definition at line 647 of file rtl81x9reg.h.

◆ RL_LAST_TXMAP

#define RL_LAST_TXMAP (   x)    (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx])

Definition at line 650 of file rtl81x9reg.h.

◆ RL_LAST_TXMBUF

#define RL_LAST_TXMBUF (   x)    (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx])

Definition at line 649 of file rtl81x9reg.h.

◆ RL_LAST_TXSTAT

#define RL_LAST_TXSTAT (   x)    ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0)

Definition at line 648 of file rtl81x9reg.h.

◆ RL_LOOPTEST_OFF

#define RL_LOOPTEST_OFF   0x00000000

Definition at line 149 of file rtl81x9reg.h.

◆ RL_LOOPTEST_ON

#define RL_LOOPTEST_ON   0x00020000

Definition at line 150 of file rtl81x9reg.h.

◆ RL_LOOPTEST_ON_CPLUS

#define RL_LOOPTEST_ON_CPLUS   0x00060000

Definition at line 151 of file rtl81x9reg.h.

◆ RL_LPAR

#define RL_LPAR   0x0068 /* PHY link partner ability */

Definition at line 99 of file rtl81x9reg.h.

◆ RL_MAR0

#define RL_MAR0   0x0008 /* Multicast hash table */

Definition at line 51 of file rtl81x9reg.h.

◆ RL_MAR1

#define RL_MAR1   0x0009

Definition at line 52 of file rtl81x9reg.h.

◆ RL_MAR2

#define RL_MAR2   0x000A

Definition at line 53 of file rtl81x9reg.h.

◆ RL_MAR3

#define RL_MAR3   0x000B

Definition at line 54 of file rtl81x9reg.h.

◆ RL_MAR4

#define RL_MAR4   0x000C

Definition at line 55 of file rtl81x9reg.h.

◆ RL_MAR5

#define RL_MAR5   0x000D

Definition at line 56 of file rtl81x9reg.h.

◆ RL_MAR6

#define RL_MAR6   0x000E

Definition at line 57 of file rtl81x9reg.h.

◆ RL_MAR7

#define RL_MAR7   0x000F

Definition at line 58 of file rtl81x9reg.h.

◆ RL_MAXRXPKTLEN

#define RL_MAXRXPKTLEN   0x00DA /* 16 bits, chip multiplies by 8 */

Definition at line 136 of file rtl81x9reg.h.

◆ RL_MEDIASTAT

#define RL_MEDIASTAT   0x0058 /* media status register (8139) */

Definition at line 86 of file rtl81x9reg.h.

◆ RL_MEDIASTAT_LINK

#define RL_MEDIASTAT_LINK   0x04

Definition at line 233 of file rtl81x9reg.h.

◆ RL_MEDIASTAT_RXFLOWCTL

#define RL_MEDIASTAT_RXFLOWCTL   0x40 /* duplex mode */

Definition at line 235 of file rtl81x9reg.h.

◆ RL_MEDIASTAT_RXPAUSE

#define RL_MEDIASTAT_RXPAUSE   0x01

Definition at line 231 of file rtl81x9reg.h.

◆ RL_MEDIASTAT_SPEED10

#define RL_MEDIASTAT_SPEED10   0x08

Definition at line 234 of file rtl81x9reg.h.

◆ RL_MEDIASTAT_TXFLOWCTL

#define RL_MEDIASTAT_TXFLOWCTL   0x80 /* duplex mode */

Definition at line 236 of file rtl81x9reg.h.

◆ RL_MEDIASTAT_TXPAUSE

#define RL_MEDIASTAT_TXPAUSE   0x02

Definition at line 232 of file rtl81x9reg.h.

◆ RL_MII

#define RL_MII   0x005A /* 8129 chip only */

Definition at line 88 of file rtl81x9reg.h.

◆ RL_MII_CLK

#define RL_MII_CLK   0x01

Definition at line 344 of file rtl81x9reg.h.

◆ RL_MII_DATAIN

#define RL_MII_DATAIN   0x02

Definition at line 345 of file rtl81x9reg.h.

◆ RL_MII_DATAOUT

#define RL_MII_DATAOUT   0x04

Definition at line 346 of file rtl81x9reg.h.

◆ RL_MII_DIR

#define RL_MII_DIR   0x80 /* 0 == input, 1 == output */

Definition at line 347 of file rtl81x9reg.h.

◆ RL_MII_READOP

#define RL_MII_READOP   0x02

Definition at line 670 of file rtl81x9reg.h.

◆ RL_MII_STARTDELIM

#define RL_MII_STARTDELIM   0x01

Definition at line 669 of file rtl81x9reg.h.

◆ RL_MII_TURNAROUND

#define RL_MII_TURNAROUND   0x02

Definition at line 672 of file rtl81x9reg.h.

◆ RL_MII_WRITEOP

#define RL_MII_WRITEOP   0x01

Definition at line 671 of file rtl81x9reg.h.

◆ RL_MIN_FRAMELEN

#define RL_MIN_FRAMELEN   60

Definition at line 452 of file rtl81x9reg.h.

◆ RL_MISSEDPKT

#define RL_MISSEDPKT   0x004C /* missed packet counter */

Definition at line 81 of file rtl81x9reg.h.

◆ RL_MULTIINTR

#define RL_MULTIINTR   0x005C /* multiple interrupt */

Definition at line 90 of file rtl81x9reg.h.

◆ RL_NEXT_RX_DESC

#define RL_NEXT_RX_DESC (   sc,
 
)    (((x) + 1) % RL_RX_DESC_CNT)

Definition at line 615 of file rtl81x9reg.h.

◆ RL_NEXT_TX_DESC

#define RL_NEXT_TX_DESC (   sc,
 
)    (((x) + 1) % RL_TX_DESC_CNT(sc))

Definition at line 613 of file rtl81x9reg.h.

◆ RL_NEXT_TXQ

#define RL_NEXT_TXQ (   sc,
 
)    (((x) + 1) % RL_TX_QLEN)

Definition at line 617 of file rtl81x9reg.h.

◆ RL_NTXDESC_RSVD

#define RL_NTXDESC_RSVD   4

Definition at line 596 of file rtl81x9reg.h.

◆ RL_NWAYTST

#define RL_NWAYTST   0x0070 /* NWAY test register */

Definition at line 104 of file rtl81x9reg.h.

◆ RL_PCI_BIOSROM

#define RL_PCI_BIOSROM   0x30

Definition at line 884 of file rtl81x9reg.h.

◆ RL_PCI_CAPID

#define RL_PCI_CAPID   0x50 /* 8 bits */

Definition at line 892 of file rtl81x9reg.h.

◆ RL_PCI_CLASSCODE

#define RL_PCI_CLASSCODE   0x09

Definition at line 879 of file rtl81x9reg.h.

◆ RL_PCI_COMMAND

#define RL_PCI_COMMAND   0x04

Definition at line 877 of file rtl81x9reg.h.

◆ RL_PCI_DEVICE_ID

#define RL_PCI_DEVICE_ID   0x02

Definition at line 876 of file rtl81x9reg.h.

◆ RL_PCI_EEPROM_DATA

#define RL_PCI_EEPROM_DATA   0x4C

Definition at line 890 of file rtl81x9reg.h.

◆ RL_PCI_HEADER_TYPE

#define RL_PCI_HEADER_TYPE   0x0E

Definition at line 881 of file rtl81x9reg.h.

◆ RL_PCI_INTLINE

#define RL_PCI_INTLINE   0x3C

Definition at line 885 of file rtl81x9reg.h.

◆ RL_PCI_INTPIN

#define RL_PCI_INTPIN   0x3D

Definition at line 886 of file rtl81x9reg.h.

◆ RL_PCI_LATENCY_TIMER

#define RL_PCI_LATENCY_TIMER   0x0D

Definition at line 880 of file rtl81x9reg.h.

◆ RL_PCI_LOIO

#define RL_PCI_LOIO   0x10

Definition at line 882 of file rtl81x9reg.h.

◆ RL_PCI_LOMEM

#define RL_PCI_LOMEM   0x14

Definition at line 883 of file rtl81x9reg.h.

◆ RL_PCI_MINGNT

#define RL_PCI_MINGNT   0x3E

Definition at line 887 of file rtl81x9reg.h.

◆ RL_PCI_MINLAT

#define RL_PCI_MINLAT   0x0F

Definition at line 888 of file rtl81x9reg.h.

◆ RL_PCI_NEXTPTR

#define RL_PCI_NEXTPTR   0x51 /* 8 bits */

Definition at line 893 of file rtl81x9reg.h.

◆ RL_PCI_PWRMGMTCAP

#define RL_PCI_PWRMGMTCAP   0x52 /* 16 bits */

Definition at line 894 of file rtl81x9reg.h.

◆ RL_PCI_PWRMGMTCTRL

#define RL_PCI_PWRMGMTCTRL   0x54 /* 16 bits */

Definition at line 895 of file rtl81x9reg.h.

◆ RL_PCI_RESETOPT

#define RL_PCI_RESETOPT   0x48

Definition at line 889 of file rtl81x9reg.h.

◆ RL_PCI_STATUS

#define RL_PCI_STATUS   0x06

Definition at line 878 of file rtl81x9reg.h.

◆ RL_PCI_VENDOR_ID

#define RL_PCI_VENDOR_ID   0x00

Definition at line 875 of file rtl81x9reg.h.

◆ RL_PCIREV

#define RL_PCIREV   0x005E /* PCI revision value */

Definition at line 91 of file rtl81x9reg.h.

◆ RL_PHYAR

#define RL_PHYAR   0x0060

Definition at line 131 of file rtl81x9reg.h.

◆ RL_PHYAR_BUSY

#define RL_PHYAR_BUSY   0x80000000

Definition at line 420 of file rtl81x9reg.h.

◆ RL_PHYAR_PHYDATA

#define RL_PHYAR_PHYDATA   0x0000FFFF

Definition at line 418 of file rtl81x9reg.h.

◆ RL_PHYAR_PHYREG

#define RL_PHYAR_PHYREG   0x001F0000

Definition at line 419 of file rtl81x9reg.h.

◆ RL_PKTSZ

#define RL_PKTSZ (   x)    ((x)/* >> 3*/)

Definition at line 600 of file rtl81x9reg.h.

◆ RL_PME_EN

#define RL_PME_EN   0x0010

Definition at line 902 of file rtl81x9reg.h.

◆ RL_PME_STATUS

#define RL_PME_STATUS   0x8000

Definition at line 903 of file rtl81x9reg.h.

◆ RL_PROTOID_IP

#define RL_PROTOID_IP   0x00030000

Definition at line 562 of file rtl81x9reg.h.

◆ RL_PROTOID_NONIP

#define RL_PROTOID_NONIP   0x00000000

Definition at line 559 of file rtl81x9reg.h.

◆ RL_PROTOID_TCPIP

#define RL_PROTOID_TCPIP   0x00010000

Definition at line 560 of file rtl81x9reg.h.

◆ RL_PROTOID_UDPIP

#define RL_PROTOID_UDPIP   0x00020000

Definition at line 561 of file rtl81x9reg.h.

◆ RL_PSTATE_D0

#define RL_PSTATE_D0   0x0000

Definition at line 898 of file rtl81x9reg.h.

◆ RL_PSTATE_D1

#define RL_PSTATE_D1   0x0002

Definition at line 899 of file rtl81x9reg.h.

◆ RL_PSTATE_D2

#define RL_PSTATE_D2   0x0002

Definition at line 900 of file rtl81x9reg.h.

◆ RL_PSTATE_D3

#define RL_PSTATE_D3   0x0003

Definition at line 901 of file rtl81x9reg.h.

◆ RL_PSTATE_MASK

#define RL_PSTATE_MASK   0x0003

Definition at line 897 of file rtl81x9reg.h.

◆ RL_RDESC_CMD_BUFLEN

#define RL_RDESC_CMD_BUFLEN   0x00001FFF

Definition at line 531 of file rtl81x9reg.h.

◆ RL_RDESC_CMD_EOR

#define RL_RDESC_CMD_EOR   0x40000000

Definition at line 529 of file rtl81x9reg.h.

◆ RL_RDESC_CMD_OWN

#define RL_RDESC_CMD_OWN   0x80000000

Definition at line 530 of file rtl81x9reg.h.

◆ RL_RDESC_STAT_BCAST

#define RL_RDESC_STAT_BCAST   0x01000000 /* broadcast pkt received */

Definition at line 540 of file rtl81x9reg.h.

◆ RL_RDESC_STAT_BUFOFLOW

#define RL_RDESC_STAT_BUFOFLOW   0x00800000 /* out of buffer space */

Definition at line 541 of file rtl81x9reg.h.

◆ RL_RDESC_STAT_CRCERR

#define RL_RDESC_STAT_CRCERR   0x00040000 /* CRC error */

Definition at line 546 of file rtl81x9reg.h.

◆ RL_RDESC_STAT_EOF

#define RL_RDESC_STAT_EOF   0x10000000

Definition at line 536 of file rtl81x9reg.h.

◆ RL_RDESC_STAT_EOR

#define RL_RDESC_STAT_EOR   0x40000000

Definition at line 534 of file rtl81x9reg.h.

◆ RL_RDESC_STAT_ERRS

#define RL_RDESC_STAT_ERRS
Value:
RL_RDESC_STAT_CRCERR)

Definition at line 553 of file rtl81x9reg.h.

◆ RL_RDESC_STAT_FIFOOFLOW

#define RL_RDESC_STAT_FIFOOFLOW   0x00400000 /* FIFO overrun */

Definition at line 542 of file rtl81x9reg.h.

◆ RL_RDESC_STAT_FRAGLEN

#define RL_RDESC_STAT_FRAGLEN   0x00001FFF /* RX'ed frame/frag len */

Definition at line 551 of file rtl81x9reg.h.

◆ RL_RDESC_STAT_FRALIGN

#define RL_RDESC_STAT_FRALIGN   0x08000000 /* frame alignment error */

Definition at line 537 of file rtl81x9reg.h.

◆ RL_RDESC_STAT_GFRAGLEN

#define RL_RDESC_STAT_GFRAGLEN   0x00003FFF /* RX'ed frame/frag len */

Definition at line 552 of file rtl81x9reg.h.

◆ RL_RDESC_STAT_GIANT

#define RL_RDESC_STAT_GIANT   0x00200000 /* pkt > 4096 bytes */

Definition at line 543 of file rtl81x9reg.h.

◆ RL_RDESC_STAT_IPSUMBAD

#define RL_RDESC_STAT_IPSUMBAD   0x00008000 /* IP header checksum bad */

Definition at line 548 of file rtl81x9reg.h.

◆ RL_RDESC_STAT_MCAST

#define RL_RDESC_STAT_MCAST   0x04000000 /* multicast pkt received */

Definition at line 538 of file rtl81x9reg.h.

◆ RL_RDESC_STAT_OWN

#define RL_RDESC_STAT_OWN   0x80000000

Definition at line 533 of file rtl81x9reg.h.

◆ RL_RDESC_STAT_PROTOID

#define RL_RDESC_STAT_PROTOID   0x00030000 /* Protocol type */

Definition at line 547 of file rtl81x9reg.h.

◆ RL_RDESC_STAT_RUNT

#define RL_RDESC_STAT_RUNT   0x00080000 /* runt packet received */

Definition at line 545 of file rtl81x9reg.h.

◆ RL_RDESC_STAT_RXERRSUM

#define RL_RDESC_STAT_RXERRSUM   0x00100000 /* RX error summary */

Definition at line 544 of file rtl81x9reg.h.

◆ RL_RDESC_STAT_SOF

#define RL_RDESC_STAT_SOF   0x20000000

Definition at line 535 of file rtl81x9reg.h.

◆ RL_RDESC_STAT_TCPSUMBAD

#define RL_RDESC_STAT_TCPSUMBAD   0x00002000 /* TCP checksum bad */

Definition at line 550 of file rtl81x9reg.h.

◆ RL_RDESC_STAT_UCAST

#define RL_RDESC_STAT_UCAST   0x02000000 /* unicast pkt received */

Definition at line 539 of file rtl81x9reg.h.

◆ RL_RDESC_STAT_UDPSUMBAD

#define RL_RDESC_STAT_UDPSUMBAD   0x00004000 /* UDP checksum bad */

Definition at line 549 of file rtl81x9reg.h.

◆ RL_RDESC_VLANCTL_DATA

#define RL_RDESC_VLANCTL_DATA   0x0000FFFF /* TAG data */

Definition at line 557 of file rtl81x9reg.h.

◆ RL_RDESC_VLANCTL_TAG

#define RL_RDESC_VLANCTL_TAG
Value:
0x00010000 /* VLAN tag available
(rl_vlandata valid)*/

Definition at line 556 of file rtl81x9reg.h.

◆ RL_RING_ALIGN

#define RL_RING_ALIGN   256

Definition at line 599 of file rtl81x9reg.h.

◆ RL_RX_BUF_SZ

#define RL_RX_BUF_SZ   RL_RXBUF_64

Definition at line 449 of file rtl81x9reg.h.

◆ RL_RX_DESC_CNT

#define RL_RX_DESC_CNT   64

Definition at line 590 of file rtl81x9reg.h.

◆ RL_RX_DMAMEM_SZ

#define RL_RX_DMAMEM_SZ   (RL_RX_LIST_SZ + RL_IP4CSUMTX_PADLEN)

Definition at line 761 of file rtl81x9reg.h.

◆ RL_RX_EARLY_BYTES

#define RL_RX_EARLY_BYTES   0x0034 /* RX early byte count */

Definition at line 71 of file rtl81x9reg.h.

◆ RL_RX_EARLY_STAT

#define RL_RX_EARLY_STAT   0x0036 /* RX early status */

Definition at line 72 of file rtl81x9reg.h.

◆ RL_RX_ER

#define RL_RX_ER   0x0072 /* RX_ER counter */

Definition at line 105 of file rtl81x9reg.h.

◆ RL_RX_FIFOTHRESH

#define RL_RX_FIFOTHRESH   RL_RXFIFO_256BYTES

Definition at line 455 of file rtl81x9reg.h.

◆ RL_RX_LIST_SZ

#define RL_RX_LIST_SZ   (RL_RX_DESC_CNT * sizeof(struct rl_desc))

Definition at line 598 of file rtl81x9reg.h.

◆ RL_RX_MAXDMA

#define RL_RX_MAXDMA   RL_RXDMA_UNLIMITED

Definition at line 456 of file rtl81x9reg.h.

◆ RL_RXADDR

#define RL_RXADDR   0x0030 /* RX ring start address */

Definition at line 70 of file rtl81x9reg.h.

◆ RL_RXBUF_16

#define RL_RXBUF_16   0x00000800

Definition at line 263 of file rtl81x9reg.h.

◆ RL_RXBUF_32

#define RL_RXBUF_32   0x00001000

Definition at line 264 of file rtl81x9reg.h.

◆ RL_RXBUF_64

#define RL_RXBUF_64   0x00001800

Definition at line 265 of file rtl81x9reg.h.

◆ RL_RXBUF_8

#define RL_RXBUF_8   0x00000000

Definition at line 262 of file rtl81x9reg.h.

◆ RL_RXBUFLEN

#define RL_RXBUFLEN   (1 << ((RL_RX_BUF_SZ >> 11) + 13))

Definition at line 450 of file rtl81x9reg.h.

◆ RL_RXCFG

#define RL_RXCFG   0x0044 /* receive config */

Definition at line 79 of file rtl81x9reg.h.

◆ RL_RXCFG_BURSZ

#define RL_RXCFG_BURSZ   0x00001800

Definition at line 249 of file rtl81x9reg.h.

◆ RL_RXCFG_CONFIG

#define RL_RXCFG_CONFIG   (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ)

Definition at line 459 of file rtl81x9reg.h.

◆ RL_RXCFG_EARLYTHRESH

#define RL_RXCFG_EARLYTHRESH   0x07000000

Definition at line 251 of file rtl81x9reg.h.

◆ RL_RXCFG_FIFOTHRESH

#define RL_RXCFG_FIFOTHRESH   0x0000E000

Definition at line 250 of file rtl81x9reg.h.

◆ RL_RXCFG_MAXDMA

#define RL_RXCFG_MAXDMA   0x00000700

Definition at line 248 of file rtl81x9reg.h.

◆ RL_RXCFG_RX_ALLPHYS

#define RL_RXCFG_RX_ALLPHYS   0x00000001 /* accept all nodes */

Definition at line 241 of file rtl81x9reg.h.

◆ RL_RXCFG_RX_BROAD

#define RL_RXCFG_RX_BROAD   0x00000008 /* accept all broadcast */

Definition at line 244 of file rtl81x9reg.h.

◆ RL_RXCFG_RX_ERRPKT

#define RL_RXCFG_RX_ERRPKT   0x00000020

Definition at line 246 of file rtl81x9reg.h.

◆ RL_RXCFG_RX_INDIV

#define RL_RXCFG_RX_INDIV   0x00000002 /* match filter */

Definition at line 242 of file rtl81x9reg.h.

◆ RL_RXCFG_RX_MULTI

#define RL_RXCFG_RX_MULTI   0x00000004 /* accept all multicast */

Definition at line 243 of file rtl81x9reg.h.

◆ RL_RXCFG_RX_RUNT

#define RL_RXCFG_RX_RUNT   0x00000010

Definition at line 245 of file rtl81x9reg.h.

◆ RL_RXCFG_WRAP

#define RL_RXCFG_WRAP   0x00000080

Definition at line 247 of file rtl81x9reg.h.

◆ RL_RXDESCSYNC

#define RL_RXDESCSYNC (   sc,
  idx,
  ops 
)
Value:
bus_dmamap_sync((sc)->sc_dmat, \
(sc)->rl_ldata.rl_rx_list_map, \
sizeof(struct rl_desc) * (idx), \
sizeof(struct rl_desc), \
(ops))

Definition at line 626 of file rtl81x9reg.h.

◆ RL_RXDMA_1024BYTES

#define RL_RXDMA_1024BYTES   0x00000600

Definition at line 259 of file rtl81x9reg.h.

◆ RL_RXDMA_128BYTES

#define RL_RXDMA_128BYTES   0x00000300

Definition at line 256 of file rtl81x9reg.h.

◆ RL_RXDMA_16BYTES

#define RL_RXDMA_16BYTES   0x00000000

Definition at line 253 of file rtl81x9reg.h.

◆ RL_RXDMA_256BYTES

#define RL_RXDMA_256BYTES   0x00000400

Definition at line 257 of file rtl81x9reg.h.

◆ RL_RXDMA_32BYTES

#define RL_RXDMA_32BYTES   0x00000100

Definition at line 254 of file rtl81x9reg.h.

◆ RL_RXDMA_512BYTES

#define RL_RXDMA_512BYTES   0x00000500

Definition at line 258 of file rtl81x9reg.h.

◆ RL_RXDMA_64BYTES

#define RL_RXDMA_64BYTES   0x00000200

Definition at line 255 of file rtl81x9reg.h.

◆ RL_RXDMA_UNLIMITED

#define RL_RXDMA_UNLIMITED   0x00000700

Definition at line 260 of file rtl81x9reg.h.

◆ RL_RXFIFO_1024BYTES

#define RL_RXFIFO_1024BYTES   0x0000C000

Definition at line 273 of file rtl81x9reg.h.

◆ RL_RXFIFO_128BYTES

#define RL_RXFIFO_128BYTES   0x00006000

Definition at line 270 of file rtl81x9reg.h.

◆ RL_RXFIFO_16BYTES

#define RL_RXFIFO_16BYTES   0x00000000

Definition at line 267 of file rtl81x9reg.h.

◆ RL_RXFIFO_256BYTES

#define RL_RXFIFO_256BYTES   0x00008000

Definition at line 271 of file rtl81x9reg.h.

◆ RL_RXFIFO_32BYTES

#define RL_RXFIFO_32BYTES   0x00002000

Definition at line 268 of file rtl81x9reg.h.

◆ RL_RXFIFO_512BYTES

#define RL_RXFIFO_512BYTES   0x0000A000

Definition at line 272 of file rtl81x9reg.h.

◆ RL_RXFIFO_64BYTES

#define RL_RXFIFO_64BYTES   0x00004000

Definition at line 269 of file rtl81x9reg.h.

◆ RL_RXFIFO_NOTHRESH

#define RL_RXFIFO_NOTHRESH   0x0000E000

Definition at line 274 of file rtl81x9reg.h.

◆ RL_RXLIST_ADDR_HI

#define RL_RXLIST_ADDR_HI   0x00E8 /* 64 bits, 256 byte alignment */

Definition at line 124 of file rtl81x9reg.h.

◆ RL_RXLIST_ADDR_LO

#define RL_RXLIST_ADDR_LO   0x00E4 /* 64 bits, 256 byte alignment */

Definition at line 123 of file rtl81x9reg.h.

◆ RL_RXSTAT_ALIGNERR

#define RL_RXSTAT_ALIGNERR   0x00000002

Definition at line 281 of file rtl81x9reg.h.

◆ RL_RXSTAT_BADSYM

#define RL_RXSTAT_BADSYM   0x00000020

Definition at line 285 of file rtl81x9reg.h.

◆ RL_RXSTAT_BROAD

#define RL_RXSTAT_BROAD   0x00002000

Definition at line 286 of file rtl81x9reg.h.

◆ RL_RXSTAT_CRCERR

#define RL_RXSTAT_CRCERR   0x00000004

Definition at line 282 of file rtl81x9reg.h.

◆ RL_RXSTAT_GIANT

#define RL_RXSTAT_GIANT   0x00000008

Definition at line 283 of file rtl81x9reg.h.

◆ RL_RXSTAT_INDIV

#define RL_RXSTAT_INDIV   0x00004000

Definition at line 287 of file rtl81x9reg.h.

◆ RL_RXSTAT_LENMASK

#define RL_RXSTAT_LENMASK   0xFFFF0000

Definition at line 289 of file rtl81x9reg.h.

◆ RL_RXSTAT_MULTI

#define RL_RXSTAT_MULTI   0x00008000

Definition at line 288 of file rtl81x9reg.h.

◆ RL_RXSTAT_RUNT

#define RL_RXSTAT_RUNT   0x00000010

Definition at line 284 of file rtl81x9reg.h.

◆ RL_RXSTAT_RXOK

#define RL_RXSTAT_RXOK   0x00000001

Definition at line 280 of file rtl81x9reg.h.

◆ RL_RXSTAT_UNFINISHED

#define RL_RXSTAT_UNFINISHED   0xFFF0 /* DMA still in progress */

Definition at line 291 of file rtl81x9reg.h.

◆ RL_TBI_ANAR

#define RL_TBI_ANAR   0x0068

Definition at line 133 of file rtl81x9reg.h.

◆ RL_TBI_LPAR

#define RL_TBI_LPAR   0x006A

Definition at line 134 of file rtl81x9reg.h.

◆ RL_TBICSR

#define RL_TBICSR   0x0064

Definition at line 132 of file rtl81x9reg.h.

◆ RL_TCPPKT

#define RL_TCPPKT (   x)
Value:
(((x) & RL_RDESC_STAT_PROTOID) == \
RL_PROTOID_TCPIP)

Definition at line 563 of file rtl81x9reg.h.

◆ RL_TDESC_CMD_EOF

#define RL_TDESC_CMD_EOF   0x10000000 /* end of frame marker */

Definition at line 504 of file rtl81x9reg.h.

◆ RL_TDESC_CMD_EOR

#define RL_TDESC_CMD_EOR   0x40000000 /* end of ring marker */

Definition at line 506 of file rtl81x9reg.h.

◆ RL_TDESC_CMD_FRAGLEN

#define RL_TDESC_CMD_FRAGLEN   0x0000FFFF

Definition at line 498 of file rtl81x9reg.h.

◆ RL_TDESC_CMD_IPCSUM

#define RL_TDESC_CMD_IPCSUM   0x00040000 /* IP header checksum enable */

Definition at line 501 of file rtl81x9reg.h.

◆ RL_TDESC_CMD_LGSEND

#define RL_TDESC_CMD_LGSEND   0x08000000 /* TCP large send enb */

Definition at line 503 of file rtl81x9reg.h.

◆ RL_TDESC_CMD_MSSVAL

#define RL_TDESC_CMD_MSSVAL   0x07FF0000 /* Large send MSS value */

Definition at line 502 of file rtl81x9reg.h.

◆ RL_TDESC_CMD_OWN

#define RL_TDESC_CMD_OWN   0x80000000 /* chip owns descriptor */

Definition at line 507 of file rtl81x9reg.h.

◆ RL_TDESC_CMD_SOF

#define RL_TDESC_CMD_SOF   0x20000000 /* start of frame marker */

Definition at line 505 of file rtl81x9reg.h.

◆ RL_TDESC_CMD_TCPCSUM

#define RL_TDESC_CMD_TCPCSUM   0x00010000 /* TCP checksum enable */

Definition at line 499 of file rtl81x9reg.h.

◆ RL_TDESC_CMD_UDPCSUM

#define RL_TDESC_CMD_UDPCSUM   0x00020000 /* UDP checksum enable */

Definition at line 500 of file rtl81x9reg.h.

◆ RL_TDESC_STAT_COLCNT

#define RL_TDESC_STAT_COLCNT   0x000F0000 /* collision count */

Definition at line 517 of file rtl81x9reg.h.

◆ RL_TDESC_STAT_EXCESSCOL

#define RL_TDESC_STAT_EXCESSCOL   0x00100000 /* excessive collisions */

Definition at line 518 of file rtl81x9reg.h.

◆ RL_TDESC_STAT_LINKFAIL

#define RL_TDESC_STAT_LINKFAIL   0x00200000 /* link faulure */

Definition at line 519 of file rtl81x9reg.h.

◆ RL_TDESC_STAT_OWINCOL

#define RL_TDESC_STAT_OWINCOL   0x00400000 /* out-of-window collision */

Definition at line 520 of file rtl81x9reg.h.

◆ RL_TDESC_STAT_OWN

#define RL_TDESC_STAT_OWN   0x80000000

Definition at line 523 of file rtl81x9reg.h.

◆ RL_TDESC_STAT_TXERRSUM

#define RL_TDESC_STAT_TXERRSUM   0x00800000 /* transmit error summary */

Definition at line 521 of file rtl81x9reg.h.

◆ RL_TDESC_STAT_UNDERRUN

#define RL_TDESC_STAT_UNDERRUN   0x02000000 /* TX underrun occured */

Definition at line 522 of file rtl81x9reg.h.

◆ RL_TDESC_VLANCTL_DATA

#define RL_TDESC_VLANCTL_DATA   0x0000FFFF /* TAG data */

Definition at line 510 of file rtl81x9reg.h.

◆ RL_TDESC_VLANCTL_TAG

#define RL_TDESC_VLANCTL_TAG   0x00020000 /* Insert VLAN tag */

Definition at line 509 of file rtl81x9reg.h.

◆ RL_TIMEOUT

#define RL_TIMEOUT   1000

Definition at line 808 of file rtl81x9reg.h.

◆ RL_TIMERCNT

#define RL_TIMERCNT   0x0048 /* timer count register */

Definition at line 80 of file rtl81x9reg.h.

◆ RL_TIMERINT

#define RL_TIMERINT   0x0054 /* interrupt on timer expire */

Definition at line 120 of file rtl81x9reg.h.

◆ RL_TIMERINT_8169

#define RL_TIMERINT_8169   0x0058 /* different offset than 8139 */

Definition at line 130 of file rtl81x9reg.h.

◆ RL_TX_DESC_CNT

#define RL_TX_DESC_CNT (   sc)    ((sc)->rl_ldata.rl_tx_desc_cnt)

Definition at line 609 of file rtl81x9reg.h.

◆ RL_TX_DESC_CNT_8139

#define RL_TX_DESC_CNT_8139   64

Definition at line 591 of file rtl81x9reg.h.

◆ RL_TX_DESC_CNT_8169

#define RL_TX_DESC_CNT_8169   1024

Definition at line 592 of file rtl81x9reg.h.

◆ RL_TX_LIST_CNT

#define RL_TX_LIST_CNT   4

Definition at line 451 of file rtl81x9reg.h.

◆ RL_TX_LIST_SZ

#define RL_TX_LIST_SZ (   sc)    (RL_TX_DESC_CNT(sc) * sizeof(struct rl_desc))

Definition at line 611 of file rtl81x9reg.h.

◆ RL_TX_MAXDMA

#define RL_TX_MAXDMA   RL_TXDMA_2048BYTES

Definition at line 457 of file rtl81x9reg.h.

◆ RL_TX_QLEN

#define RL_TX_QLEN   64

Definition at line 594 of file rtl81x9reg.h.

◆ RL_TX_THRESH_INIT

#define RL_TX_THRESH_INIT   96

Definition at line 454 of file rtl81x9reg.h.

◆ RL_TXADDR0

#define RL_TXADDR0   0x0020 /* address of TX descriptor 0 */

Definition at line 65 of file rtl81x9reg.h.

◆ RL_TXADDR1

#define RL_TXADDR1   0x0024 /* address of TX descriptor 1 */

Definition at line 66 of file rtl81x9reg.h.

◆ RL_TXADDR2

#define RL_TXADDR2   0x0028 /* address of TX descriptor 2 */

Definition at line 67 of file rtl81x9reg.h.

◆ RL_TXADDR3

#define RL_TXADDR3   0x002C /* address of TX descriptor 3 */

Definition at line 68 of file rtl81x9reg.h.

◆ RL_TXCFG

#define RL_TXCFG   0x0040 /* transmit config */

Definition at line 78 of file rtl81x9reg.h.

◆ RL_TXCFG_CLRABRT

#define RL_TXCFG_CLRABRT   0x00000001 /* retransmit aborted pkt */

Definition at line 141 of file rtl81x9reg.h.

◆ RL_TXCFG_CONFIG

#define RL_TXCFG_CONFIG   (RL_TXCFG_IFG|RL_TX_MAXDMA)

Definition at line 460 of file rtl81x9reg.h.

◆ RL_TXCFG_CRCAPPEND

#define RL_TXCFG_CRCAPPEND   0x00010000 /* CRC append (0 = yes) */

Definition at line 143 of file rtl81x9reg.h.

◆ RL_TXCFG_HWREV

#define RL_TXCFG_HWREV   0x7C800000

Definition at line 147 of file rtl81x9reg.h.

◆ RL_TXCFG_IFG

#define RL_TXCFG_IFG   0x03000000 /* interframe gap */

Definition at line 146 of file rtl81x9reg.h.

◆ RL_TXCFG_IFG2

#define RL_TXCFG_IFG2   0x00080000 /* 8169 only */

Definition at line 145 of file rtl81x9reg.h.

◆ RL_TXCFG_LOOPBKTST

#define RL_TXCFG_LOOPBKTST   0x00060000 /* loopback test */

Definition at line 144 of file rtl81x9reg.h.

◆ RL_TXCFG_MAXDMA

#define RL_TXCFG_MAXDMA   0x00000700 /* max DMA burst size */

Definition at line 142 of file rtl81x9reg.h.

◆ RL_TXDESCSYNC

#define RL_TXDESCSYNC (   sc,
  idx,
  ops 
)
Value:
bus_dmamap_sync((sc)->sc_dmat, \
(sc)->rl_ldata.rl_tx_list_map, \
sizeof(struct rl_desc) * (idx), \
sizeof(struct rl_desc), \
(ops))

Definition at line 620 of file rtl81x9reg.h.

◆ RL_TXDMA_1024BYTES

#define RL_TXDMA_1024BYTES   0x00000600

Definition at line 182 of file rtl81x9reg.h.

◆ RL_TXDMA_128BYTES

#define RL_TXDMA_128BYTES   0x00000300

Definition at line 179 of file rtl81x9reg.h.

◆ RL_TXDMA_16BYTES

#define RL_TXDMA_16BYTES   0x00000000

Definition at line 176 of file rtl81x9reg.h.

◆ RL_TXDMA_2048BYTES

#define RL_TXDMA_2048BYTES   0x00000700

Definition at line 183 of file rtl81x9reg.h.

◆ RL_TXDMA_256BYTES

#define RL_TXDMA_256BYTES   0x00000400

Definition at line 180 of file rtl81x9reg.h.

◆ RL_TXDMA_32BYTES

#define RL_TXDMA_32BYTES   0x00000100

Definition at line 177 of file rtl81x9reg.h.

◆ RL_TXDMA_512BYTES

#define RL_TXDMA_512BYTES   0x00000500

Definition at line 181 of file rtl81x9reg.h.

◆ RL_TXDMA_64BYTES

#define RL_TXDMA_64BYTES   0x00000200

Definition at line 178 of file rtl81x9reg.h.

◆ RL_TXLIST_ADDR_HI

#define RL_TXLIST_ADDR_HI   0x0024 /* 64 bits, 256 byte alignment */

Definition at line 116 of file rtl81x9reg.h.

◆ RL_TXLIST_ADDR_HPRIO_HI

#define RL_TXLIST_ADDR_HPRIO_HI   0x002C /* 64 bits, 256 byte aligned */

Definition at line 118 of file rtl81x9reg.h.

◆ RL_TXLIST_ADDR_HPRIO_LO

#define RL_TXLIST_ADDR_HPRIO_LO   0x0028 /* 64 bits, 256 byte aligned */

Definition at line 117 of file rtl81x9reg.h.

◆ RL_TXLIST_ADDR_LO

#define RL_TXLIST_ADDR_LO   0x0020 /* 64 bits, 256 byte alignment */

Definition at line 115 of file rtl81x9reg.h.

◆ RL_TXPADDADDR

#define RL_TXPADDADDR (   sc)    ((sc)->rl_ldata.rl_rx_list_map->dm_segs[0].ds_addr + RL_TXPADOFF)

Definition at line 763 of file rtl81x9reg.h.

◆ RL_TXPADOFF

#define RL_TXPADOFF   RL_RX_LIST_SZ

Definition at line 762 of file rtl81x9reg.h.

◆ RL_TXSTART

#define RL_TXSTART   0x00D9 /* 8 bits */

Definition at line 121 of file rtl81x9reg.h.

◆ RL_TXSTART_HPRIO_START

#define RL_TXSTART_HPRIO_START   0x80 /* start hi prio queue transmit */

Definition at line 386 of file rtl81x9reg.h.

◆ RL_TXSTART_START

#define RL_TXSTART_START   0x40 /* start normal queue transmit */

Definition at line 385 of file rtl81x9reg.h.

◆ RL_TXSTART_SWI

#define RL_TXSTART_SWI   0x01 /* generate TX interrupt */

Definition at line 384 of file rtl81x9reg.h.

◆ RL_TXSTAT0

#define RL_TXSTAT0   0x0010 /* status of TX descriptor 0 */

Definition at line 60 of file rtl81x9reg.h.

◆ RL_TXSTAT1

#define RL_TXSTAT1   0x0014 /* status of TX descriptor 1 */

Definition at line 61 of file rtl81x9reg.h.

◆ RL_TXSTAT2

#define RL_TXSTAT2   0x0018 /* status of TX descriptor 2 */

Definition at line 62 of file rtl81x9reg.h.

◆ RL_TXSTAT3

#define RL_TXSTAT3   0x001C /* status of TX descriptor 3 */

Definition at line 63 of file rtl81x9reg.h.

◆ RL_TXSTAT_ALL

#define RL_TXSTAT_ALL   0x0060 /* TX status of all descriptors */

Definition at line 93 of file rtl81x9reg.h.

◆ RL_TXSTAT_CARR_HBEAT

#define RL_TXSTAT_CARR_HBEAT   0x10000000

Definition at line 194 of file rtl81x9reg.h.

◆ RL_TXSTAT_CARRLOSS

#define RL_TXSTAT_CARRLOSS   0x80000000

Definition at line 197 of file rtl81x9reg.h.

◆ RL_TXSTAT_COLLCNT

#define RL_TXSTAT_COLLCNT   0x0F000000

Definition at line 193 of file rtl81x9reg.h.

◆ RL_TXSTAT_EARLY_THRESH

#define RL_TXSTAT_EARLY_THRESH   0x003F0000

Definition at line 192 of file rtl81x9reg.h.

◆ RL_TXSTAT_LENMASK

#define RL_TXSTAT_LENMASK   0x00001FFF

Definition at line 188 of file rtl81x9reg.h.

◆ RL_TXSTAT_OUTOFWIN

#define RL_TXSTAT_OUTOFWIN   0x20000000

Definition at line 195 of file rtl81x9reg.h.

◆ RL_TXSTAT_OWN

#define RL_TXSTAT_OWN   0x00002000

Definition at line 189 of file rtl81x9reg.h.

◆ RL_TXSTAT_TX_OK

#define RL_TXSTAT_TX_OK   0x00008000

Definition at line 191 of file rtl81x9reg.h.

◆ RL_TXSTAT_TX_UNDERRUN

#define RL_TXSTAT_TX_UNDERRUN   0x00004000

Definition at line 190 of file rtl81x9reg.h.

◆ RL_TXSTAT_TXABRT

#define RL_TXSTAT_TXABRT   0x40000000

Definition at line 196 of file rtl81x9reg.h.

◆ RL_TXTHRESH

#define RL_TXTHRESH (   x)    ((x) << 11)

Definition at line 453 of file rtl81x9reg.h.

◆ RL_UDPPKT

#define RL_UDPPKT (   x)
Value:
(((x) & RL_RDESC_STAT_PROTOID) == \
RL_PROTOID_UDPIP)

Definition at line 565 of file rtl81x9reg.h.

◆ RL_UNKNOWN

#define RL_UNKNOWN   0

Definition at line 674 of file rtl81x9reg.h.

◆ RT_DEVICEID_8100

#define RT_DEVICEID_8100   0x8100

Definition at line 827 of file rtl81x9reg.h.

◆ RT_DEVICEID_8101E

#define RT_DEVICEID_8101E   0x8136

Definition at line 821 of file rtl81x9reg.h.

◆ RT_DEVICEID_8129

#define RT_DEVICEID_8129   0x8129

Definition at line 820 of file rtl81x9reg.h.

◆ RT_DEVICEID_8138

#define RT_DEVICEID_8138   0x8138

Definition at line 822 of file rtl81x9reg.h.

◆ RT_DEVICEID_8139

#define RT_DEVICEID_8139   0x8139

Definition at line 823 of file rtl81x9reg.h.

◆ RT_DEVICEID_8168

#define RT_DEVICEID_8168   0x8168

Definition at line 825 of file rtl81x9reg.h.

◆ RT_DEVICEID_8169

#define RT_DEVICEID_8169   0x8169

Definition at line 826 of file rtl81x9reg.h.

◆ RT_DEVICEID_8169SC

#define RT_DEVICEID_8169SC   0x8167

Definition at line 824 of file rtl81x9reg.h.

◆ RT_VENDORID

#define RT_VENDORID   0x10EC

Definition at line 815 of file rtl81x9reg.h.

RL_8169
#define RL_8169
Definition: rtl81x9reg.h:677
RL_ISR_RX_OK
#define RL_ISR_RX_OK
Definition: rtl81x9reg.h:201
RL_8139CPLUS
#define RL_8139CPLUS
Definition: rtl81x9reg.h:676
rl_type
Definition: rtl81x9reg.h:651
RL_ISR_RX_ERR
#define RL_ISR_RX_ERR
Definition: rtl81x9reg.h:202
RL_ISR_TX_ERR
#define RL_ISR_TX_ERR
Definition: rtl81x9reg.h:204
RL_ISR_FIFO_OFLOW
#define RL_ISR_FIFO_OFLOW
Definition: rtl81x9reg.h:208
rl_desc
Definition: rtl81x9reg.h:490
RL_ISR_TX_OK
#define RL_ISR_TX_OK
Definition: rtl81x9reg.h:203
RL_RDESC_STAT_GIANT
#define RL_RDESC_STAT_GIANT
Definition: rtl81x9reg.h:542
RL_RDESC_STAT_PROTOID
#define RL_RDESC_STAT_PROTOID
Definition: rtl81x9reg.h:546
RL_RDESC_STAT_RUNT
#define RL_RDESC_STAT_RUNT
Definition: rtl81x9reg.h:544
RL_ISR_SYSTEM_ERR
#define RL_ISR_SYSTEM_ERR
Definition: rtl81x9reg.h:214
RL_ISR_TIMEOUT_EXPIRED
#define RL_ISR_TIMEOUT_EXPIRED
Definition: rtl81x9reg.h:213
RL_ISR_PKT_UNDERRUN
#define RL_ISR_PKT_UNDERRUN
Definition: rtl81x9reg.h:206

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