armreg.h Source File
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59 #define PSR_FLAGS 0xf0000000
60 #define PSR_N_bit (1 << 31)
61 #define PSR_Z_bit (1 << 30)
62 #define PSR_C_bit (1 << 29)
63 #define PSR_V_bit (1 << 28)
65 #define PSR_Q_bit (1 << 27)
66 #define PSR_IT1_bit (1 << 26)
67 #define PSR_IT0_bit (1 << 25)
68 #define PSR_J_bit (1 << 24)
69 #define PSR_GE_bits (15 << 16)
70 #define PSR_IT7_bit (1 << 15)
71 #define PSR_IT6_bit (1 << 14)
72 #define PSR_IT5_bit (1 << 13)
73 #define PSR_IT4_bit (1 << 12)
74 #define PSR_IT3_bit (1 << 11)
75 #define PSR_IT2_bit (1 << 10)
76 #define PSR_E_BIT (1 << 9)
77 #define PSR_A_BIT (1 << 8)
79 #define I32_bit (1 << 7)
80 #define F32_bit (1 << 6)
81 #define IF32_bits (3 << 6)
83 #define PSR_T_bit (1 << 5)
85 #define PSR_MODE 0x0000001f
86 #define PSR_USR32_MODE 0x00000010
87 #define PSR_FIQ32_MODE 0x00000011
88 #define PSR_IRQ32_MODE 0x00000012
89 #define PSR_SVC32_MODE 0x00000013
90 #define PSR_MON32_MODE 0x00000016
91 #define PSR_ABT32_MODE 0x00000017
92 #define PSR_HYP32_MODE 0x0000001a
93 #define PSR_UND32_MODE 0x0000001b
94 #define PSR_SYS32_MODE 0x0000001f
95 #define PSR_32_MODE 0x00000010
97 #define R15_FLAGS 0xf0000000
98 #define R15_FLAG_N 0x80000000
99 #define R15_FLAG_Z 0x40000000
100 #define R15_FLAG_C 0x20000000
101 #define R15_FLAG_V 0x10000000
107 #define ARM_CP15_CPU_ID 0
110 #define ARM_ISA3_SYNCHPRIM_MASK 0x0000f000
111 #define ARM_ISA4_SYNCHPRIM_MASK 0x00f00000
112 #define ARM_ISA3_SYNCHPRIM_LDREX 0x10 // LDREX
113 #define ARM_ISA3_SYNCHPRIM_LDREXPLUS 0x13 // +CLREX/LDREXB/LDREXH
114 #define ARM_ISA3_SYNCHPRIM_LDREXD 0x20 // +LDREXD
115 #define ARM_PFR0_THUMBEE_MASK 0x0000f000
116 #define ARM_PFR1_GTIMER_MASK 0x000f0000
117 #define ARM_PFR1_VIRT_MASK 0x0000f000
118 #define ARM_PFR1_SEC_MASK 0x000000f0
121 #define ARM_MVFR0_ROUNDING_MASK 0xf0000000
122 #define ARM_MVFR0_SHORTVEC_MASK 0x0f000000
123 #define ARM_MVFR0_SQRT_MASK 0x00f00000
124 #define ARM_MVFR0_DIVIDE_MASK 0x000f0000
125 #define ARM_MVFR0_EXCEPT_MASK 0x0000f000
126 #define ARM_MVFR0_DFLOAT_MASK 0x00000f00
127 #define ARM_MVFR0_SFLOAT_MASK 0x000000f0
128 #define ARM_MVFR0_ASIMD_MASK 0x0000000f
129 #define ARM_MVFR1_ASIMD_FMACS_MASK 0xf0000000
130 #define ARM_MVFR1_VFP_HPFP_MASK 0x0f000000
131 #define ARM_MVFR1_ASIMD_HPFP_MASK 0x00f00000
132 #define ARM_MVFR1_ASIMD_SPFP_MASK 0x000f0000
133 #define ARM_MVFR1_ASIMD_INT_MASK 0x0000f000
134 #define ARM_MVFR1_ASIMD_LDST_MASK 0x00000f00
135 #define ARM_MVFR1_D_NAN_MASK 0x000000f0
136 #define ARM_MVFR1_FTZ_MASK 0x0000000f
139 #define ARM3_CP15_FLUSH 1
140 #define ARM3_CP15_CONTROL 2
141 #define ARM3_CP15_CACHEABLE 3
142 #define ARM3_CP15_UPDATEABLE 4
143 #define ARM3_CP15_DISRUPTIVE 5
146 #define ARM3_CTL_CACHE_ON 0x00000001
147 #define ARM3_CTL_SHARED 0x00000002
148 #define ARM3_CTL_MONITOR 0x00000004
187 #define CPU_CONTROL_MMU_ENABLE 0x00000001
188 #define CPU_CONTROL_AFLT_ENABLE 0x00000002
189 #define CPU_CONTROL_DC_ENABLE 0x00000004
190 #define CPU_CONTROL_WBUF_ENABLE 0x00000008
191 #define CPU_CONTROL_32BP_ENABLE 0x00000010
192 #define CPU_CONTROL_32BD_ENABLE 0x00000020
193 #define CPU_CONTROL_LABT_ENABLE 0x00000040
194 #define CPU_CONTROL_BEND_ENABLE 0x00000080
195 #define CPU_CONTROL_SYST_ENABLE 0x00000100
196 #define CPU_CONTROL_ROM_ENABLE 0x00000200
197 #define CPU_CONTROL_CPCLK 0x00000400
198 #define CPU_CONTROL_SWP_ENABLE 0x00000400
199 #define CPU_CONTROL_BPRD_ENABLE 0x00000800
200 #define CPU_CONTROL_IC_ENABLE 0x00001000
201 #define CPU_CONTROL_VECRELOC 0x00002000
202 #define CPU_CONTROL_ROUNDROBIN 0x00004000
203 #define CPU_CONTROL_V4COMPAT 0x00008000
204 #define CPU_CONTROL_HA_ENABLE 0x00020000
205 #define CPU_CONTROL_WXN_ENABLE 0x00080000
206 #define CPU_CONTROL_UWXN_ENABLE 0x00100000
207 #define CPU_CONTROL_FI_ENABLE 0x00200000
208 #define CPU_CONTROL_UNAL_ENABLE 0x00400000
209 #define CPU_CONTROL_XP_ENABLE 0x00800000
210 #define CPU_CONTROL_V_ENABLE 0x01000000
211 #define CPU_CONTROL_EX_BEND 0x02000000
212 #define CPU_CONTROL_NMFI 0x08000000
213 #define CPU_CONTROL_TR_ENABLE 0x10000000
214 #define CPU_CONTROL_AF_ENABLE 0x20000000
215 #define CPU_CONTROL_TE_ENABLE 0x40000000
217 #define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE
220 #define CPACR_V7_ASEDIS 0x80000000
221 #define CPACR_V7_D32DIS 0x40000000
222 #define CPACR_CPn(n) (3 << (2*n))
223 #define CPACR_NOACCESS 0
224 #define CPACR_PRIVED 1
225 #define CPACR_RESERVED 2
229 #define NSACR_SMP 0x00040000
230 #define NSACR_L2ERR 0x00020000
231 #define NSACR_ASEDIS 0x00008000
232 #define NSACR_D32DIS 0x00004000
233 #define NSACR_CPn(n) (1 << (n))
236 #define ARM11X6_AUXCTL_RS 0x00000001
237 #define ARM11X6_AUXCTL_DB 0x00000002
238 #define ARM11X6_AUXCTL_SB 0x00000004
239 #define ARM11X6_AUXCTL_TR 0x00000008
240 #define ARM11X6_AUXCTL_EX 0x00000010
241 #define ARM11X6_AUXCTL_RA 0x00000020
242 #define ARM11X6_AUXCTL_RV 0x00000040
243 #define ARM11X6_AUXCTL_CZ 0x00000080
246 #define ARM1136_AUXCTL_PFI 0x80000000
253 #define ARM1176_AUXCTL_PHD 0x10000000
254 #define ARM1176_AUXCTL_BFD 0x20000000
255 #define ARM1176_AUXCTL_FSD 0x40000000
256 #define ARM1176_AUXCTL_FIO 0x80000000
259 #define XSCALE_AUXCTL_K 0x00000001
260 #define XSCALE_AUXCTL_P 0x00000002
261 #define XSCALE_AUXCTL_MD_WB_RA 0x00000000
262 #define XSCALE_AUXCTL_MD_WB_RWA 0x00000010
263 #define XSCALE_AUXCTL_MD_WT 0x00000020
264 #define XSCALE_AUXCTL_MD_MASK 0x00000030
267 #define MPCORE_AUXCTL_RS 0x00000001
268 #define MPCORE_AUXCTL_DB 0x00000002
269 #define MPCORE_AUXCTL_SB 0x00000004
270 #define MPCORE_AUXCTL_F 0x00000008
271 #define MPCORE_AUXCTL_EX 0x00000010
272 #define MPCORE_AUXCTL_SA 0x00000020
275 #define PJ4B_AUXCTL_FW __BIT(0)
276 #define PJ4B_AUXCTL_SMPNAMP __BIT(6)
277 #define PJ4B_AUXCTL_L1PARITY __BIT(9)
280 #define PJ4B_AUXFMC0_L2EN __BIT(0)
281 #define PJ4B_AUXFMC0_SMPNAMP __BIT(1)
282 #define PJ4B_AUXFMC0_L1PARITY __BIT(2)
283 #define PJ4B_AUXFMC0_DCSLFD __BIT(2)
284 #define PJ4B_AUXFMC0_FW __BIT(8)
287 #define CORTEXA5_ACTLR_FW __BIT(0)
288 #define CORTEXA5_ACTLR_SMP __BIT(6)
289 #define CORTEXA5_ACTLR_EXCL __BIT(7)
292 #define CORTEXA7_ACTLR_L1ALIAS __BIT(0)
293 #define CORTEXA7_ACTLR_L2EN __BIT(1)
294 #define CORTEXA7_ACTLR_SMP __BIT(6)
297 #define CORTEXA8_ACTLR_L1ALIAS __BIT(0)
298 #define CORTEXA8_ACTLR_L2EN __BIT(1)
301 #define CORTEXA9_AUXCTL_FW 0x00000001
302 #define CORTEXA9_AUXCTL_L2PE 0x00000002
303 #define CORTEXA9_AUXCTL_L1PE 0x00000004
304 #define CORTEXA9_AUXCTL_WR_ZERO 0x00000008
305 #define CORTEXA9_AUXCTL_SMP 0x00000040
306 #define CORTEXA9_AUXCTL_EXCL 0x00000080
307 #define CORTEXA9_AUXCTL_ONEWAY 0x00000100
308 #define CORTEXA9_AUXCTL_PARITY 0x00000200
311 #define CORTEXA15_ACTLR_BTB __BIT(0)
312 #define CORTEXA15_ACTLR_SMP __BIT(6)
313 #define CORTEXA15_ACTLR_IOBEU __BIT(15)
314 #define CORTEXA15_ACTLR_SDEH __BIT(31)
317 #define FC_DCACHE_REPL_LOCK 0x80000000
318 #define FC_DCACHE_STREAM_EN 0x20000000
319 #define FC_WR_ALLOC_EN 0x10000000
320 #define FC_L2_PREF_DIS 0x01000000
321 #define FC_L2_INV_EVICT_LINE 0x00800000
322 #define FC_L2CACHE_EN 0x00400000
323 #define FC_ICACHE_REPL_LOCK 0x00080000
324 #define FC_GLOB_HIST_REG_EN 0x00040000
325 #define FC_BRANCH_TARG_BUF_DIS 0x00020000
326 #define FC_L1_PAR_ERR_EN 0x00010000
329 #define CPU_CT_FORMAT(x) (((x) >> 29) & 0x7)
330 #define CPU_CT_ISIZE(x) ((x) & 0xfff)
331 #define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff)
332 #define CPU_CT_S (1U << 24)
333 #define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf)
335 #define CPU_CT_CTYPE_WT 0
336 #define CPU_CT_CTYPE_WB1 1
337 #define CPU_CT_CTYPE_WB2 2
338 #define CPU_CT_CTYPE_WB6 6
339 #define CPU_CT_CTYPE_WB7 7
340 #define CPU_CT_CTYPE_WB14 14
342 #define CPU_CT_xSIZE_LEN(x) ((x) & 0x3)
343 #define CPU_CT_xSIZE_M (1U << 2)
344 #define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7)
345 #define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7)
346 #define CPU_CT_xSIZE_P (1U << 11)
349 #define CPU_CT4_ILINE(x) ((x) & 0xf)
350 #define CPU_CT4_DLINE(x) (((x) >> 16) & 0xf)
351 #define CPU_CT4_L1IPOLICY(x) (((x) >> 14) & 0x3)
352 #define CPU_CT4_L1_AIVIVT 1
353 #define CPU_CT4_L1_VIPT 2
354 #define CPU_CT4_L1_PIPT 3
355 #define CPU_CT4_ERG(x) (((x) >> 20) & 0xf)
356 #define CPU_CT4_CWG(x) (((x) >> 24) & 0xf)
359 #define CPU_CSID_CTYPE_WT 0x80000000
360 #define CPU_CSID_CTYPE_WB 0x40000000
361 #define CPU_CSID_CTYPE_RA 0x20000000
362 #define CPU_CSID_CTYPE_WA 0x10000000
363 #define CPU_CSID_NUMSETS(x) (((x) >> 13) & 0x7fff)
364 #define CPU_CSID_ASSOC(x) (((x) >> 3) & 0x1ff)
365 #define CPU_CSID_LEN(x) ((x) & 0x07)
368 #define CPU_CSSR_L2 0x00000002
369 #define CPU_CSSR_L1 0x00000000
370 #define CPU_CSSR_InD 0x00000001
374 #define FAULT_TYPE_MASK 0x0f
375 #define FAULT_USER 0x10
377 #define FAULT_WRTBUF_0 0x00
378 #define FAULT_WRTBUF_1 0x02
379 #define FAULT_BUSERR_0 0x04
380 #define FAULT_BUSERR_1 0x06
381 #define FAULT_BUSERR_2 0x08
382 #define FAULT_BUSERR_3 0x0a
383 #define FAULT_BUSTRNL1 0x0c
384 #define FAULT_BUSTRNL2 0x0e
385 #define FAULT_ALIGN_0 0x01
386 #define FAULT_ALIGN_1 0x03
387 #define FAULT_TRANS_S 0x05
388 #define FAULT_TRANS_P 0x07
389 #define FAULT_DOMAIN_S 0x09
390 #define FAULT_DOMAIN_P 0x0b
391 #define FAULT_PERM_S 0x0d
392 #define FAULT_PERM_P 0x0f
394 #define FAULT_LPAE 0x0200
395 #define FAULT_IMPRECISE 0x0400
396 #define FAULT_WRITE 0x0800
397 #define FAULT_EXT 0x1000
398 #define FAULT_CM 0x2000
403 #define ARM_VECTORS_LOW 0x00000000U
404 #define ARM_VECTORS_HIGH 0xffff0000U
418 #define INSN_COND_MASK 0xf0000000
419 #define INSN_COND_EQ 0
420 #define INSN_COND_NE 1
421 #define INSN_COND_CS 2
422 #define INSN_COND_CC 3
423 #define INSN_COND_MI 4
424 #define INSN_COND_PL 5
425 #define INSN_COND_VS 6
426 #define INSN_COND_VC 7
427 #define INSN_COND_HI 8
428 #define INSN_COND_LS 9
429 #define INSN_COND_GE 10
430 #define INSN_COND_LT 11
431 #define INSN_COND_GT 12
432 #define INSN_COND_LE 13
433 #define INSN_COND_AL 14
435 #define THUMB_INSN_SIZE 2
440 #define ARM11_PMCCTL_E __BIT(0)
441 #define ARM11_PMCCTL_P __BIT(1)
442 #define ARM11_PMCCTL_C __BIT(2)
443 #define ARM11_PMCCTL_D __BIT(3)
444 #define ARM11_PMCCTL_EC0 __BIT(4)
445 #define ARM11_PMCCTL_EC1 __BIT(5)
446 #define ARM11_PMCCTL_ECC __BIT(6)
447 #define ARM11_PMCCTL_SBZa __BIT(7)
448 #define ARM11_PMCCTL_CR0 __BIT(8)
449 #define ARM11_PMCCTL_CR1 __BIT(9)
450 #define ARM11_PMCCTL_CCR __BIT(10)
451 #define ARM11_PMCCTL_X __BIT(11)
452 #define ARM11_PMCCTL_EVT1 __BITS(19,12)
453 #define ARM11_PMCCTL_EVT0 __BITS(27,20)
454 #define ARM11_PMCCTL_SBZb __BITS(31,28)
455 #define ARM11_PMCCTL_SBZ \
456 (ARM11_PMCCTL_SBZa | ARM11_PMCCTL_SBZb)
458 #define ARM11_PMCEVT_ICACHE_MISS 0
459 #define ARM11_PMCEVT_ISTREAM_STALL 1
460 #define ARM11_PMCEVT_IUTLB_MISS 2
461 #define ARM11_PMCEVT_DUTLB_MISS 3
462 #define ARM11_PMCEVT_BRANCH 4
463 #define ARM11_PMCEVT_BRANCH_MISS 6
464 #define ARM11_PMCEVT_INST_EXEC 7
465 #define ARM11_PMCEVT_DCACHE_ACCESS0 9
466 #define ARM11_PMCEVT_DCACHE_ACCESS1 10
467 #define ARM11_PMCEVT_DCACHE_MISS 11
468 #define ARM11_PMCEVT_DCACHE_WRITEBACK 12
469 #define ARM11_PMCEVT_PC_CHANGE 13
470 #define ARM11_PMCEVT_TLB_MISS 15
471 #define ARM11_PMCEVT_DATA_ACCESS 16
472 #define ARM11_PMCEVT_LSU_STALL 17
473 #define ARM11_PMCEVT_WBUF_DRAIN 18
474 #define ARM11_PMCEVT_ETMEXTOUT0 32
475 #define ARM11_PMCEVT_ETMEXTOUT1 33
476 #define ARM11_PMCEVT_ETMEXTOUT 34
477 #define ARM11_PMCEVT_CALL_EXEC 35
478 #define ARM11_PMCEVT_RETURN_EXEC 36
479 #define ARM11_PMCEVT_RETURN_HIT 37
480 #define ARM11_PMCEVT_RETURN_MISS 38
481 #define ARM11_PMCEVT_CYCLE 255
484 #define CORTEX_CNTENS_C __BIT(31)
485 #define CORTEX_CNTENC_C __BIT(31)
486 #define CORTEX_CNTOFL_C __BIT(31)
489 #define L2CTRL_NUMCPU __BITS(25,24) // numcpus - 1
490 #define L2CTRL_ICPRES __BIT(23) // Interrupt Controller is present
493 #define TTBR_C __BIT(0)
494 #define TTBR_S __BIT(1)
495 #define TTBR_IMP __BIT(2)
496 #define TTBR_RGN_MASK __BITS(4,3)
497 #define TTBR_RGN_NC __SHIFTIN(0, TTBR_RGN_MASK)
498 #define TTBR_RGN_WBWA __SHIFTIN(1, TTBR_RGN_MASK)
499 #define TTBR_RGN_WT __SHIFTIN(2, TTBR_RGN_MASK)
500 #define TTBR_RGN_WBNWA __SHIFTIN(3, TTBR_RGN_MASK)
501 #define TTBR_NOS __BIT(5)
502 #define TTBR_IRGN_MASK (__BIT(6) | __BIT(0))
503 #define TTBR_IRGN_NC 0
504 #define TTBR_IRGN_WBWA __BIT(6)
505 #define TTBR_IRGN_WT __BIT(0)
506 #define TTBR_IRGN_WBNWA (__BIT(0) | __BIT(6))
509 #define TTBCR_S_EAE __BIT(31) // Extended Address Extension
510 #define TTBCR_S_PD1 __BIT(5) // Don't use TTBR1
511 #define TTBCR_S_PD0 __BIT(4) // Don't use TTBR0
512 #define TTBCR_S_N __BITS(2,0) // Width of base address in TTB0
514 #define TTBCR_L_EAE __BIT(31) // Extended Address Extension
515 #define TTBCR_L_SH1 __BITS(29,28) // TTBR1 Shareability
516 #define TTBCR_L_ORGN1 __BITS(27,26) // TTBR1 Outer cacheability
517 #define TTBCR_L_IRGN1 __BITS(25,24) // TTBR1 inner cacheability
518 #define TTBCR_L_EPD1 __BIT(23) // Don't use TTBR1
519 #define TTBCR_L_A1 __BIT(22) // ASID is in TTBR1
520 #define TTBCR_L_T1SZ __BITS(18,16) // TTBR1 size offset
521 #define TTBCR_L_SH0 __BITS(13,12) // TTBR0 Shareability
522 #define TTBCR_L_ORGN0 __BITS(11,10) // TTBR0 Outer cacheability
523 #define TTBCR_L_IRGN0 __BITS(9,8) // TTBR0 inner cacheability
524 #define TTBCR_L_EPD0 __BIT(7) // Don't use TTBR0
525 #define TTBCR_L_T0SZ __BITS(2,0) // TTBR0 size offset
527 #define NRRR_ORn(n) __BITS(17+2*(n),16+2*(n)) // Outer Cacheable mappings
528 #define NRRR_IRn(n) __BITS(1+2*(n),0+2*(n)) // Inner Cacheable mappings
529 #define NRRR_NC 0 // non-cacheable
530 #define NRRR_WB_WA 1 // write-back write-allocate
531 #define NRRR_WT 2 // write-through
532 #define NRRR_WB 3 // write-back
533 #define PRRR_NOSn(n) __BITS(24+2*(n))// Memory region is Inner Shareable
534 #define PRRR_NS1 __BIT(19) // Normal Shareable S=1 is Shareable
535 #define PRRR_NS0 __BIT(18) // Normal Shareable S=0 is Shareable
536 #define PRRR_DS1 __BIT(17) // Device Shareable S=1 is Shareable
537 #define PRRR_DS0 __BIT(16) // Device Shareable S=0 is Shareable
538 #define PRRR_TRn(n) __BITS(1+2*(n),0+2*(n))
539 #define PRRR_TR_STRONG 0 // Strongly Ordered
540 #define PRRR_TR_DEVICE 1 // Device
541 #define PRRR_TR_NORMAL 2 // Normal Memory
544 #define MPIDR_MP __BIT(31)
545 #define MPIDR_U __BIT(30)
546 #define MPIDR_MT __BIT(24)
547 #define MPIDR_AFF2 __BITS(23,16)
548 #define MPIDR_AFF1 __BITS(15,8)
549 #define MPIDR_AFF0 __BITS(7,0)
552 #define CORTEXA9_MPIDR_MP MPIDR_MP
553 #define CORTEXA9_MPIDR_U MPIDR_U
554 #define CORTEXA9_MPIDR_CLID __BITS(11,8)
555 #define CORTEXA9_MPIDR_CPUID __BITS(0,1)
558 #define PJ4B_MPIDR_MP MPIDR_MP
559 #define PJ4B_MPIDR_U MPIDR_U
560 #define PJ4B_MPIDR_MT MPIDR_MT
561 #define PJ4B_MPIDR_CLID __BITS(11,8)
562 #define PJ4B_MPIDR_CPUID __BITS(0,3)
565 #define CNTCTL_ISTATUS __BIT(2) // Interrupt is pending
566 #define CNTCTL_IMASK __BIT(1) // Mask Interrupt
567 #define CNTCTL_ENABLE __BIT(0) // Timer Enabled
569 #define CNTKCTL_PL0PTEN __BIT(9)
570 #define CNTKCTL_PL0VTEN __BIT(8)
571 #define CNTKCTL_EVNTI __BITS(7,4)
572 #define CNTKCTL_EVNTDIR __BIT(3)
573 #define CNTKCTL_EVNTEN __BIT(2)
574 #define CNTKCTL_PL0VCTEN __BIT(1)
575 #define CNTKCTL_PL0PCTEN __BIT(0)
578 #define CNTHCTL_EVNTI __BITS(7,4)
579 #define CNTHCTL_EVNTDIR __BIT(3)
580 #define CNTHCTL_EVNTEN __BIT(2)
581 #define CNTHCTL_PL1PCEN __BIT(1)
582 #define CNTHCTL_PL1PCTEN __BIT(0)
584 #define ARM_A5_TLBDATA_DOM __BITS(62,59)
585 #define ARM_A5_TLBDATA_AP __BITS(58,56)
586 #define ARM_A5_TLBDATA_NS_WALK __BIT(55)
587 #define ARM_A5_TLBDATA_NS_PAGE __BIT(54)
588 #define ARM_A5_TLBDATA_XN __BIT(53)
589 #define ARM_A5_TLBDATA_TEX __BITS(52,50)
590 #define ARM_A5_TLBDATA_B __BIT(49)
591 #define ARM_A5_TLBDATA_C __BIT(48)
592 #define ARM_A5_TLBDATA_S __BIT(47)
593 #define ARM_A5_TLBDATA_ASID __BITS(46,39)
594 #define ARM_A5_TLBDATA_SIZE __BITS(38,37)
595 #define ARM_A5_TLBDATA_SIZE_4KB 0
596 #define ARM_A5_TLBDATA_SIZE_16KB 1
597 #define ARM_A5_TLBDATA_SIZE_1MB 2
598 #define ARM_A5_TLBDATA_SIZE_16MB 3
599 #define ARM_A5_TLBDATA_VA __BITS(36,22)
600 #define ARM_A5_TLBDATA_PA __BITS(21,2)
601 #define ARM_A5_TLBDATA_nG __BIT(1)
602 #define ARM_A5_TLBDATA_VALID __BIT(0)
604 #define ARM_A7_TLBDATA2_S2_LEVEL __BITS(85-64,84-64)
605 #define ARM_A7_TLBDATA2_S1_SIZE __BITS(83-64,82-64)
606 #define ARM_A7_TLBDATA2_S1_SIZE_4KB 0
607 #define ARM_A7_TLBDATA2_S1_SIZE_64KB 1
608 #define ARM_A7_TLBDATA2_S1_SIZE_1MB 2
609 #define ARM_A7_TLBDATA2_S1_SIZE_16MB 3
610 #define ARM_A7_TLBDATA2_DOM __BITS(81-64,78-64)
611 #define ARM_A7_TLBDATA2_IS __BITS(77-64,76-64)
612 #define ARM_A7_TLBDATA2_IS_NC 0
613 #define ARM_A7_TLBDATA2_IS_WB_WA 1
614 #define ARM_A7_TLBDATA2_IS_WT 2
615 #define ARM_A7_TLBDATA2_IS_DSO 3
616 #define ARM_A7_TLBDATA2_S2OVR __BIT(75-64)
617 #define ARM_A7_TLBDATA2_SDO_MT __BITS(74-64,72-64)
618 #define ARM_A7_TLBDATA2_SDO_MT_D 2
619 #define ARM_A7_TLBDATA2_SDO_MT_SO 6
620 #define ARM_A7_TLBDATA2_OS __BITS(75-64,74-64)
621 #define ARM_A7_TLBDATA2_OS_NC 0
622 #define ARM_A7_TLBDATA2_OS_WB_WA 1
623 #define ARM_A7_TLBDATA2_OS_WT 2
624 #define ARM_A7_TLBDATA2_OS_WB 3
625 #define ARM_A7_TLBDATA2_SH __BITS(73-64,72-64)
626 #define ARM_A7_TLBDATA2_SH_NONE 0
627 #define ARM_A7_TLBDATA2_SH_UNUSED 1
628 #define ARM_A7_TLBDATA2_SH_OS 2
629 #define ARM_A7_TLBDATA2_SH_IS 3
630 #define ARM_A7_TLBDATA2_XN2 __BIT(71-64)
631 #define ARM_A7_TLBDATA2_XN1 __BIT(70-64)
632 #define ARM_A7_TLBDATA2_PXN __BIT(69-64)
634 #define ARM_A7_TLBDATA12_PA __BITS(68-32,41-32)
636 #define ARM_A7_TLBDATA1_NS __BIT(40-32)
637 #define ARM_A7_TLBDATA1_HAP __BITS(39-32,38-32)
638 #define ARM_A7_TLBDATA1_AP __BITS(37-32,35-32)
639 #define ARM_A7_TLBDATA1_nG __BIT(34-32)
641 #define ARM_A7_TLBDATA01_ASID __BITS(33,26)
643 #define ARM_A7_TLBDATA0_VMID __BITS(25,18)
644 #define ARM_A7_TLBDATA0_VA __BITS(17,5)
645 #define ARM_A7_TLBDATA0_NS_WALK __BIT(4)
646 #define ARM_A7_TLBDATA0_SIZE __BITS(3,1)
647 #define ARM_A7_TLBDATA0_SIZE_V7_4KB 0
648 #define ARM_A7_TLBDATA0_SIZE_LPAE_4KB 1
649 #define ARM_A7_TLBDATA0_SIZE_V7_64KB 2
650 #define ARM_A7_TLBDATA0_SIZE_LPAE_64KB 3
651 #define ARM_A7_TLBDATA0_SIZE_V7_1MB 4
652 #define ARM_A7_TLBDATA0_SIZE_LPAE_2MB 5
653 #define ARM_A7_TLBDATA0_SIZE_V7_16MB 6
654 #define ARM_A7_TLBDATA0_SIZE_LPAE_1GB 7
656 #define ARM_TLBDATA_VALID __BIT(0)
658 #define ARM_TLBDATAOP_WAY __BIT(31)
659 #define ARM_A5_TLBDATAOP_INDEX __BITS(5,0)
660 #define ARM_A7_TLBDATAOP_INDEX __BITS(6,0)
662 #if !defined(__ASSEMBLER__) && defined(_KERNEL)
664 arm_cond_ok_p(uint32_t insn, uint32_t psr)
673 switch (__cond & ~1) {
693 __ok = __n == __v && !__z;
699 return (__cond & 1) ? !__ok : __ok;
703 #if !defined(__ASSEMBLER__) && !defined(_RUMPKERNEL)
704 #define ARMREG_READ_INLINE(name, __insnstring) \
705 static inline uint32_t armreg_##name##_read(void) \
708 __asm __volatile("mrc " __insnstring : "=r"(__rv)); \
712 #define ARMREG_WRITE_INLINE(name, __insnstring) \
713 static inline void armreg_##name##_write(uint32_t __val) \
715 __asm __volatile("mcr " __insnstring :: "r"(__val)); \
718 #define ARMREG_READ_INLINE2(name, __insnstring) \
719 static inline uint32_t armreg_##name##_read(void) \
722 __asm __volatile(".fpu vfp"); \
723 __asm __volatile(__insnstring : "=r"(__rv)); \
727 #define ARMREG_WRITE_INLINE2(name, __insnstring) \
728 static inline void armreg_##name##_write(uint32_t __val) \
730 __asm __volatile(".fpu vfp"); \
731 __asm __volatile(__insnstring :: "r"(__val)); \
734 #define ARMREG_READ64_INLINE(name, __insnstring) \
735 static inline uint64_t armreg_##name##_read(void) \
738 __asm __volatile("mrrc " __insnstring : "=r"(__rv)); \
742 #define ARMREG_WRITE64_INLINE(name, __insnstring) \
743 static inline void armreg_##name##_write(uint64_t __val) \
745 __asm __volatile("mcrr " __insnstring :: "r"(__val)); \
929 static inline uint64_t
930 cpu_mpidr_aff_read(
void)
939 static inline uint32_t
940 gtmr_cntfrq_read(
void)
943 return armreg_cnt_frq_read();
946 static inline uint32_t
947 gtmr_cntk_ctl_read(
void)
950 return armreg_cntk_ctl_read();
954 gtmr_cntk_ctl_write(uint32_t val)
957 armreg_cntk_ctl_write(val);
960 static inline uint64_t
961 gtmr_cntpct_read(
void)
964 return armreg_cntp_ct_read();
970 static inline uint64_t
971 gtmr_cntvct_read(
void)
974 return armreg_cntv_ct_read();
980 static inline uint32_t
981 gtmr_cntv_ctl_read(
void)
984 return armreg_cntv_ctl_read();
988 gtmr_cntv_ctl_write(uint32_t val)
991 armreg_cntv_ctl_write(val);
995 gtmr_cntp_ctl_write(uint32_t val)
998 armreg_cntp_ctl_write(val);
1005 static inline uint32_t
1006 gtmr_cntv_tval_read(
void)
1009 return armreg_cntv_tval_read();
1013 gtmr_cntv_tval_write(uint32_t val)
1016 armreg_cntv_tval_write(val);
1023 static inline uint64_t
1024 gtmr_cntv_cval_read(
void)
1027 return armreg_cntv_cval_read();
1033 #elif defined(__aarch64__)
1035 #include <aarch64/armreg.h>
#define ARMREG_WRITE_INLINE(name, __insnstring)
#define ARMREG_READ_INLINE(name, __insnstring)
vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 c3
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#define ARMREG_READ_INLINE2(name, __insnstring)
#define ARMREG_WRITE_INLINE2(name, __insnstring)
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 Q0
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#define ARMREG_READ64_INLINE(name, __insnstring)
#define ARMREG_WRITE64_INLINE(name, __insnstring)
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vmrs fpscr vmrs mvfr1 vmrs fpexc fmrx fpinst fmrx fpinst2 R0
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