99 #define wdt_reset() __asm__ __volatile__ ("wdr") 104 # define _WD_PS3_MASK _BV(WDP3) 106 # define _WD_PS3_MASK 0x00 110 # define _WD_CONTROL_REG WDTCSR 112 # define _WD_CONTROL_REG WDTCR 114 # define _WD_CONTROL_REG WDT 118 #define _WD_CHANGE_BIT WDTOE 120 #define _WD_CHANGE_BIT WDCE 138 #if defined(__AVR_XMEGA__) 140 #if defined (WDT_CTRLA) && !defined(RAMPD) 142 #define wdt_enable(timeout) \ 145 __asm__ __volatile__ ( \ 147 "out %[ccp_reg], %[ioreg_cen_mask]" "\n\t" \ 148 "lds %[tmp], %[wdt_reg]" "\n\t" \ 149 "sbr %[tmp], %[wdt_enable_timeout]" "\n\t" \ 150 "sts %[wdt_reg], %[tmp]" "\n\t" \ 151 "1:lds %[tmp], %[wdt_status_reg]" "\n\t" \ 152 "sbrc %[tmp], %[wdt_syncbusy_bit]" "\n\t" \ 154 : [tmp] "=r" (temp) \ 155 : [ccp_reg] "I" (_SFR_IO_ADDR(CCP)), \ 156 [ioreg_cen_mask] "r" ((uint8_t)CCP_IOREG_gc), \ 157 [wdt_reg] "n" (_SFR_MEM_ADDR(WDT_CTRLA)), \ 158 [wdt_enable_timeout] "M" (timeout), \ 159 [wdt_status_reg] "n" (_SFR_MEM_ADDR(WDT_STATUS)), \ 160 [wdt_syncbusy_bit] "I" (WDT_SYNCBUSY_bm) \ 164 #define wdt_disable() \ 167 __asm__ __volatile__ ( \ 169 "out %[ccp_reg], %[ioreg_cen_mask]" "\n\t" \ 170 "lds %[tmp], %[wdt_reg]" "\n\t" \ 171 "cbr %[tmp], %[timeout_mask]" "\n\t" \ 172 "sts %[wdt_reg], %[tmp]" "\n\t" \ 173 : [tmp] "=r" (temp) \ 174 : [ccp_reg] "I" (_SFR_IO_ADDR(CCP)), \ 175 [ioreg_cen_mask] "r" ((uint8_t)CCP_IOREG_gc), \ 176 [wdt_reg] "n" (_SFR_MEM_ADDR(WDT_CTRLA)),\ 177 [timeout_mask] "I" (WDT_PERIOD_gm) \ 181 #else // defined (WDT_CTRLA) && !defined(RAMPD) 195 #define wdt_enable(timeout) \ 198 __asm__ __volatile__ ( \ 199 "in __tmp_reg__, %[rampd]" "\n\t" \ 200 "out %[rampd], __zero_reg__" "\n\t" \ 201 "out %[ccp_reg], %[ioreg_cen_mask]" "\n\t" \ 202 "sts %[wdt_reg], %[wdt_enable_timeout]" "\n\t" \ 203 "1:lds %[tmp], %[wdt_status_reg]" "\n\t" \ 204 "sbrc %[tmp], %[wdt_syncbusy_bit]" "\n\t" \ 206 "out %[rampd], __tmp_reg__" "\n\t" \ 207 : [tmp] "=r" (temp) \ 208 : [rampd] "I" (_SFR_IO_ADDR(RAMPD)), \ 209 [ccp_reg] "I" (_SFR_IO_ADDR(CCP)), \ 210 [ioreg_cen_mask] "r" ((uint8_t)CCP_IOREG_gc), \ 211 [wdt_reg] "n" (_SFR_MEM_ADDR(WDT_CTRL)), \ 212 [wdt_enable_timeout] "r" ((uint8_t)(WDT_CEN_bm | WDT_ENABLE_bm | timeout)), \ 213 [wdt_status_reg] "n" (_SFR_MEM_ADDR(WDT_STATUS)), \ 214 [wdt_syncbusy_bit] "I" (WDT_SYNCBUSY_bm) \ 219 #define wdt_disable() \ 220 __asm__ __volatile__ ( \ 221 "in __tmp_reg__, %[rampd]" "\n\t" \ 222 "out %[rampd], __zero_reg__" "\n\t" \ 223 "out %[ccp_reg], %[ioreg_cen_mask]" "\n\t" \ 224 "sts %[wdt_reg], %[disable_mask]" "\n\t" \ 225 "out %[rampd], __tmp_reg__" "\n\t" \ 227 : [rampd] "I" (_SFR_IO_ADDR(RAMPD)), \ 228 [ccp_reg] "I" (_SFR_IO_ADDR(CCP)), \ 229 [ioreg_cen_mask] "r" ((uint8_t)CCP_IOREG_gc), \ 230 [wdt_reg] "n" (_SFR_MEM_ADDR(WDT_CTRL)), \ 231 [disable_mask] "r" ((uint8_t)((~WDT_ENABLE_bm) | WDT_CEN_bm)) \ 235 #endif // defined (WDT_CTRLA) && !defined(RAMPD) 237 #elif defined(__AVR_TINY__) 239 #define wdt_enable(value) \ 240 __asm__ __volatile__ ( \ 241 "in __tmp_reg__,__SREG__" "\n\t" \ 244 "out %[CCPADDRESS],%[SIGNATURE]" "\n\t" \ 245 "out %[WDTREG],%[WDVALUE]" "\n\t" \ 246 "out __SREG__,__tmp_reg__" "\n\t" \ 248 : [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)), \ 249 [SIGNATURE] "r" ((uint8_t)0xD8), \ 250 [WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \ 251 [WDVALUE] "r" ((uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00) \ 252 | _BV(WDE) | (value & 0x07) )) \ 256 #define wdt_disable() \ 259 __asm__ __volatile__ ( \ 260 "in __tmp_reg__,__SREG__" "\n\t" \ 263 "out %[CCPADDRESS],%[SIGNATURE]" "\n\t" \ 264 "in %[TEMP_WD],%[WDTREG]" "\n\t" \ 265 "cbr %[TEMP_WD],%[WDVALUE]" "\n\t" \ 266 "out %[WDTREG],%[TEMP_WD]" "\n\t" \ 267 "out __SREG__,__tmp_reg__" "\n\t" \ 269 : [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)), \ 270 [SIGNATURE] "r" ((uint8_t)0xD8), \ 271 [WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \ 272 [TEMP_WD] "d" (temp_wd), \ 273 [WDVALUE] "n" (1 << WDE) \ 282 void wdt_enable (
const uint8_t value)
284 if (!_SFR_IO_REG_P (CCP) && !_SFR_IO_REG_P (_WD_CONTROL_REG))
286 __asm__ __volatile__ (
287 "in __tmp_reg__,__SREG__" "\n\t" 290 "sts %[CCPADDRESS],%[SIGNATURE]" "\n\t" 291 "sts %[WDTREG],%[WDVALUE]" "\n\t" 292 "out __SREG__,__tmp_reg__" "\n\t" 294 : [CCPADDRESS]
"n" (_SFR_MEM_ADDR(CCP)),
295 [SIGNATURE]
"r" ((
uint8_t)0xD8),
296 [WDTREG]
"n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)),
297 [WDVALUE]
"r" ((
uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00)
298 |
_BV(WDE) | (value & 0x07) ))
302 else if (!_SFR_IO_REG_P (CCP) && _SFR_IO_REG_P (_WD_CONTROL_REG))
304 __asm__ __volatile__ (
305 "in __tmp_reg__,__SREG__" "\n\t" 308 "sts %[CCPADDRESS],%[SIGNATURE]" "\n\t" 309 "out %[WDTREG],%[WDVALUE]" "\n\t" 310 "out __SREG__,__tmp_reg__" "\n\t" 312 : [CCPADDRESS]
"n" (_SFR_MEM_ADDR(CCP)),
313 [SIGNATURE]
"r" ((
uint8_t)0xD8),
314 [WDTREG]
"I" (_SFR_IO_ADDR(_WD_CONTROL_REG)),
315 [WDVALUE]
"r" ((
uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00)
316 |
_BV(WDE) | (value & 0x07) ))
320 else if (_SFR_IO_REG_P (CCP) && !_SFR_IO_REG_P (_WD_CONTROL_REG))
322 __asm__ __volatile__ (
323 "in __tmp_reg__,__SREG__" "\n\t" 326 "out %[CCPADDRESS],%[SIGNATURE]" "\n\t" 327 "sts %[WDTREG],%[WDVALUE]" "\n\t" 328 "out __SREG__,__tmp_reg__" "\n\t" 330 : [CCPADDRESS]
"I" (_SFR_IO_ADDR(CCP)),
331 [SIGNATURE]
"r" ((
uint8_t)0xD8),
332 [WDTREG]
"n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)),
333 [WDVALUE]
"r" ((
uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00)
334 |
_BV(WDE) | (value & 0x07) ))
340 __asm__ __volatile__ (
341 "in __tmp_reg__,__SREG__" "\n\t" 344 "out %[CCPADDRESS],%[SIGNATURE]" "\n\t" 345 "out %[WDTREG],%[WDVALUE]" "\n\t" 346 "out __SREG__,__tmp_reg__" "\n\t" 348 : [CCPADDRESS]
"I" (_SFR_IO_ADDR(CCP)),
349 [SIGNATURE]
"r" ((
uint8_t)0xD8),
350 [WDTREG]
"I" (_SFR_IO_ADDR(_WD_CONTROL_REG)),
351 [WDVALUE]
"r" ((
uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00)
352 |
_BV(WDE) | (value & 0x07) ))
360 void wdt_disable (
void)
362 if (!_SFR_IO_REG_P (CCP) && !_SFR_IO_REG_P(_WD_CONTROL_REG))
365 __asm__ __volatile__ (
366 "in __tmp_reg__,__SREG__" "\n\t" 369 "sts %[CCPADDRESS],%[SIGNATURE]" "\n\t" 370 "lds %[TEMP_WD],%[WDTREG]" "\n\t" 371 "cbr %[TEMP_WD],%[WDVALUE]" "\n\t" 372 "sts %[WDTREG],%[TEMP_WD]" "\n\t" 373 "out __SREG__,__tmp_reg__" "\n\t" 375 : [CCPADDRESS]
"n" (_SFR_MEM_ADDR(CCP)),
376 [SIGNATURE]
"r" ((
uint8_t)0xD8),
377 [WDTREG]
"n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)),
378 [TEMP_WD]
"d" (temp_wd),
379 [WDVALUE]
"n" (1 << WDE)
383 else if (!_SFR_IO_REG_P (CCP) && _SFR_IO_REG_P(_WD_CONTROL_REG))
386 __asm__ __volatile__ (
387 "in __tmp_reg__,__SREG__" "\n\t" 390 "sts %[CCPADDRESS],%[SIGNATURE]" "\n\t" 391 "in %[TEMP_WD],%[WDTREG]" "\n\t" 392 "cbr %[TEMP_WD],%[WDVALUE]" "\n\t" 393 "out %[WDTREG],%[TEMP_WD]" "\n\t" 394 "out __SREG__,__tmp_reg__" "\n\t" 396 : [CCPADDRESS]
"n" (_SFR_MEM_ADDR(CCP)),
397 [SIGNATURE]
"r" ((
uint8_t)0xD8),
398 [WDTREG]
"I" (_SFR_IO_ADDR(_WD_CONTROL_REG)),
399 [TEMP_WD]
"d" (temp_wd),
400 [WDVALUE]
"n" (1 << WDE)
404 else if (_SFR_IO_REG_P (CCP) && !_SFR_IO_REG_P(_WD_CONTROL_REG))
407 __asm__ __volatile__ (
408 "in __tmp_reg__,__SREG__" "\n\t" 411 "out %[CCPADDRESS],%[SIGNATURE]" "\n\t" 412 "lds %[TEMP_WD],%[WDTREG]" "\n\t" 413 "cbr %[TEMP_WD],%[WDVALUE]" "\n\t" 414 "sts %[WDTREG],%[TEMP_WD]" "\n\t" 415 "out __SREG__,__tmp_reg__" "\n\t" 417 : [CCPADDRESS]
"I" (_SFR_IO_ADDR(CCP)),
418 [SIGNATURE]
"r" ((
uint8_t)0xD8),
419 [WDTREG]
"n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)),
420 [TEMP_WD]
"d" (temp_wd),
421 [WDVALUE]
"n" (1 << WDE)
428 __asm__ __volatile__ (
429 "in __tmp_reg__,__SREG__" "\n\t" 432 "out %[CCPADDRESS],%[SIGNATURE]" "\n\t" 433 "in %[TEMP_WD],%[WDTREG]" "\n\t" 434 "cbr %[TEMP_WD],%[WDVALUE]" "\n\t" 435 "out %[WDTREG],%[TEMP_WD]" "\n\t" 436 "out __SREG__,__tmp_reg__" "\n\t" 438 : [CCPADDRESS]
"I" (_SFR_IO_ADDR(CCP)),
439 [SIGNATURE]
"r" ((
uint8_t)0xD8),
440 [WDTREG]
"I" (_SFR_IO_ADDR(_WD_CONTROL_REG)),
441 [TEMP_WD]
"d" (temp_wd),
442 [WDVALUE]
"n" (1 << WDE)
452 void wdt_enable (
const uint8_t value)
454 if (_SFR_IO_REG_P (_WD_CONTROL_REG))
456 __asm__ __volatile__ (
457 "in __tmp_reg__,__SREG__" "\n\t" 461 "out __SREG__,__tmp_reg__" "\n\t" 464 :
"I" (_SFR_IO_ADDR(_WD_CONTROL_REG)),
466 "r" ((
uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) |
467 _BV(WDE) | (value & 0x07)) )
473 __asm__ __volatile__ (
474 "in __tmp_reg__,__SREG__" "\n\t" 478 "out __SREG__,__tmp_reg__" "\n\t" 481 :
"n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)),
483 "r" ((
uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) |
484 _BV(WDE) | (value & 0x07)) )
492 void wdt_disable (
void)
494 if (_SFR_IO_REG_P (_WD_CONTROL_REG))
497 __asm__ __volatile__ (
498 "in __tmp_reg__,__SREG__" "\n\t" 501 "in %[TEMPREG],%[WDTREG]" "\n\t" 502 "ori %[TEMPREG],%[WDCE_WDE]" "\n\t" 503 "out %[WDTREG],%[TEMPREG]" "\n\t" 504 "out %[WDTREG],__zero_reg__" "\n\t" 505 "out __SREG__,__tmp_reg__" "\n\t" 506 : [TEMPREG]
"=d" (temp_reg)
507 : [WDTREG]
"I" (_SFR_IO_ADDR(_WD_CONTROL_REG)),
515 __asm__ __volatile__ (
516 "in __tmp_reg__,__SREG__" "\n\t" 519 "lds %[TEMPREG],%[WDTREG]" "\n\t" 520 "ori %[TEMPREG],%[WDCE_WDE]" "\n\t" 521 "sts %[WDTREG],%[TEMPREG]" "\n\t" 522 "sts %[WDTREG],__zero_reg__" "\n\t" 523 "out __SREG__,__tmp_reg__" "\n\t" 524 : [TEMPREG]
"=d" (temp_reg)
525 : [WDTREG]
"n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)),
586 #if defined(__DOXYGEN__) || defined(WDP3)
unsigned char uint8_t
Definition: stdint.h:83
#define _BV(bit)
Definition: sfr_defs.h:208
static __inline__ __attribute__((__always_inline__)) void wdt_enable(const uint8_t value)
Definition: wdt.h:451