sh4_cpu.h Source File
Back to the index.
Go to the documentation of this file. 47 #if defined(_KERNEL_OPT) 48 #include "opt_lockdebug.h" 53 #include <sh3/frame.h> 57 #include <sys/cpu_data.h> 59 struct cpu_data ci_data;
62 extern struct cpu_info cpu_info_store;
63 #define curcpu() (&cpu_info_store) 69 #define cpu_number() 0 75 #define cpu_swapout(p) panic("cpu_swapout: can't get here"); 76 #define cpu_proc_fork(p1, p2) 88 #define CLKF_USERMODE(cf) (!KERNELMODE((cf)->ssr)) 89 #define CLKF_BASEPRI(cf) (((cf)->ssr & 0xf0) == 0) 90 #define CLKF_PC(cf) ((cf)->spc) 91 #define CLKF_INTR(cf) 0 98 (((struct trapframe *)(p)->p_md.md_regs)->tf_spc) 104 #define need_resched(ci) \ 107 if (curproc != NULL) \ 116 #define need_proftick(p) \ 118 (p)->p_flag |= P_OWEUPC; \ 126 #define signotify(p) aston(p) 128 #define aston(p) ((p)->p_md.md_astpending = 1) 130 extern int want_resched;
135 #define DELAY(x) delay(x) 141 #define SH3_PHYS_MASK 0x1fffffff 143 #define SH3_P0SEG_BASE 0x00000000 144 #define SH3_P0SEG_END 0x7fffffff 145 #define SH3_P1SEG_BASE 0x80000000 146 #define SH3_P1SEG_END 0x9fffffff 147 #define SH3_P2SEG_BASE 0xa0000000 148 #define SH3_P2SEG_END 0xbfffffff 149 #define SH3_P3SEG_BASE 0xc0000000 150 #define SH3_P3SEG_END 0xdfffffff 151 #define SH3_P4SEG_BASE 0xe0000000 152 #define SH3_P4SEG_END 0xffffffff 154 #define SH3_P1SEG_TO_PHYS(x) ((uint32_t)(x) & SH3_PHYS_MASK) 155 #define SH3_P2SEG_TO_PHYS(x) ((uint32_t)(x) & SH3_PHYS_MASK) 156 #define SH3_PHYS_TO_P1SEG(x) ((uint32_t)(x) | SH3_P1SEG_BASE) 157 #define SH3_PHYS_TO_P2SEG(x) ((uint32_t)(x) | SH3_P2SEG_BASE) 158 #define SH3_P1SEG_TO_P2SEG(x) ((uint32_t)(x) | 0x20000000) 159 #define SH3_P2SEG_TO_P1SEG(x) ((uint32_t)(x) & ~0x20000000) 164 #define RUN_P2 do { \ 167 goto *(void *)SH3_P1SEG_TO_P2SEG(p); \ 172 #define RUN_P1 do { \ 175 __asm volatile("nop;nop;nop;nop;nop;nop;nop;nop"); \ 176 goto *(void *)SH3_P2SEG_TO_P1SEG(p); \ 181 #define RUN_P2 do {} while ( 0) 182 #define RUN_P1 do {} while ( 0) 187 #define SH4_PVR_ADDR 0xff000030 188 #define SH4_PVR (*(volatile uint32_t *) SH4_PVR_ADDR) 189 #define SH4_PRR_ADDR 0xff000044 190 #define SH4_PRR (*(volatile uint32_t *) SH4_PRR_ADDR) 192 #define SH4_PVR_MASK 0xffffff00 193 #define SH4_PVR_SH7750 0x04020500 194 #define SH4_PVR_SH7750S 0x04020600 195 #define SH4_PVR_SH775xR 0x04050000 196 #define SH4_PVR_SH7751 0x04110000 198 #define SH4_PRR_MASK 0xfffffff0 199 #define SH4_PRR_7750R 0x00000100 200 #define SH4_PRR_7751R 0x00000110 211 #define CPU_CONSDEV 1 212 #define CPU_LOADANDRESET 2 215 #define CTL_MACHDEP_NAMES { \ 217 { "console_device", CTLTYPE_STRUCT }, \ 218 { "load_and_reset", CTLTYPE_INT }, \ 222 void sh_cpu_init(
int,
int);
223 void sh_startup(
void);
225 void _cpu_spin(uint32_t);
228 void savectx(
struct pcb *);
Generated on Fri Dec 7 2018 19:52:23 for GXemul by
1.8.13