arm_cputypes.h Source File

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arm_cputypes.h
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1 /* Imported into GXemul from NetBSD, 2018-09-25 */
2 /* $NetBSD: cputypes.h,v 1.2 2018/05/01 10:10:31 ryo Exp $ */
3 
4 /*
5  * Copyright (c) 1998, 2001 Ben Harris
6  * Copyright (c) 1994-1996 Mark Brinicombe.
7  * Copyright (c) 1994 Brini.
8  * All rights reserved.
9  *
10  * This code is derived from software written for Brini by Mark Brinicombe
11  *
12  * Redistribution and use in source and binary forms, with or without
13  * modification, are permitted provided that the following conditions
14  * are met:
15  * 1. Redistributions of source code must retain the above copyright
16  * notice, this list of conditions and the following disclaimer.
17  * 2. Redistributions in binary form must reproduce the above copyright
18  * notice, this list of conditions and the following disclaimer in the
19  * documentation and/or other materials provided with the distribution.
20  * 3. All advertising materials mentioning features or use of this software
21  * must display the following acknowledgement:
22  * This product includes software developed by Brini.
23  * 4. The name of the company nor the name of the author may be used to
24  * endorse or promote products derived from this software without specific
25  * prior written permission.
26  *
27  * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
28  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
29  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
30  * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
31  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
32  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
33  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37  * SUCH DAMAGE.
38  */
39 
40 #ifndef _ARM_CPUTYPES_H_
41 #define _ARM_CPUTYPES_H_
42 
43 /*
44  * The CPU ID register is theoretically structured, but the definitions of
45  * the fields keep changing.
46  */
47 
48 /* The high-order byte is always the implementor */
49 #define CPU_ID_IMPLEMENTOR_MASK 0xff000000
50 #define CPU_ID_ARM_LTD 0x41000000 /* 'A' */
51 #define CPU_ID_BROADCOM 0x42000000 /* 'B' */
52 #define CPU_ID_CAVIUM 0x43000000 /* 'C' */
53 #define CPU_ID_DEC 0x44000000 /* 'D' */
54 #define CPU_ID_INFINEON 0x49000000 /* 'I' */
55 #define CPU_ID_MOTOROLA 0x4d000000 /* 'M' */
56 #define CPU_ID_NVIDIA 0x4e000000 /* 'N' */
57 #define CPU_ID_APM 0x50000000 /* 'P' */
58 #define CPU_ID_QUALCOMM 0x51000000 /* 'Q' */
59 #define CPU_ID_SAMSUNG 0x53000000 /* 'S' */
60 #define CPU_ID_TI 0x54000000 /* 'T' */
61 #define CPU_ID_MARVELL 0x56000000 /* 'V' */
62 #define CPU_ID_APPLE 0x61000000 /* 'a' */
63 #define CPU_ID_FARADAY 0x66000000 /* 'f' */
64 #define CPU_ID_INTEL 0x69000000 /* 'i' */
65 
66 /* How to decide what format the CPUID is in. */
67 #define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000)
68 #define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000)
69 #define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x))
70 
71 /* On ARM3 and ARM6, this byte holds the foundry ID. */
72 #define CPU_ID_FOUNDRY_MASK 0x00ff0000
73 #define CPU_ID_FOUNDRY_VLSI 0x00560000
74 
75 /* On ARM7 it holds the architecture and variant (sub-model) */
76 #define CPU_ID_7ARCH_MASK 0x00800000
77 #define CPU_ID_7ARCH_V3 0x00000000
78 #define CPU_ID_7ARCH_V4T 0x00800000
79 #define CPU_ID_7VARIANT_MASK 0x007f0000
80 
81 /* On more recent ARMs, it does the same, but in a different format */
82 #define CPU_ID_ARCH_MASK 0x000f0000
83 #define CPU_ID_ARCH_V3 0x00000000
84 #define CPU_ID_ARCH_V4 0x00010000
85 #define CPU_ID_ARCH_V4T 0x00020000
86 #define CPU_ID_ARCH_V5 0x00030000
87 #define CPU_ID_ARCH_V5T 0x00040000
88 #define CPU_ID_ARCH_V5TE 0x00050000
89 #define CPU_ID_ARCH_V5TEJ 0x00060000
90 #define CPU_ID_ARCH_V6 0x00070000
91 #define CPU_ID_VARIANT_MASK 0x00f00000
92 
93 /* Next three nybbles are part number */
94 #define CPU_ID_PARTNO_MASK 0x0000fff0
95 
96 /* Intel XScale has sub fields in part number */
97 #define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */
98 #define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */
99 #define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */
100 
101 /* And finally, the revision number. */
102 #define CPU_ID_REVISION_MASK 0x0000000f
103 
104 /* Individual CPUs are probably best IDed by everything but the revision. */
105 #define CPU_ID_CPU_MASK 0xfffffff0
106 
107 /* Fake CPU IDs for ARMs without CP15 */
108 #define CPU_ID_ARM2 0x41560200
109 #define CPU_ID_ARM250 0x41560250
110 
111 /* Pre-ARM7 CPUs -- [15:12] == 0 */
112 #define CPU_ID_ARM3 0x41560300
113 #define CPU_ID_ARM600 0x41560600
114 #define CPU_ID_ARM610 0x41560610
115 #define CPU_ID_ARM620 0x41560620
116 
117 /* ARM7 CPUs -- [15:12] == 7 */
118 #define CPU_ID_ARM700 0x41007000 /* XXX This is a guess. */
119 #define CPU_ID_ARM710 0x41007100
120 #define CPU_ID_ARM7500 0x41027100
121 #define CPU_ID_ARM710A 0x41067100
122 #define CPU_ID_ARM7500FE 0x41077100
123 #define CPU_ID_ARM710T 0x41807100
124 #define CPU_ID_ARM720T 0x41807200
125 #define CPU_ID_ARM740T8K 0x41807400 /* XXX no MMU, 8KB cache */
126 #define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */
127 
128 /* Post-ARM7 CPUs */
129 #define CPU_ID_ARM810 0x41018100
130 #define CPU_ID_ARM920T 0x41129200
131 #define CPU_ID_ARM922T 0x41029220
132 #define CPU_ID_ARM926EJS 0x41069260
133 #define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */
134 #define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */
135 #define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */
136 #define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */
137 #define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */
138 #define CPU_ID_ARM1022ES 0x4105a220
139 #define CPU_ID_ARM1026EJS 0x4106a260
140 #define CPU_ID_ARM11MPCORE 0x410fb020
141 #define CPU_ID_ARM1136JS 0x4107b360
142 #define CPU_ID_ARM1136JSR1 0x4117b360
143 #define CPU_ID_ARM1156T2S 0x4107b560 /* MPU only */
144 #define CPU_ID_ARM1176JZS 0x410fb760
145 #define CPU_ID_ARM11_P(n) ((n & 0xff07f000) == 0x4107b000)
146 #define CPU_ID_CORTEXA5R0 0x410fc050
147 #define CPU_ID_CORTEXA7R0 0x410fc070
148 #define CPU_ID_CORTEXA8R1 0x411fc080
149 #define CPU_ID_CORTEXA8R2 0x412fc080
150 #define CPU_ID_CORTEXA8R3 0x413fc080
151 #define CPU_ID_CORTEXA9R1 0x411fc090
152 #define CPU_ID_CORTEXA9R2 0x412fc090
153 #define CPU_ID_CORTEXA9R3 0x413fc090
154 #define CPU_ID_CORTEXA9R4 0x414fc090
155 #define CPU_ID_CORTEXA15R2 0x412fc0f0
156 #define CPU_ID_CORTEXA15R3 0x413fc0f0
157 #define CPU_ID_CORTEXA17R1 0x411fc0e0
158 #define CPU_ID_CORTEXA35R0 0x410fd040
159 #define CPU_ID_CORTEXA53R0 0x410fd030
160 #define CPU_ID_CORTEXA55R1 0x411fd050
161 #define CPU_ID_CORTEXA57R0 0x410fd070
162 #define CPU_ID_CORTEXA57R1 0x411fd070
163 #define CPU_ID_CORTEXA72R0 0x410fd080
164 #define CPU_ID_CORTEXA73R0 0x410fd090
165 #define CPU_ID_CORTEXA75R2 0x412fd0a0
166 
167 #define CPU_ID_CORTEX_P(n) ((n & 0xff0fe000) == 0x410fc000)
168 #define CPU_ID_CORTEX_A5_P(n) ((n & 0xff0ff0f0) == 0x410fc050)
169 #define CPU_ID_CORTEX_A7_P(n) ((n & 0xff0ff0f0) == 0x410fc070)
170 #define CPU_ID_CORTEX_A8_P(n) ((n & 0xff0ff0f0) == 0x410fc080)
171 #define CPU_ID_CORTEX_A9_P(n) ((n & 0xff0ff0f0) == 0x410fc090)
172 #define CPU_ID_CORTEX_A15_P(n) ((n & 0xff0ff0f0) == 0x410fc0f0)
173 #define CPU_ID_CORTEX_A35_P(n) ((n & 0xff0ff0f0) == 0x410fd040)
174 #define CPU_ID_CORTEX_A53_P(n) ((n & 0xff0ff0f0) == 0x410fd030)
175 #define CPU_ID_CORTEX_A55_P(n) ((n & 0xff0ff0f0) == 0x410fd050)
176 #define CPU_ID_CORTEX_A57_P(n) ((n & 0xff0ff0f0) == 0x410fd070)
177 #define CPU_ID_CORTEX_A72_P(n) ((n & 0xff0ff0f0) == 0x410fd080)
178 #define CPU_ID_CORTEX_A73_P(n) ((n & 0xff0ff0f0) == 0x410fd090)
179 #define CPU_ID_CORTEX_A75_P(n) ((n & 0xff0ff0f0) == 0x410fd0a0)
180 #define CPU_ID_SA110 0x4401a100
181 #define CPU_ID_SA1100 0x4401a110
182 #define CPU_ID_TI925T 0x54029250
183 #define CPU_ID_MV88FR571_VD 0x56155710
184 #define CPU_ID_MV88SV131 0x56251310
185 #define CPU_ID_FA526 0x66015260
186 #define CPU_ID_SA1110 0x6901b110
187 #define CPU_ID_IXP1200 0x6901c120
188 #define CPU_ID_80200 0x69052000
189 #define CPU_ID_PXA250 0x69052100 /* sans core revision */
190 #define CPU_ID_PXA210 0x69052120
191 #define CPU_ID_PXA250A 0x69052100 /* 1st version Core */
192 #define CPU_ID_PXA210A 0x69052120 /* 1st version Core */
193 #define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */
194 #define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */
195 #define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */
196 #define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */
197 #define CPU_ID_PXA27X 0x69054110
198 #define CPU_ID_80321_400 0x69052420
199 #define CPU_ID_80321_600 0x69052430
200 #define CPU_ID_80321_400_B0 0x69052c20
201 #define CPU_ID_80321_600_B0 0x69052c30
202 #define CPU_ID_80321_600_2 0x69052c32
203 #define CPU_ID_80219_400 0x69052e20
204 #define CPU_ID_80219_600 0x69052e30
205 #define CPU_ID_IXP425_533 0x690541c0
206 #define CPU_ID_IXP425_400 0x690541d0
207 #define CPU_ID_IXP425_266 0x690541f0
208 #define CPU_ID_MV88SV58XX_P(n) ((n & 0xff0fff00) == 0x560f5800)
209 #define CPU_ID_MV88SV581X_V6 0x560f5810 /* Marvell Sheeva 88SV581x v6 Core */
210 #define CPU_ID_MV88SV581X_V7 0x561f5810 /* Marvell Sheeva 88SV581x v7 Core */
211 #define CPU_ID_MV88SV584X_V6 0x561f5840 /* Marvell Sheeva 88SV584x v6 Core */
212 #define CPU_ID_MV88SV584X_V7 0x562f5840 /* Marvell Sheeva 88SV584x v7 Core */
213 /* Marvell's CPUIDs with ARM ID in implementor field */
214 #define CPU_ID_ARM_88SV581X_V6 0x410fb760 /* Marvell Sheeva 88SV581x v6 Core */
215 #define CPU_ID_ARM_88SV581X_V7 0x413fc080 /* Marvell Sheeva 88SV581x v7 Core */
216 #define CPU_ID_ARM_88SV584X_V6 0x410fb020 /* Marvell Sheeva 88SV584x v6 Core */
217 
218 #endif /* _ARM_CPUTYPES_H_ */

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