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cpu_sh.h
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1 #ifndef CPU_SH_H
2 #define CPU_SH_H
3 
4 /*
5  * Copyright (C) 2005-2011 Anders Gavare. All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions are met:
9  *
10  * 1. Redistributions of source code must retain the above copyright
11  * notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  * notice, this list of conditions and the following disclaimer in the
14  * documentation and/or other materials provided with the distribution.
15  * 3. The name of the author may not be used to endorse or promote products
16  * derived from this software without specific prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28  * SUCH DAMAGE.
29  *
30  *
31  * SuperH CPU definitions.
32  *
33  * Note 1: Many things here are SH4-specific, so it probably doesn't work
34  * for SH3 emulation.
35  *
36  * Note 2: The SuperH emulation in GXemul does not include SH5/SH64 at
37  * this time. There doesn't seem to be that much interesting code
38  * to run in the emulator for SH5. There was a NetBSD port to that
39  * architecture, but it seems to have died out. :-/
40  */
41 
42 #include "interrupt.h"
43 #include "misc.h"
44 #include "sh4_dmacreg.h"
45 
46 #include "thirdparty/sh4_cpu.h"
47 
48 
49 struct cpu_family;
50 
51 
52 /* SH CPU types: */
54  const char *name;
55  int bits;
56  int arch;
57  uint32_t pvr;
58  uint32_t prr;
59 };
60 
61 #define SH_CPU_TYPE_DEFS { \
62  { "SH7708R", 32, 3, 0, 0, }, \
63  { "SH7750", 32, 4, SH4_PVR_SH7750, 0 }, \
64  { "SH7750R", 32, 4, SH4_PVR_SH7750, SH4_PRR_7750R }, \
65  { "SH7751R", 32, 4, SH4_PVR_SH7751, SH4_PRR_7751R }, \
66  /* { "SH5", 64, 5, 0, 0 }, */ \
67  { NULL, 0, 0, 0, 0 } }
68 
69 
70 #define SH_N_IC_ARGS 2
71 #define SH_INSTR_ALIGNMENT_SHIFT 1
72 #define SH_IC_ENTRIES_SHIFT 11
73 #define SH_IC_ENTRIES_PER_PAGE (1 << SH_IC_ENTRIES_SHIFT)
74 #define SH_PC_TO_IC_ENTRY(a) (((a)>>SH_INSTR_ALIGNMENT_SHIFT) \
75  & (SH_IC_ENTRIES_PER_PAGE-1))
76 #define SH_ADDR_TO_PAGENR(a) ((a) >> (SH_IC_ENTRIES_SHIFT \
77  + SH_INSTR_ALIGNMENT_SHIFT))
78 
79 DYNTRANS_MISC_DECLARATIONS(sh,SH,uint32_t)
80 
81 #define SH_MAX_VPH_TLB_ENTRIES 128
82 
83 
84 #define SH_N_GPRS 16
85 #define SH_N_GPRS_BANKED 8
86 #define SH_N_FPRS 16
87 
88 #define SH_N_ITLB_ENTRIES 4
89 #define SH_N_UTLB_ENTRIES 64
90 
91 /* An instruction with an invalid encoding; used for software
92  emulation of PROM calls within GXemul: */
93 #define SH_INVALID_INSTR 0x00fb
94 
95 
96 struct sh_cpu {
97  struct sh_cpu_type_def cpu_type;
98 
99  /* General Purpose Registers: */
100  uint32_t r[SH_N_GPRS];
101  uint32_t r_bank[SH_N_GPRS_BANKED];
102 
103  /* Floating-Point Registers: */
104  uint32_t fr[SH_N_FPRS];
105  uint32_t xf[SH_N_FPRS]; /* "Other bank." */
106 
107  uint32_t mach; /* Multiply-Accumulate High */
108  uint32_t macl; /* Multiply-Accumulate Low */
109  uint32_t pr; /* Procedure Register */
110  uint32_t fpscr; /* Floating-point Status/Control */
111  uint32_t fpul; /* Floating-point Communication Reg */
112  uint32_t sr; /* Status Register */
113  uint32_t ssr; /* Saved Status Register */
114  uint32_t spc; /* Saved PC */
115  uint32_t gbr; /* Global Base Register */
116  uint32_t vbr; /* Vector Base Register */
117  uint32_t sgr; /* Saved General Register */
118  uint32_t dbr; /* Debug Base Register */
119 
120  /* Cache control: */
121  uint32_t ccr; /* Cache Control Register */
122  uint32_t qacr0; /* Queue Address Control Register 0 */
123  uint32_t qacr1; /* Queue Address Control Register 1 */
124 
125  /* MMU/TLB registers: */
126  uint32_t pteh; /* Page Table Entry High */
127  uint32_t ptel; /* Page Table Entry Low */
128  uint32_t ptea; /* Page Table Entry A */
129  uint32_t ttb; /* Translation Table Base */
130  uint32_t tea; /* TLB Exception Address Register */
131  uint32_t mmucr; /* MMU Control Register */
132  uint32_t itlb_hi[SH_N_ITLB_ENTRIES];
133  uint32_t itlb_lo[SH_N_ITLB_ENTRIES];
134  uint32_t utlb_hi[SH_N_UTLB_ENTRIES];
135  uint32_t utlb_lo[SH_N_UTLB_ENTRIES];
136 
137  /* Exception handling: */
138  uint32_t tra; /* TRAPA Exception Register */
139  uint32_t expevt; /* Exception Event Register */
140  uint32_t intevt; /* Interrupt Event Register */
141 
142  /* Interrupt controller: */
143  uint16_t intc_ipra; /* Interrupt Priority Registers */
144  uint16_t intc_iprb;
145  uint16_t intc_iprc;
146  uint16_t intc_iprd;
147  uint32_t intc_intpri00;
148  uint32_t intc_intpri04;
149  uint32_t intc_intpri08;
150  uint32_t intc_intpri0c;
151  uint32_t intc_intreq00;
152  uint32_t intc_intreq04;
153  uint32_t intc_intmsk00;
154  uint32_t intc_intmsk04;
155  /* Cached and calculated values: */
156  uint8_t int_prio_and_pending[0x1000 / 0x20];
157  int16_t int_to_assert; /* Calculated int to assert */
158  unsigned int int_level; /* Calculated int level */
159 
160  /* Timer/clock functionality: */
161  int pclock;
162 
163  /* DMA Controller: (4 channels) */
164  uint32_t dmac_sar[N_SH4_DMA_CHANNELS];
165  uint32_t dmac_dar[N_SH4_DMA_CHANNELS];
166  uint32_t dmac_tcr[N_SH4_DMA_CHANNELS];
167  uint32_t dmac_chcr[N_SH4_DMA_CHANNELS];
168  uint32_t dmaor; /* DMA operation register */
169 
170  /* PCI controller: */
171  struct pci_data *pcic_pcibus;
172 
173 
174  /*
175  * Instruction translation cache and Virtual->Physical->Host
176  * address translation:
177  */
178  DYNTRANS_ITC(sh)
179  VPH_TLBS(sh,SH)
180  VPH32(sh,SH)
181 };
182 
183 
184 /* Status register bits: */
185 #define SH_SR_T 0x00000001 /* True/false */
186 #define SH_SR_S 0x00000002 /* Saturation */
187 #define SH_SR_IMASK 0x000000f0 /* Interrupt mask */
188 #define SH_SR_IMASK_SHIFT 4
189 #define SH_SR_Q 0x00000100 /* State for Divide Step */
190 #define SH_SR_M 0x00000200 /* State for Divide Step */
191 #define SH_SR_FD 0x00008000 /* FPU Disable */
192 #define SH_SR_BL 0x10000000 /* Exception/Interrupt Block */
193 #define SH_SR_RB 0x20000000 /* Register Bank 0/1 */
194 #define SH_SR_MD 0x40000000 /* Privileged Mode */
195 
196 /* Floating-point status/control register bits: */
197 #define SH_FPSCR_RM_MASK 0x00000003 /* Rounding Mode */
198 #define SH_FPSCR_RM_NEAREST 0x0 /* Round to nearest */
199 #define SH_FPSCR_RM_ZERO 0x1 /* Round to zero */
200 #define SH_FPSCR_INEXACT 0x00000004 /* Inexact exception */
201 #define SH_FPSCR_UNDERFLOW 0x00000008 /* Underflow exception */
202 #define SH_FPSCR_OVERFLOW 0x00000010 /* Overflow exception */
203 #define SH_FPSCR_DIV_BY_ZERO 0x00000020 /* Div by zero exception */
204 #define SH_FPSCR_INVALID 0x00000040 /* Invalid exception */
205 #define SH_FPSCR_EN_INEXACT 0x00000080 /* Inexact enable */
206 #define SH_FPSCR_EN_UNDERFLOW 0x00000100 /* Underflow enable */
207 #define SH_FPSCR_EN_OVERFLOW 0x00000200 /* Overflow enable */
208 #define SH_FPSCR_EN_DIV_BY_ZERO 0x00000400 /* Div by zero enable */
209 #define SH_FPSCR_EN_INVALID 0x00000800 /* Invalid enable */
210 #define SH_FPSCR_CAUSE_INEXACT 0x00001000 /* Cause Inexact */
211 #define SH_FPSCR_CAUSE_UNDERFLOW 0x00002000 /* Cause Underflow */
212 #define SH_FPSCR_CAUSE_OVERFLOW 0x00004000 /* Cause Overflow */
213 #define SH_FPSCR_CAUSE_DIVBY0 0x00008000 /* Cause Div by 0 */
214 #define SH_FPSCR_CAUSE_INVALID 0x00010000 /* Cause Invalid */
215 #define SH_FPSCR_CAUSE_ERROR 0x00020000 /* Cause Error */
216 #define SH_FPSCR_DN_ZERO 0x00040000 /* Denormalization Mode */
217 #define SH_FPSCR_PR 0x00080000 /* Double-Precision Mode */
218 #define SH_FPSCR_SZ 0x00100000 /* Double-Precision Size */
219 #define SH_FPSCR_FR 0x00200000 /* Register Bank Select */
220 
221 
222 /* int_prio_and_pending bits: */
223 #define SH_INT_ASSERTED 0x10
224 #define SH_INT_PRIO_MASK 0x0f
225 
226 /* cpu_sh.c: */
229 int sh_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib);
230 int sh_run_instr(struct cpu *cpu);
231 void sh_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
232  unsigned char *host_page, int writeflag, uint64_t paddr_page);
233 void sh_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
234 void sh_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
235 void sh_init_64bit_dummy_tables(struct cpu *cpu);
236 int sh_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
237  unsigned char *data, size_t len, int writeflag, int cache_flags);
238 int sh_cpu_family_init(struct cpu_family *);
239 
241 void sh_update_sr(struct cpu *cpu, uint32_t new_sr);
242 void sh_exception(struct cpu *cpu, int expevt, int intevt, uint32_t vaddr);
243 
244 /* memory_sh.c: */
245 int sh_translate_v2p(struct cpu *cpu, uint64_t vaddr,
246  uint64_t *return_addr, int flags);
247 
248 
249 #endif /* CPU_SH_H */
#define DYNTRANS_MISC_DECLARATIONS(arch, ARCH, addrtype)
Definition: cpu.h:72
uint16_t intc_iprd
Definition: cpu_sh.h:146
void sh_exception(struct cpu *cpu, int expevt, int intevt, uint32_t vaddr)
Definition: cpu_sh.cc:632
void sh_cpu_interrupt_assert(struct interrupt *interrupt)
Definition: cpu_sh.cc:304
#define SH_N_GPRS_BANKED
Definition: cpu_sh.h:85
uint32_t pvr
Definition: cpu_sh.h:57
uint32_t expevt
Definition: cpu_sh.h:139
uint32_t vbr
Definition: cpu_sh.h:116
uint32_t spc
Definition: cpu_sh.h:114
#define SH_N_UTLB_ENTRIES
Definition: cpu_sh.h:89
uint32_t sr
Definition: cpu_sh.h:112
int sh_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags)
int sh_cpu_family_init(struct cpu_family *)
uint32_t prr
Definition: cpu_sh.h:58
uint32_t fpul
Definition: cpu_sh.h:111
uint32_t qacr0
Definition: cpu_sh.h:122
void sh_update_interrupt_priorities(struct cpu *cpu)
Definition: cpu_sh.cc:249
struct pci_data * pcic_pcibus
Definition: cpu_sh.h:171
uint32_t macl
Definition: cpu_sh.h:108
int16_t int_to_assert
Definition: cpu_sh.h:157
uint32_t intc_intpri00
Definition: cpu_sh.h:147
uint32_t tra
Definition: cpu_sh.h:138
uint32_t fpscr
Definition: cpu_sh.h:110
uint32_t intc_intpri0c
Definition: cpu_sh.h:150
uint32_t intc_intmsk04
Definition: cpu_sh.h:154
uint32_t mmucr
Definition: cpu_sh.h:131
unsigned int int_level
Definition: cpu_sh.h:158
uint32_t qacr1
Definition: cpu_sh.h:123
const char * name
Definition: cpu_sh.h:54
uint32_t intc_intreq04
Definition: cpu_sh.h:152
void sh_init_64bit_dummy_tables(struct cpu *cpu)
uint32_t dbr
Definition: cpu_sh.h:118
uint32_t dmaor
Definition: cpu_sh.h:168
uint32_t ttb
Definition: cpu_sh.h:129
#define SH_N_ITLB_ENTRIES
Definition: cpu_sh.h:88
void sh_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page)
uint32_t intevt
Definition: cpu_sh.h:140
u_short data
Definition: siireg.h:79
uint32_t ptel
Definition: cpu_sh.h:127
#define DYNTRANS_ITC(arch)
Definition: cpu.h:143
Definition: cpu_sh.h:96
uint32_t pr
Definition: cpu_sh.h:109
uint32_t pteh
Definition: cpu_sh.h:126
void sh_update_sr(struct cpu *cpu, uint32_t new_sr)
Definition: cpu_sh.cc:585
uint32_t intc_intpri08
Definition: cpu_sh.h:149
void sh_invalidate_code_translation(struct cpu *cpu, uint64_t, int)
uint32_t ssr
Definition: cpu_sh.h:113
uint16_t intc_ipra
Definition: cpu_sh.h:143
int sh_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib)
Definition: cpu_sh.cc:395
uint16_t intc_iprb
Definition: cpu_sh.h:144
#define N_SH4_DMA_CHANNELS
Definition: sh4_dmacreg.h:35
#define SH_N_GPRS
Definition: cpu_sh.h:84
uint32_t intc_intpri04
Definition: cpu_sh.h:148
Definition: cpu.h:326
uint32_t ptea
Definition: cpu_sh.h:128
#define SH_N_FPRS
Definition: cpu_sh.h:86
int sh_translate_v2p(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
Definition: memory_sh.cc:248
#define VPH_TLBS(arch, ARCH)
Definition: cpu.h:157
uint16_t intc_iprc
Definition: cpu_sh.h:145
uint32_t tea
Definition: cpu_sh.h:130
Definition: memory.h:75
int sh_run_instr(struct cpu *cpu)
int pclock
Definition: cpu_sh.h:161
uint32_t ccr
Definition: cpu_sh.h:121
uint32_t intc_intreq00
Definition: cpu_sh.h:151
uint32_t gbr
Definition: cpu_sh.h:115
uint32_t sgr
Definition: cpu_sh.h:117
void sh_invalidate_translation_caches(struct cpu *cpu, uint64_t, int)
uint32_t mach
Definition: cpu_sh.h:107
#define VPH32(arch, ARCH)
Definition: cpu.h:189
uint32_t intc_intmsk00
Definition: cpu_sh.h:153
void sh_cpu_interrupt_deassert(struct interrupt *interrupt)
Definition: cpu_sh.cc:331

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