dev_ahc.cc Source File
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dev_ahc.cc
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/*
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* Copyright (C) 2004-2018 Anders Gavare. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*
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* COMMENT: Adaptec AHC SCSI controller
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*
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* NetBSD should say something like this, on SGI-IP32:
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*
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* ahc0 at pci0 dev 1 function 0: Adaptec aic7880 Ultra SCSI adapter
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* ahc0: interrupting at crime interrupt 8
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* ahc0: Using left over BIOS settings
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* ahc0: Host Adapter has no SEEPROM. Using default SCSI target parameters
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* ahc0: aic7880: Ultra Wide Channel A, SCSI Id=0, 16/253 SCBs
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* scsibus0 at ahc0: 16 targets, 8 luns per target
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*
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* TODO: This is just a dummy device, so far.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include "
cpu.h
"
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#include "
device.h
"
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#include "
machine.h
"
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#include "
memory.h
"
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#include "
misc.h
"
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#include "
thirdparty/aic7xxx_reg.h
"
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#define AHC_DEBUG
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#define debug fatal
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#define DEV_AHC_LENGTH 0x100
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struct
ahc_data
{
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unsigned
char
reg
[
DEV_AHC_LENGTH
];
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};
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DEVICE_ACCESS
(ahc)
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{
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struct
ahc_data
*d = (
struct
ahc_data
*) extra;
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uint64_t idata, odata = 0;
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int
ok = 0;
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const
char
*name = NULL;
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idata =
memory_readmax64
(
cpu
,
data
, len);
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/* SGI uses weird reversed order addresses: */
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if
(
cpu
->
byte_order
==
EMUL_BIG_ENDIAN
)
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relative_addr ^= 3;
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if
(len != 1)
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fatal
(
"[ ahc: ERROR! Unimplemented len %i ]\n"
, len);
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if
(writeflag ==
MEM_READ
)
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odata = d->
reg
[relative_addr];
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switch
(relative_addr) {
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case
SCSIID
:
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if
(writeflag ==
MEM_READ
) {
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ok = 1; name =
"SCSIID"
;
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odata = 0;
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}
else
{
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fatal
(
"[ ahc: write to SCSIOFFSET, data = 0x"
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"%02x: TODO ]\n"
, (
int
)idata);
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}
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break
;
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case
KERNEL_QINPOS
:
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if
(writeflag ==
MEM_WRITE
) {
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/* TODO */
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d->
reg
[
INTSTAT
] |=
SEQINT
;
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}
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break
;
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case
SEECTL
:
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ok = 1; name =
"SEECTL"
;
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if
(writeflag ==
MEM_WRITE
)
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d->
reg
[relative_addr] = idata;
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odata |=
SEERDY
;
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break
;
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case
SCSICONF
:
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ok = 1; name =
"SCSICONF"
;
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if
(writeflag ==
MEM_READ
) {
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odata = 0;
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}
else
{
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fatal
(
"[ ahc: write to SCSICONF, data = 0x%02x:"
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" TODO ]\n"
, (
int
)idata);
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}
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break
;
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case
SEQRAM
:
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case
SEQADDR0
:
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case
SEQADDR1
:
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/* TODO: This is just a dummy. */
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break
;
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case
HCNTRL
:
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ok = 1; name =
"HCNTRL"
;
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if
(writeflag ==
MEM_WRITE
)
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d->
reg
[relative_addr] = idata;
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break
;
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case
INTSTAT
:
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ok = 1; name =
"INTSTAT"
;
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if
(writeflag ==
MEM_WRITE
)
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fatal
(
"[ ahc: write to INTSTAT? data = 0x%02x ]\n"
,
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(
int
)idata);
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break
;
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case
CLRINT
:
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if
(writeflag ==
MEM_READ
) {
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ok = 1; name =
"ERROR"
;
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/* TODO */
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}
else
{
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ok = 1; name =
"CLRINT"
;
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if
(idata & ~0xf)
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fatal
(
"[ ahc: write to CLRINT: 0x%02x "
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"(TODO) ]\n"
, (
int
)idata);
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/* Clear the lowest 4 bits of intstat: */
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d->
reg
[
INTSTAT
] &= ~(idata & 0xf);
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}
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break
;
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default
:
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if
(writeflag ==
MEM_WRITE
)
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fatal
(
"[ ahc: UNIMPLEMENTED write to address 0x%x, "
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"data=0x%02x ]\n"
, (
int
)relative_addr, (
int
)idata);
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else
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fatal
(
"[ ahc: UNIMPLEMENTED read from address 0x%x ]\n"
,
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(
int
)relative_addr);
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}
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#ifdef AHC_DEBUG
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if
(ok) {
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if
(name == NULL) {
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if
(writeflag ==
MEM_WRITE
)
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debug
(
"[ ahc: write to address 0x%x: 0x"
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"%02x ]\n"
, (
int
)relative_addr, (
int
)idata);
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else
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debug
(
"[ ahc: read from address 0x%x: 0x"
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"%02x ]\n"
, (
int
)relative_addr, (
int
)odata);
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}
else
{
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if
(writeflag ==
MEM_WRITE
)
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debug
(
"[ ahc: write to %s: 0x%02x ]\n"
,
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name, (
int
)idata);
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else
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debug
(
"[ ahc: read from %s: 0x%02x ]\n"
,
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name, (
int
)odata);
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}
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}
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#endif
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if
(writeflag ==
MEM_READ
)
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memory_writemax64
(
cpu
,
data
, len, odata);
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return
1;
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}
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DEVINIT
(ahc)
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{
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struct
ahc_data
*d;
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CHECK_ALLOCATION
(d = (
struct
ahc_data
*) malloc(
sizeof
(
struct
ahc_data
)));
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memset(d, 0,
sizeof
(
struct
ahc_data
));
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memory_device_register
(
devinit
->
machine
->
memory
,
devinit
->
name
,
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devinit
->
addr
,
DEV_AHC_LENGTH
, dev_ahc_access, d,
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DM_DEFAULT
, NULL);
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return
1;
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}
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DEVICE_ACCESS
DEVICE_ACCESS(ahc)
Definition:
dev_ahc.cc:66
memory_readmax64
uint64_t memory_readmax64(struct cpu *cpu, unsigned char *buf, int len)
Definition:
memory.cc:55
fatal
void fatal(const char *fmt,...)
Definition:
main.cc:152
DM_DEFAULT
#define DM_DEFAULT
Definition:
memory.h:130
ahc_data
Definition:
dev_ahc.cc:61
memory.h
misc.h
INTSTAT
#define INTSTAT
Definition:
aic7xxx_reg.h:1532
devinit::name
char * name
Definition:
device.h:43
KERNEL_QINPOS
#define KERNEL_QINPOS
Definition:
aic7xxx_reg.h:1374
MEM_READ
#define MEM_READ
Definition:
memory.h:116
machine::memory
struct memory * memory
Definition:
machine.h:126
SEQRAM
#define SEQRAM
Definition:
aic7xxx_reg.h:1445
DEVINIT
DEVINIT(ahc)
Definition:
dev_ahc.cc:192
SEQADDR0
#define SEQADDR0
Definition:
aic7xxx_reg.h:1447
SCSICONF
#define SCSICONF
Definition:
aic7xxx_reg.h:1417
SEERDY
#define SEERDY
Definition:
aic7xxx_reg.h:1289
CHECK_ALLOCATION
#define CHECK_ALLOCATION(ptr)
Definition:
misc.h:239
DEV_AHC_LENGTH
#define DEV_AHC_LENGTH
Definition:
dev_ahc.cc:59
SCSIID
#define SCSIID
Definition:
aic7xxx_reg.h:1129
data
u_short data
Definition:
siireg.h:79
HCNTRL
#define HCNTRL
Definition:
aic7xxx_reg.h:1517
debug
#define debug
Definition:
dev_ahc.cc:56
MEM_WRITE
#define MEM_WRITE
Definition:
memory.h:117
aic7xxx_reg.h
devinit
Definition:
device.h:40
cpu.h
cpu
Definition:
cpu.h:326
devinit::machine
struct machine * machine
Definition:
device.h:41
memory_writemax64
void memory_writemax64(struct cpu *cpu, unsigned char *buf, int len, uint64_t data)
Definition:
memory.cc:89
SEECTL
#define SEECTL
Definition:
aic7xxx_reg.h:1285
memory_device_register
void memory_device_register(struct memory *mem, const char *, uint64_t baseaddr, uint64_t len, int(*f)(struct cpu *, struct memory *, uint64_t, unsigned char *, size_t, int, void *), void *extra, int flags, unsigned char *dyntrans_data)
Definition:
memory.cc:339
SEQINT
#define SEQINT
Definition:
aic7xxx_reg.h:1553
CLRINT
#define CLRINT
Definition:
aic7xxx_reg.h:1565
cpu::byte_order
uint8_t byte_order
Definition:
cpu.h:347
device.h
devinit::addr
uint64_t addr
Definition:
device.h:46
machine.h
ahc_data::reg
unsigned char reg[DEV_AHC_LENGTH]
Definition:
dev_ahc.cc:62
SEQADDR1
#define SEQADDR1
Definition:
aic7xxx_reg.h:1449
EMUL_BIG_ENDIAN
#define EMUL_BIG_ENDIAN
Definition:
misc.h:165
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