ppc_spr.h Source File
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Go to the documentation of this file. 12 #ifndef _POWERPC_SPR_H_ 13 #define _POWERPC_SPR_H_ 17 #define mtspr(reg, val) \ 18 __asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val)) 22 __asm __volatile("mfspr %0,%1" : "=r"(val) : "K"(reg)); \ 38 #define SPR_RTCU_R 0x004 39 #define SPR_RTCL_R 0x005 42 #define SPR_DSISR 0x012 43 #define DSISR_DIRECT 0x80000000 44 #define DSISR_NOTFOUND 0x40000000 45 #define DSISR_PROTECT 0x08000000 46 #define DSISR_INVRX 0x04000000 47 #define DSISR_STORE 0x02000000 48 #define DSISR_DABR 0x00400000 49 #define DSISR_SEGMENT 0x00200000 50 #define DSISR_EAR 0x00100000 52 #define SPR_RTCU_W 0x014 53 #define SPR_RTCL_W 0x015 55 #define SPR_SDR1 0x019 56 #define SPR_SRR0 0x01a 57 #define SPR_SRR1 0x01b 61 #define SPR_USPRG0 0x100 62 #define SPR_VRSAVE 0x100 63 #define SPR_SPRG0 0x110 64 #define SPR_SPRG1 0x111 65 #define SPR_SPRG2 0x112 66 #define SPR_SPRG3 0x113 67 #define SPR_SPRG4 0x114 68 #define SPR_SPRG5 0x115 69 #define SPR_SPRG6 0x116 70 #define SPR_SPRG7 0x117 80 #define MPC603e 0x0006 81 #define MPC603ev 0x0007 83 #define MPC604e 0x0009 84 #define MPC604ev 0x000a 85 #define MPC7400 0x000c 88 #define IBM401A1 0x0021 89 #define IBM401B2 0x0022 90 #define IBM401C2 0x0023 91 #define IBM401D2 0x0024 92 #define IBM401E2 0x0025 93 #define IBM401F2 0x0026 94 #define IBM401G2 0x0027 95 #define IBMPOWER3 0x0041 97 #define MPC8240 0x0081 98 #define IBM405GP 0x4011 99 #define IBM405GPR 0x5091 100 #define IBM405L 0x4161 101 #define IBM750FX 0x7000 102 #define MPC7450 0x8000 103 #define MPC7455 0x8001 104 #define MPC7457 0x8002 105 #define MPC7447A 0x8003 106 #define MPC7448 0x8004 107 #define MPC745X_P(v) ((v & 0xFFF8) == 0x8000) 108 #define MPC7410 0x800c 109 #define MPC8245 0x8081 110 #define SPR_HSPRG0 0x130 111 #define SPR_HSPRG1 0x131 112 #define SPR_HDEC 0x136 113 #define SPR_HIOR 0x137 114 #define SPR_RMOR 0x138 115 #define SPR_HRMOR 0x139 116 #define SPR_HSRR0 0x13a 117 #define SPR_HSRR1 0x13b 119 #define SPR_IBAT0U 0x210 120 #define SPR_IBAT0L 0x211 121 #define SPR_IBAT1U 0x212 122 #define SPR_IBAT1L 0x213 123 #define SPR_IBAT2U 0x214 124 #define SPR_IBAT2L 0x215 125 #define SPR_IBAT3U 0x216 126 #define SPR_IBAT3L 0x217 127 #define SPR_DBAT0U 0x218 128 #define SPR_DBAT0L 0x219 129 #define SPR_DBAT1U 0x21a 130 #define SPR_DBAT1L 0x21b 131 #define SPR_DBAT2U 0x21c 132 #define SPR_DBAT2L 0x21d 133 #define SPR_DBAT3U 0x21e 134 #define SPR_DBAT3L 0x21f 135 #define SPR_IC_CST 0x230 136 #define IC_CST_IEN 0x80000000 137 #define IC_CST_CMD_INVALL 0x0c000000 138 #define IC_CST_CMD_UNLOCKALL 0x0a000000 139 #define IC_CST_CMD_UNLOCK 0x08000000 140 #define IC_CST_CMD_LOADLOCK 0x06000000 141 #define IC_CST_CMD_DISABLE 0x04000000 142 #define IC_CST_CMD_ENABLE 0x02000000 143 #define IC_CST_CCER1 0x00200000 144 #define IC_CST_CCER2 0x00100000 145 #define IC_CST_CCER3 0x00080000 146 #define SPR_IBAT4U 0x230 147 #define SPR_IC_ADR 0x231 148 #define SPR_IBAT4L 0x231 149 #define SPR_IC_DAT 0x232 150 #define SPR_IBAT5U 0x232 151 #define SPR_IBAT5L 0x233 152 #define SPR_IBAT6U 0x234 153 #define SPR_IBAT6L 0x235 154 #define SPR_IBAT7U 0x236 155 #define SPR_IBAT7L 0x237 156 #define SPR_DC_CST 0x238 157 #define DC_CST_DEN 0x80000000 158 #define DC_CST_DFWT 0x40000000 159 #define DC_CST_LES 0x20000000 160 #define DC_CST_CMD_FLUSH 0x0e000000 161 #define DC_CST_CMD_INVALL 0x0c000000 162 #define DC_CST_CMD_UNLOCKALL 0x0a000000 163 #define DC_CST_CMD_UNLOCK 0x08000000 164 #define DC_CST_CMD_CLRLESWAP 0x07000000 165 #define DC_CST_CMD_LOADLOCK 0x06000000 166 #define DC_CST_CMD_SETLESWAP 0x05000000 167 #define DC_CST_CMD_DISABLE 0x04000000 168 #define DC_CST_CMD_CLRFWT 0x03000000 169 #define DC_CST_CMD_ENABLE 0x02000000 170 #define DC_CST_CMD_SETFWT 0x01000000 171 #define DC_CST_CCER1 0x00200000 172 #define DC_CST_CCER2 0x00100000 173 #define DC_CST_CCER3 0x00080000 174 #define SPR_DBAT4U 0x238 175 #define SPR_DC_ADR 0x231 176 #define SPR_DBAT4L 0x239 177 #define SPR_DC_DAT 0x232 178 #define SPR_DBAT5U 0x23a 179 #define SPR_DBAT5L 0x23b 180 #define SPR_DBAT6U 0x23c 181 #define SPR_DBAT6L 0x23d 182 #define SPR_DBAT7U 0x23e 183 #define SPR_DBAT7L 0x23f 184 #define SPR_MI_CTR 0x310 185 #define Mx_CTR_GPM 0x80000000 186 #define Mx_CTR_PPM 0x40000000 187 #define Mx_CTR_CIDEF 0x20000000 188 #define MD_CTR_WTDEF 0x20000000 189 #define Mx_CTR_RSV4 0x08000000 190 #define MD_CTR_TWAM 0x04000000 191 #define Mx_CTR_PPCS 0x02000000 192 #define Mx_CTR_TLB_INDX 0x000001f0 193 #define Mx_CTR_TLB_INDX_BITPOS 8 194 #define SPR_MI_AP 0x312 195 #define Mx_GP_SUPER(n) (0 << (2*(15-(n)))) 196 #define Mx_GP_PAGE (1 << (2*(15-(n)))) 197 #define Mx_GP_SWAPPED (2 << (2*(15-(n)))) 198 #define Mx_GP_USER (3 << (2*(15-(n)))) 199 #define SPR_MI_EPN 0x313 200 #define Mx_EPN_EPN 0xfffff000 201 #define Mx_EPN_EV 0x00000020 202 #define Mx_EPN_ASID 0x0000000f 203 #define SPR_MI_TWC 0x315 204 #define MD_TWC_L2TB 0xfffff000 205 #define Mx_TWC_APG 0x000001e0 206 #define Mx_TWC_G 0x00000010 207 #define Mx_TWC_PS 0x0000000c 208 #define MD_TWC_WT 0x00000002 209 #define Mx_TWC_V 0x00000001 210 #define SPR_MI_RPN 0x316 211 #define Mx_RPN_RPN 0xfffff000 212 #define Mx_RPN_PP 0x00000ff0 213 #define Mx_RPN_SPS 0x00000008 214 #define Mx_RPN_SH 0x00000004 215 #define Mx_RPN_CI 0x00000002 216 #define Mx_RPN_V 0x00000001 217 #define SPR_MD_CTR 0x318 218 #define SPR_M_CASID 0x319 219 #define M_CASID 0x0000000f 220 #define SPR_MD_AP 0x31a 221 #define SPR_MD_EPN 0x31b 222 #define SPR_M_TWB 0x31c 223 #define M_TWB_L1TB 0xfffff000 224 #define M_TWB_L1INDX 0x00000ffc 225 #define SPR_MD_TWC 0x31d 226 #define SPR_MD_RPN 0x31e 227 #define SPR_MD_TW 0x31f 228 #define SPR_MI_CAM 0x330 229 #define SPR_MI_RAM0 0x331 230 #define SPR_MI_RAM1 0x332 231 #define SPR_MD_CAM 0x338 232 #define SPR_MD_RAM0 0x339 233 #define SPR_MD_RAM1 0x33a 234 #define SPR_UMMCR2 0x3a0 235 #define SPR_UMMCR0 0x3a8 236 #define SPR_USIA 0x3ab 237 #define SPR_UMMCR1 0x3ac 238 #define SPR_ZPR 0x3b0 239 #define SPR_MMCR2 0x3b0 240 #define SPR_MMCR2_THRESHMULT_32 0x80000000 241 #define SPR_MMCR2_THRESHMULT_2 0x00000000 242 #define SPR_PID 0x3b1 243 #define SPR_PMC5 0x3b1 244 #define SPR_PMC6 0x3b2 245 #define SPR_CCR0 0x3b3 246 #define SPR_IAC3 0x3b4 247 #define SPR_IAC4 0x3b5 248 #define SPR_DVC1 0x3b6 249 #define SPR_DVC2 0x3b7 250 #define SPR_MMCR0 0x3b8 251 #define MMCR0_FC 0x80000000 252 #define MMCR0_FCS 0x40000000 253 #define MMCR0_FCP 0x20000000 254 #define MMCR0_FCM1 0x10000000 255 #define MMCR0_FCM0 0x08000000 256 #define MMCR0_PMXE 0x04000000 257 #define MMCR0_FCECE 0x02000000 258 #define MMCR0_TBSEL_15 0x01800000 259 #define MMCR0_TBSEL_19 0x01000000 260 #define MMCR0_TBSEL_23 0x00800000 261 #define MMCR0_TBSEL_31 0x00000000 262 #define MMCR0_TBEE 0x00400000 263 #define MMCRO_THRESHOLD(x) ((x) << 16) 264 #define MMCR0_PMC1CE 0x00008000 265 #define MMCR0_PMCNCE 0x00004000 266 #define MMCR0_TRIGGER 0x00002000 267 #define MMCR0_PMC1SEL(x) ((x) << 6) 268 #define MMCR0_PMC2SEL(x) ((x) << 0) 269 #define SPR_SGR 0x3b9 270 #define SPR_PMC1 0x3b9 271 #define SPR_DCWR 0x3ba 272 #define SPR_PMC2 0x3ba 273 #define SPR_SLER 0x3bb 274 #define SPR_SIA 0x3bb 275 #define SPR_MMCR1 0x3bc 276 #define MMCR1_PMC3SEL(x) ((x) << 27) 277 #define MMCR1_PMC4SEL(x) ((x) << 22) 278 #define MMCR1_PMC5SEL(x) ((x) << 17) 279 #define MMCR1_PMC6SEL(x) ((x) << 11) 281 #define SPR_SU0R 0x3bc 282 #define SPR_DBCR1 0x3bd 283 #define SPR_PMC3 0x3bd 284 #define SPR_PMC4 0x3be 285 #define SPR_DMISS 0x3d0 286 #define SPR_DCMP 0x3d1 287 #define SPR_HASH1 0x3d2 288 #define SPR_ICDBDR 0x3d3 289 #define SPR_HASH2 0x3d3 290 #define SPR_ESR 0x3d4 291 #define ESR_MCI 0x80000000 292 #define ESR_PIL 0x08000000 293 #define ESR_PPR 0x04000000 294 #define ESR_PTR 0x02000000 295 #define ESR_DST 0x00800000 296 #define ESR_DIZ 0x00800000 297 #define ESR_U0F 0x00008000 298 #define SPR_IMISS 0x3d4 299 #define SPR_TLBMISS 0x3d4 300 #define SPR_DEAR 0x3d5 301 #define SPR_ICMP 0x3d5 302 #define SPR_PTEHI 0x3d5 303 #define SPR_EVPR 0x3d6 304 #define SPR_RPA 0x3d6 305 #define SPR_PTELO 0x3d6 306 #define SPR_TSR 0x3d8 307 #define TSR_ENW 0x80000000 308 #define TSR_WIS 0x40000000 309 #define TSR_WRS_MASK 0x30000000 310 #define TSR_WRS_NONE 0x00000000 311 #define TSR_WRS_CORE 0x10000000 312 #define TSR_WRS_CHIP 0x20000000 313 #define TSR_WRS_SYSTEM 0x30000000 314 #define TSR_PIS 0x08000000 315 #define TSR_FIS 0x04000000 316 #define SPR_TCR 0x3da 317 #define TCR_WP_MASK 0xc0000000 318 #define TCR_WP_2_17 0x00000000 319 #define TCR_WP_2_21 0x40000000 320 #define TCR_WP_2_25 0x80000000 321 #define TCR_WP_2_29 0xc0000000 322 #define TCR_WRC_MASK 0x30000000 323 #define TCR_WRC_NONE 0x00000000 324 #define TCR_WRC_CORE 0x10000000 325 #define TCR_WRC_CHIP 0x20000000 326 #define TCR_WRC_SYSTEM 0x30000000 327 #define TCR_WIE 0x08000000 328 #define TCR_PIE 0x04000000 329 #define TCR_FP_MASK 0x03000000 330 #define TCR_FP_2_9 0x00000000 331 #define TCR_FP_2_13 0x01000000 332 #define TCR_FP_2_17 0x02000000 333 #define TCR_FP_2_21 0x03000000 334 #define TCR_FIE 0x00800000 335 #define TCR_ARE 0x00400000 336 #define SPR_PIT 0x3db 337 #define SPR_SRR2 0x3de 338 #define SPR_SRR3 0x3df 339 #define SPR_DBSR 0x3f0 340 #define DBSR_IC 0x80000000 341 #define DBSR_BT 0x40000000 342 #define DBSR_EDE 0x20000000 343 #define DBSR_TIE 0x10000000 344 #define DBSR_UDE 0x08000000 345 #define DBSR_IA1 0x04000000 346 #define DBSR_IA2 0x02000000 347 #define DBSR_DR1 0x01000000 348 #define DBSR_DW1 0x00800000 349 #define DBSR_DR2 0x00400000 350 #define DBSR_DW2 0x00200000 351 #define DBSR_IDE 0x00100000 352 #define DBSR_IA3 0x00080000 353 #define DBSR_IA4 0x00040000 354 #define DBSR_MRR 0x00000300 355 #define SPR_HID0 0x3f0 356 #define SPR_HID1 0x3f1 357 #define SPR_DBCR0 0x3f2 358 #define DBCR0_EDM 0x80000000 359 #define DBCR0_IDM 0x40000000 360 #define DBCR0_RST_MASK 0x30000000 361 #define DBCR0_RST_NONE 0x00000000 362 #define DBCR0_RST_CORE 0x10000000 363 #define DBCR0_RST_CHIP 0x20000000 364 #define DBCR0_RST_SYSTEM 0x30000000 365 #define DBCR0_IC 0x08000000 366 #define DBCR0_BT 0x04000000 367 #define DBCR0_EDE 0x02000000 368 #define DBCR0_TDE 0x01000000 369 #define DBCR0_IA1 0x00800000 370 #define DBCR0_IA2 0x00400000 371 #define DBCR0_IA12 0x00200000 372 #define DBCR0_IA12X 0x00100000 373 #define DBCR0_IA3 0x00080000 374 #define DBCR0_IA4 0x00040000 375 #define DBCR0_IA34 0x00020000 376 #define DBCR0_IA34X 0x00010000 377 #define DBCR0_IA12T 0x00008000 378 #define DBCR0_IA34T 0x00004000 379 #define DBCR0_FT 0x00000001 380 #define SPR_IABR 0x3f2 381 #define SPR_HID2 0x3f3 382 #define SPR_IAC1 0x3f4 383 #define SPR_IAC2 0x3f5 384 #define SPR_DABR 0x3f5 385 #define SPR_DAC1 0x3f6 386 #define SPR_MSSCR0 0x3f6 387 #define MSSCR0_SHDEN 0x80000000 388 #define MSSCR0_SHDPEN3 0x40000000 389 #define MSSCR0_L1INTVEN 0x38000000 390 #define MSSCR0_L2INTVEN 0x07000000 391 #define MSSCR0_DL1HWF 0x00800000 392 #define MSSCR0_MBO 0x00400000 393 #define MSSCR0_EMODE 0x00200000 394 #define MSSCR0_ABD 0x00100000 395 #define MSSCR0_BMODE 0x0000c000 396 #define MSSCR0_ID 0x00000040 397 #define MSSCR0_L2PFE 0x00000003 398 #define SPR_DAC2 0x3f7 399 #define SPR_L2PM 0x3f8 400 #define SPR_L2CR 0x3f9 401 #define L2CR_L2E 0x80000000 402 #define L2CR_L2PE 0x40000000 403 #define L2CR_L2SIZ 0x30000000 404 #define L2SIZ_2M 0x00000000 405 #define L2SIZ_256K 0x10000000 406 #define L2SIZ_512K 0x20000000 407 #define L2SIZ_1M 0x30000000 408 #define L2CR_L2CLK 0x0e000000 409 #define L2CLK_DIS 0x00000000 410 #define L2CLK_10 0x02000000 411 #define L2CLK_15 0x04000000 412 #define L2CLK_35 0x06000000 413 #define L2CLK_20 0x08000000 414 #define L2CLK_25 0x0a000000 415 #define L2CLK_30 0x0c000000 416 #define L2CLK_40 0x0e000000 417 #define L2CR_L2RAM 0x01800000 418 #define L2RAM_FLOWTHRU_BURST 0x00000000 419 #define L2RAM_PIPELINE_BURST 0x01000000 420 #define L2RAM_PIPELINE_LATE 0x01800000 421 #define L2CR_L2DO 0x00400000 424 #define L2CR_L2I 0x00200000 425 #define L2CR_L2CTL 0x00100000 428 #define L2CR_L2WT 0x00080000 429 #define L2CR_L2TS 0x00040000 430 #define L2CR_L2OH 0x00030000 431 #define L2CR_L2SL 0x00008000 432 #define L2CR_L2DF 0x00004000 433 #define L2CR_L2BYP 0x00002000 434 #define L2CR_L2FA 0x00001000 435 #define L2CR_L2HWF 0x00000800 436 #define L2CR_L2IO 0x00000400 437 #define L2CR_L2CLKSTP 0x00000200 438 #define L2CR_L2DRO 0x00000100 439 #define L2CR_L2IP 0x00000001 441 #define SPR_L3CR 0x3fa 442 #define L3CR_RESERVED 0x0438003a 443 #define L3CR_L3E 0x80000000 444 #define L3CR_L3PE 0x40000000 445 #define L3CR_L3APE 0x20000000 446 #define L3CR_L3SIZ 0x10000000 447 #define L3SIZ_1M 0x00000000 448 #define L3SIZ_2M 0x10000000 449 #define L3CR_L3CLKEN 0x08000000 450 #define L3CR_L3CLK 0x03800000 451 #define L3CLK_60 0x00000000 452 #define L3CLK_20 0x01000000 453 #define L3CLK_25 0x01800000 454 #define L3CLK_30 0x02000000 455 #define L3CLK_35 0x02800000 456 #define L3CLK_40 0x03000000 457 #define L3CLK_50 0x03800000 458 #define L3CR_L3IO 0x00400000 459 #define L3CR_L3SPO 0x00040000 460 #define L3CR_L3CKSP 0x00030000 461 #define L3CKSP_2 0x00000000 462 #define L3CKSP_3 0x00010000 463 #define L3CKSP_4 0x00020000 464 #define L3CKSP_5 0x00030000 465 #define L3CR_L3PSP 0x0000e000 466 #define L3PSP_0 0x00000000 467 #define L3PSP_1 0x00002000 468 #define L3PSP_2 0x00004000 469 #define L3PSP_3 0x00006000 470 #define L3PSP_4 0x00008000 471 #define L3PSP_5 0x0000a000 472 #define L3CR_L3REP 0x00001000 473 #define L3CR_L3HWF 0x00000800 474 #define L3CR_L3I 0x00000400 475 #define L3CR_L3RT 0x00000300 476 #define L3RT_MSUG2_DDR 0x00000000 477 #define L3RT_PIPELINE_LATE 0x00000100 478 #define L3RT_PB2_SRAM 0x00000300 479 #define L3CR_L3NIRCA 0x00000080 480 #define L3CR_L3DO 0x00000040 481 #define L3CR_PMEN 0x00000004 482 #define L3CR_PMSIZ 0x00000004 483 #define SPR_DCCR 0x3fa 484 #define SPR_ICCR 0x3fb 485 #define SPR_THRM1 0x3fc 486 #define SPR_THRM2 0x3fd 487 #define SPR_THRM_TIN 0x80000000 488 #define SPR_THRM_TIV 0x40000000 489 #define SPR_THRM_THRESHOLD(x) ((x) << 23) 490 #define SPR_THRM_TID 0x00000004 491 #define SPR_THRM_TIE 0x00000002 492 #define SPR_THRM_VALID 0x00000001 493 #define SPR_THRM3 0x3fe 494 #define SPR_THRM_TIMER(x) ((x) << 1) 495 #define SPR_THRM_ENABLE 0x00000001 496 #define SPR_FPECR 0x3fe 497 #define SPR_PIR 0x3ff 500 #define TBR_TBL 0x10c 501 #define TBR_TBU 0x10d 504 #define PMC_OVERFLOW 0x80000000 508 #define PMCN_CYCLES 1 510 #define PMCN_TBLTRANS 3 511 #define PCMN_IDISPATCH 4
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