dec_maxine.h Source File
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Go to the documentation of this file. 97 #define XINE_PHYS_MIN 0x00000000 98 #define XINE_PHYS_MAX 0x1fffffff 103 #define XINE_PHYS_MEMORY_START 0x00000000 104 #define XINE_PHYS_MEMORY_END 0x027fffff 110 #define XINE_PHYS_CFB_START 0x08000000 111 #define XINE_PHYS_CFB_END 0x0bffffff 113 #define XINE_PHYS_MREGS_START 0x0c000000 114 #define XINE_PHYS_MREGS_END 0x0dffffff 115 #define XINE_PHYS_CREGS_START 0x0e000000 116 #define XINE_PHYS_CREGS_END 0x0fffffff 118 #define XINE_PHYS_TC_0_START 0x10000000 119 #define XINE_PHYS_TC_0_END 0x13ffffff 121 #define XINE_PHYS_TC_1_START 0x14000000 122 #define XINE_PHYS_TC_1_END 0x17ffffff 124 #define XINE_PHYS_TC_RESERVED 0x18000000 127 #define XINE_PHYS_TC_3_START 0x1c000000 128 #define XINE_PHYS_TC_3_END 0x1fffffff 130 #define XINE_PHYS_TC_START XINE_PHYS_TC_0_START 131 #define XINE_PHYS_TC_END XINE_PHYS_TC_3_END 133 #define XINE_TC_NSLOTS 4 134 #define XINE_TC_MIN 0 135 #define XINE_TC_MAX 1 140 #define XINE_SYS_ASIC (XINE_PHYS_TC_3_START + 0x0000000) 141 #define XINE_SYS_ROM_START (XINE_SYS_ASIC + IOASIC_SLOT_0_START) 142 #define XINE_SYS_ASIC_REGS (XINE_SYS_ASIC + IOASIC_SLOT_1_START) 143 #define XINE_SYS_ETHER_ADDRESS (XINE_SYS_ASIC + IOASIC_SLOT_2_START) 144 #define XINE_SYS_LANCE (XINE_SYS_ASIC + IOASIC_SLOT_3_START) 145 #define XINE_SYS_SCC_0 (XINE_SYS_ASIC + IOASIC_SLOT_4_START) 146 #define XINE_SYS_VDAC_HI (XINE_SYS_ASIC + IOASIC_SLOT_5_START) 147 #define XINE_SYS_VDAC_LO (XINE_SYS_ASIC + IOASIC_SLOT_7_START) 148 #define XINE_SYS_CLOCK (XINE_SYS_ASIC + IOASIC_SLOT_8_START) 149 #define XINE_SYS_ISDN (XINE_SYS_ASIC + IOASIC_SLOT_9_START) 150 #define XINE_SYS_DTOP (XINE_SYS_ASIC + IOASIC_SLOT_10_START) 151 #define XINE_SYS_FLOPPY (XINE_SYS_ASIC + IOASIC_SLOT_11_START) 152 #define XINE_SYS_SCSI (XINE_SYS_ASIC + IOASIC_SLOT_12_START) 153 #define XINE_SYS_FLOPPY_DMA (XINE_SYS_ASIC + IOASIC_SLOT_13_START) 154 #define XINE_SYS_SCSI_DMA (XINE_SYS_ASIC + IOASIC_SLOT_14_START) 155 #define XINE_SYS_BOOT_ROM_START (XINE_PHYS_TC_3_START + 0x3c00000) 156 #define XINE_SYS_BOOT_ROM_END (XINE_PHYS_TC_3_START + 0x3c40000) 161 #define XINE_INT_FPA IP_LEV7 162 #define XINE_INT_HALTB IP_LEV6 163 #define XINE_INT_TC3 IP_LEV5 164 #define XINE_INT_TIMEOUT IP_LEV4 165 #define XINE_INT_TOY IP_LEV3 166 #define XINE_INT_1_10_MS IP_LEV2 171 #define XINE_REG_CMR 0x0c000000 172 #define XINE_REG_MER 0x0c400000 173 #define XINE_REG_MSR 0x0c800000 174 #define XINE_REG_FCTR 0x0ca00000 175 #define XINE_REG_FI 0x0cc00000 177 #define XINE_REG_CNFG 0x0e000000 178 #define XINE_REG_AER 0x0e000004 179 #define XINE_REG_TIMEOUT 0x0e00000c 181 #define XINE_REG_SCSI_DMAPTR ( XINE_SYS_ASIC + IOASIC_SCSI_DMAPTR ) 182 #define XINE_REG_SCSI_DMANPTR ( XINE_SYS_ASIC + IOASIC_SCSI_NEXTPTR ) 183 #define XINE_REG_LANCE_DMAPTR ( XINE_SYS_ASIC + IOASIC_LANCE_DMAPTR ) 184 #define XINE_REG_SCC_T1_DMAPTR ( XINE_SYS_ASIC + IOASIC_SCC_T1_DMAPTR ) 185 #define XINE_REG_SCC_R1_DMAPTR ( XINE_SYS_ASIC + IOASIC_SCC_R1_DMAPTR ) 186 #define XINE_REG_DTOP_T_DMAPTR ( XINE_SYS_ASIC + IOASIC_SCC_T2_DMAPTR ) 187 #define XINE_REG_DTOP_R_DMAPTR ( XINE_SYS_ASIC + IOASIC_SCC_R2_DMAPTR ) 188 #define XINE_FLOPPY_DMAPTR ( XINE_SYS_ASIC + IOASIC_FLOPPY_DMAPTR ) 189 #define XINE_ISDN_X_DMAPTR ( XINE_SYS_ASIC + IOASIC_ISDN_X_DMAPTR ) 190 #define XINE_ISDN_X_NEXTPTR ( XINE_SYS_ASIC + IOASIC_ISDN_X_NEXTPTR ) 191 #define XINE_ISDN_R_DMAPTR ( XINE_SYS_ASIC + IOASIC_ISDN_R_DMAPTR ) 192 #define XINE_ISDN_R_NEXTPTR ( XINE_SYS_ASIC + IOASIC_ISDN_R_NEXTPTR ) 193 #define XINE_REG_CSR ( XINE_SYS_ASIC + IOASIC_CSR ) 194 #define XINE_REG_INTR ( XINE_SYS_ASIC + IOASIC_INTR ) 195 #define XINE_REG_IMSK ( XINE_SYS_ASIC + IOASIC_IMSK ) 196 #define XINE_REG_CURADDR ( XINE_SYS_ASIC + IOASIC_CURADDR ) 197 #define XINE_ISDN_X_DATA ( XINE_SYS_ASIC + IOASIC_ISDN_X_DATA ) 198 #define XINE_ISDN_R_DATA ( XINE_SYS_ASIC + IOASIC_ISDN_R_DATA ) 200 #define XINE_REG_LANCE_DECODE ( XINE_SYS_ASIC + IOASIC_LANCE_DECODE ) 201 #define XINE_REG_SCSI_DECODE ( XINE_SYS_ASIC + IOASIC_SCSI_DECODE ) 202 #define XINE_REG_SCC0_DECODE ( XINE_SYS_ASIC + IOASIC_SCC0_DECODE ) 203 #define XINE_REG_DTOP_DECODE ( XINE_SYS_ASIC + IOASIC_SCC1_DECODE ) 204 #define XINE_REG_FLOPPY_DECODE ( XINE_SYS_ASIC + IOASIC_FLOPPY_DECODE ) 205 # define XINE_LANCE_CONFIG 3 206 # define XINE_SCSI_CONFIG 14 207 # define XINE_SCC0_CONFIG (0x10|4) 208 # define XINE_DTOP_CONFIG 10 209 # define XINE_FLOPPY_CONFIG 13 211 #define XINE_REG_SCSI_SCR ( XINE_SYS_ASIC + IOASIC_SCSI_SCR ) 212 #define XINE_REG_SCSI_SDR0 ( XINE_SYS_ASIC + IOASIC_SCSI_SDR0 ) 213 #define XINE_REG_SCSI_SDR1 ( XINE_SYS_ASIC + IOASIC_SCSI_SDR1 ) 219 #define XINE_MER_xxx 0xf7fe30ff 220 #define XINE_MER_10_1_MS_IP 0x08000000 221 #define XINE_MER_PAGE_BRY 0x00010000 222 #define XINE_MER_TLEN 0x00008000 223 #define XINE_MER_PARDIS 0x00004000 224 #define XINE_MER_LASTBYTE 0x00000f00 225 # define XINE_LASTB31 0x00000800 226 # define XINE_LASTB23 0x00000400 227 # define XINE_LASTB15 0x00000200 228 # define XINE_LASTB07 0x00000100 231 #define XINE_MSR_xxx 0xffffdfff 232 #define XINE_MSR_10_1_MS_EN 0x04000000 233 #define XINE_MSR_10_1_MS 0x02000000 234 #define XINE_MSR_PFORCE 0x01e00000 235 #define XINE_MSR_MABEN 0x00100000 236 #define XINE_MSR_LAST_BANK 0x000e0000 237 # define XINE_BANK_0 0x00020000 238 # define XINE_BANK_1 0x00040000 239 # define XINE_BANK_2 0x00080000 240 #define XINE_MSR_SIZE_16Mb 0x00002000 243 #define XINE_FI_VALUE 0x00001000 264 #define XINE_CNFG_VALUE 121 267 #define XINE_AER_ADDR_MASK 0x1ffffffc 270 #define XINE_TIMEO_INTR 0x00000001 277 #define XINE_CSR_DIAGDN 0x00008000 278 #define XINE_CSR_ISDN_ENABLE 0x00001000 279 #define XINE_CSR_SCC_ENABLE 0x00000800 280 #define XINE_CSR_RTC_ENABLE 0x00000400 281 #define XINE_CSR_SCSI_ENABLE 0x00000200 282 #define XINE_CSR_LANCE_ENABLE 0x00000100 283 #define XINE_CSR_FLOPPY_ENABLE 0x00000080 284 #define XINE_CSR_VDAC_ENABLE 0x00000040 285 #define XINE_CSR_DTOP_ENABLE 0x00000020 286 #define XINE_CSR_LED 0x00000001 290 #define XINE_INTR_xxxx 0x00002808 291 #define XINE_INTR_FLOPPY 0x00008000 292 #define XINE_INTR_NVR_JUMPER 0x00004000 293 #define XINE_INTR_POWERUP 0x00002000 294 #define XINE_INTR_TC_0 0x00001000 295 #define XINE_INTR_ISDN 0x00000800 296 #define XINE_INTR_NRMOD_JUMPER 0x00000400 297 #define XINE_INTR_SCSI 0x00000200 298 #define XINE_INTR_LANCE 0x00000100 299 #define XINE_INTR_FLOPPY_HDS 0x00000080 300 #define XINE_INTR_SCC_0 0x00000040 301 #define XINE_INTR_TC_1 0x00000020 302 #define XINE_INTR_FLOPPY_XDS 0x00000010 303 #define XINE_INTR_VINT 0x00000008 304 #define XINE_INTR_N_VINT 0x00000004 305 #define XINE_INTR_DTOP_TX 0x00000002 306 #define XINE_INTR_DTOP_RX 0x00000001 307 #define XINE_INTR_ASIC 0xffff0000 308 #define XINE_INTR_DTOP 0x00000003 309 #define XINE_IM0 0xffff9b6b
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