i82365reg.h Source File
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Go to the documentation of this file. 44 #define PCIC_REG_INDEX 0 45 #define PCIC_REG_DATA 1 54 #define PCIC_CHIP_OFFSET 0x80 55 #define PCIC_SOCKET_OFFSET 0x40 59 #define PCIC_IDENT 0x00 60 #define PCIC_IDENT_IFTYPE_MASK 0xC0 61 #define PCIC_IDENT_IFTYPE_IO_ONLY 0x00 62 #define PCIC_IDENT_IFTYPE_MEM_ONLY 0x40 63 #define PCIC_IDENT_IFTYPE_MEM_AND_IO 0x80 64 #define PCIC_IDENT_IFTYPE_RESERVED 0xC0 65 #define PCIC_IDENT_ZERO 0x30 66 #define PCIC_IDENT_REV_MASK 0x0F 67 #define PCIC_IDENT_REV_I82365SLR0 0x02 68 #define PCIC_IDENT_REV_I82365SLR1 0x03 70 #define PCIC_IDENT_ID_INTEL0 0x82 71 #define PCIC_IDENT_ID_INTEL1 0x83 72 #define PCIC_IDENT_ID_INTEL2 0x84 73 #define PCIC_IDENT_ID_IBM1 0x88 74 #define PCIC_IDENT_ID_IBM2 0x89 75 #define PCIC_IDENT_ID_IBM3 0x8A 77 #define PCIC_IF_STATUS 0x01 78 #define PCIC_IF_STATUS_GPI 0x80 79 #define PCIC_IF_STATUS_POWERACTIVE 0x40 80 #define PCIC_IF_STATUS_READY 0x20 81 #define PCIC_IF_STATUS_MEM_WP 0x10 82 #define PCIC_IF_STATUS_CARDDETECT_MASK 0x0C 83 #define PCIC_IF_STATUS_CARDDETECT_PRESENT 0x0C 84 #define PCIC_IF_STATUS_BATTERY_MASK 0x03 85 #define PCIC_IF_STATUS_BATTERY_DEAD1 0x00 86 #define PCIC_IF_STATUS_BATTERY_DEAD2 0x01 87 #define PCIC_IF_STATUS_BATTERY_WARNING 0x02 88 #define PCIC_IF_STATUS_BATTERY_GOOD 0x03 90 #define PCIC_PWRCTL 0x02 91 #define PCIC_PWRCTL_OE 0x80 92 #define PCIC_PWRCTL_DISABLE_RESETDRV 0x40 93 #define PCIC_PWRCTL_AUTOSWITCH_ENABLE 0x20 94 #define PCIC_PWRCTL_PWR_ENABLE 0x10 95 #define PCIC_PWRCTL_VPP2_MASK 0x0C 96 #define PCIC_PWRCTL_VPP2_RESERVED 0x0C 97 #define PCIC_PWRCTL_VPP2_12V 0x08 98 #define PCIC_PWRCTL_VPP2_VCC 0x04 99 #define PCIC_PWRCTL_VPP2_OFF 0x00 100 #define PCIC_PWRCTL_VPP1_MASK 0x03 101 #define PCIC_PWRCTL_VPP1_RESERVED 0x03 102 #define PCIC_PWRCTL_VPP1_12V 0x02 103 #define PCIC_PWRCTL_VPP1_VCC 0x01 104 #define PCIC_PWRCTL_VPP1_OFF 0x00 106 #define PCIC_CSC 0x04 107 #define PCIC_CSC_ZERO 0xE0 108 #define PCIC_CSC_GPI 0x10 109 #define PCIC_CSC_CD 0x08 110 #define PCIC_CSC_READY 0x04 111 #define PCIC_CSC_BATTWARN 0x02 112 #define PCIC_CSC_BATTDEAD 0x01 113 #define PCIC_CSC_RI 0x01 115 #define PCIC_ADDRWIN_ENABLE 0x06 116 #define PCIC_ADDRWIN_ENABLE_IO1 0x80 117 #define PCIC_ADDRWIN_ENABLE_IO0 0x40 118 #define PCIC_ADDRWIN_ENABLE_MEMCS16 0x20 119 #define PCIC_ADDRWIN_ENABLE_MEM4 0x10 120 #define PCIC_ADDRWIN_ENABLE_MEM3 0x08 121 #define PCIC_ADDRWIN_ENABLE_MEM2 0x04 122 #define PCIC_ADDRWIN_ENABLE_MEM1 0x02 123 #define PCIC_ADDRWIN_ENABLE_MEM0 0x01 126 #define PCIC_CARD_DETECT 0x16 127 #define PCIC_CARD_DETECT_RESERVED 0xC0 128 #define PCIC_CARD_DETECT_SW_INTR 0x20 129 #define PCIC_CARD_DETECT_RESUME_ENABLE 0x10 130 #define PCIC_CARD_DETECT_GPI_TRANSCTL 0x08 131 #define PCIC_CARD_DETECT_GPI_ENABLE 0x04 132 #define PCIC_CARD_DETECT_CFGRST_ENABLE 0x02 133 #define PCIC_CARD_DETECT_MEMDLY_INHIBIT 0x01 137 #define PCIC_INTR 0x03 138 #define PCIC_INTR_RI_ENABLE 0x80 139 #define PCIC_INTR_RESET 0x40 140 #define PCIC_INTR_CARDTYPE_MASK 0x20 141 #define PCIC_INTR_CARDTYPE_IO 0x20 142 #define PCIC_INTR_CARDTYPE_MEM 0x00 143 #define PCIC_INTR_ENABLE 0x10 144 #define PCIC_INTR_IRQ_MASK 0x0F 145 #define PCIC_INTR_IRQ_SHIFT 0 146 #define PCIC_INTR_IRQ_NONE 0x00 147 #define PCIC_INTR_IRQ_RESERVED1 0x01 148 #define PCIC_INTR_IRQ_RESERVED2 0x02 149 #define PCIC_INTR_IRQ3 0x03 150 #define PCIC_INTR_IRQ4 0x04 151 #define PCIC_INTR_IRQ5 0x05 152 #define PCIC_INTR_IRQ_RESERVED6 0x06 153 #define PCIC_INTR_IRQ7 0x07 154 #define PCIC_INTR_IRQ_RESERVED8 0x08 155 #define PCIC_INTR_IRQ9 0x09 156 #define PCIC_INTR_IRQ10 0x0A 157 #define PCIC_INTR_IRQ11 0x0B 158 #define PCIC_INTR_IRQ12 0x0C 159 #define PCIC_INTR_IRQ_RESERVED13 0x0D 160 #define PCIC_INTR_IRQ14 0x0E 161 #define PCIC_INTR_IRQ15 0x0F 163 #define PCIC_INTR_IRQ_VALIDMASK 0xDEB8 165 #define PCIC_CSC_INTR 0x05 166 #define PCIC_CSC_INTR_IRQ_MASK 0xF0 167 #define PCIC_CSC_INTR_IRQ_SHIFT 4 168 #define PCIC_CSC_INTR_IRQ_NONE 0x00 169 #define PCIC_CSC_INTR_IRQ_RESERVED1 0x10 170 #define PCIC_CSC_INTR_IRQ_RESERVED2 0x20 171 #define PCIC_CSC_INTR_IRQ3 0x30 172 #define PCIC_CSC_INTR_IRQ4 0x40 173 #define PCIC_CSC_INTR_IRQ5 0x50 174 #define PCIC_CSC_INTR_IRQ_RESERVED6 0x60 175 #define PCIC_CSC_INTR_IRQ7 0x70 176 #define PCIC_CSC_INTR_IRQ_RESERVED8 0x80 177 #define PCIC_CSC_INTR_IRQ9 0x90 178 #define PCIC_CSC_INTR_IRQ10 0xA0 179 #define PCIC_CSC_INTR_IRQ11 0xB0 180 #define PCIC_CSC_INTR_IRQ12 0xC0 181 #define PCIC_CSC_INTR_IRQ_RESERVED13 0xD0 182 #define PCIC_CSC_INTR_IRQ14 0xE0 183 #define PCIC_CSC_INTR_IRQ15 0xF0 184 #define PCIC_CSC_INTR_CD_ENABLE 0x08 185 #define PCIC_CSC_INTR_READY_ENABLE 0x04 186 #define PCIC_CSC_INTR_BATTWARN_ENABLE 0x02 187 #define PCIC_CSC_INTR_BATTDEAD_ENABLE 0x01 188 #define PCIC_CSC_INTR_RI_ENABLE 0x01 190 #define PCIC_CSC_INTR_FORMAT "\177\020" "f\4\4CSC_INTR_IRQ\0" \ 196 #define PCIC_CSC_INTR_IRQ_VALIDMASK 0xDEB8 200 #define PCIC_IO_WINS 2 202 #define PCIC_IOCTL 0x07 203 #define PCIC_IOCTL_IO1_WAITSTATE 0x80 204 #define PCIC_IOCTL_IO1_ZEROWAIT 0x40 205 #define PCIC_IOCTL_IO1_IOCS16SRC_MASK 0x20 206 #define PCIC_IOCTL_IO1_IOCS16SRC_CARD 0x20 207 #define PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE 0x00 208 #define PCIC_IOCTL_IO1_DATASIZE_MASK 0x10 209 #define PCIC_IOCTL_IO1_DATASIZE_16BIT 0x10 210 #define PCIC_IOCTL_IO1_DATASIZE_8BIT 0x00 211 #define PCIC_IOCTL_IO0_WAITSTATE 0x08 212 #define PCIC_IOCTL_IO0_ZEROWAIT 0x04 213 #define PCIC_IOCTL_IO0_IOCS16SRC_MASK 0x02 214 #define PCIC_IOCTL_IO0_IOCS16SRC_CARD 0x02 215 #define PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE 0x00 216 #define PCIC_IOCTL_IO0_DATASIZE_MASK 0x01 217 #define PCIC_IOCTL_IO0_DATASIZE_16BIT 0x01 218 #define PCIC_IOCTL_IO0_DATASIZE_8BIT 0x00 220 #define PCIC_IOADDR0_START_LSB 0x08 221 #define PCIC_IOADDR0_START_MSB 0x09 222 #define PCIC_IOADDR0_STOP_LSB 0x0A 223 #define PCIC_IOADDR0_STOP_MSB 0x0B 224 #define PCIC_IOADDR1_START_LSB 0x0C 225 #define PCIC_IOADDR1_START_MSB 0x0D 226 #define PCIC_IOADDR1_STOP_LSB 0x0E 227 #define PCIC_IOADDR1_STOP_MSB 0x0F 237 #define PCIC_MEM_WINS 5 239 #define PCIC_MEM_SHIFT 12 240 #define PCIC_MEM_PAGESIZE (1<<PCIC_MEM_SHIFT) 242 #define PCIC_SYSMEM_ADDRX_SHIFT PCIC_MEM_SHIFT 243 #define PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_MASK 0x80 244 #define PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT 0x80 245 #define PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_8BIT 0x00 246 #define PCIC_SYSMEM_ADDRX_START_MSB_ZEROWAIT 0x40 247 #define PCIC_SYSMEM_ADDRX_START_MSB_SCRATCH_MASK 0x30 248 #define PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK 0x0F 250 #define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT_MASK 0xC0 251 #define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT0 0x00 252 #define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT1 0x40 253 #define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2 0x80 254 #define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT3 0xC0 255 #define PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK 0x0F 263 #define PCIC_CARDMEM_ADDRX_SHIFT PCIC_MEM_SHIFT 264 #define PCIC_CARDMEM_ADDRX_MSB_WP 0x80 265 #define PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_MASK 0x40 266 #define PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR 0x40 267 #define PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_COMMON 0x00 268 #define PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK 0x3F 270 #define PCIC_SYSMEM_ADDR0_START_LSB 0x10 271 #define PCIC_SYSMEM_ADDR0_START_MSB 0x11 272 #define PCIC_SYSMEM_ADDR0_STOP_LSB 0x12 273 #define PCIC_SYSMEM_ADDR0_STOP_MSB 0x13 275 #define PCIC_CARDMEM_ADDR0_LSB 0x14 276 #define PCIC_CARDMEM_ADDR0_MSB 0x15 280 #define PCIC_SYSMEM_ADDR1_START_LSB 0x18 281 #define PCIC_SYSMEM_ADDR1_START_MSB 0x19 282 #define PCIC_SYSMEM_ADDR1_STOP_LSB 0x1A 283 #define PCIC_SYSMEM_ADDR1_STOP_MSB 0x1B 285 #define PCIC_CARDMEM_ADDR1_LSB 0x1C 286 #define PCIC_CARDMEM_ADDR1_MSB 0x1D 288 #define PCIC_SYSMEM_ADDR2_START_LSB 0x20 289 #define PCIC_SYSMEM_ADDR2_START_MSB 0x21 290 #define PCIC_SYSMEM_ADDR2_STOP_LSB 0x22 291 #define PCIC_SYSMEM_ADDR2_STOP_MSB 0x23 293 #define PCIC_CARDMEM_ADDR2_LSB 0x24 294 #define PCIC_CARDMEM_ADDR2_MSB 0x25 299 #define PCIC_SYSMEM_ADDR3_START_LSB 0x28 300 #define PCIC_SYSMEM_ADDR3_START_MSB 0x29 301 #define PCIC_SYSMEM_ADDR3_STOP_LSB 0x2A 302 #define PCIC_SYSMEM_ADDR3_STOP_MSB 0x2B 304 #define PCIC_CARDMEM_ADDR3_LSB 0x2C 305 #define PCIC_CARDMEM_ADDR3_MSB 0x2D 310 #define PCIC_SYSMEM_ADDR4_START_LSB 0x30 311 #define PCIC_SYSMEM_ADDR4_START_MSB 0x31 312 #define PCIC_SYSMEM_ADDR4_STOP_LSB 0x32 313 #define PCIC_SYSMEM_ADDR4_STOP_MSB 0x33 315 #define PCIC_CARDMEM_ADDR4_LSB 0x34 316 #define PCIC_CARDMEM_ADDR4_MSB 0x35 331 #define PCIC_INTEL_GLOBAL_CTL 0x1E 332 #define PCIC_INTEL_GLOBAL_CTL_RESERVED 0xF0 333 #define PCIC_INTEL_GLOBAL_CTL_IRQ14PULSE_ENABLE 0x08 334 #define PCIC_INTEL_GLOBAL_CTL_EXPLICIT_CSC_ACK 0x04 335 #define PCIC_INTEL_GLOBAL_CTL_IRQLEVEL_ENABLE 0x02 336 #define PCIC_INTEL_GLOBAL_CTL_POWERDOWN 0x01 338 #define PCIC_CIRRUS_MISC_CTL_1 0x16 339 #define PCIC_CIRRUS_MISC_CTL_1_SPKR_ENABLE 0x10 341 #define PCIC_CIRRUS_FIFO_CTL 0x17 342 #define PCIC_CIRRUS_FIFO_CTL_EMPTY 0x80 343 #define PCIC_CIRRUS_FIFO_CTL_FLUSH 0x80 345 #define PCIC_CIRRUS_MISC_CTL_2 0x1E 346 #define PCIC_CIRRUS_MISC_CTL_2_SUSPEND 0x04 347 #define PCIC_CIRRUS_MISC_CTL_2_LP_DYNAMIC_MODE 0x02 349 #define PCIC_CIRRUS_CHIP_INFO 0x1F 350 #define PCIC_CIRRUS_CHIP_INFO_CHIP_ID 0xC0 351 #define PCIC_CIRRUS_CHIP_INFO_SLOTS 0x20 352 #define PCIC_CIRRUS_CHIP_INFO_REV 0x1F 354 #define PCIC_CIRRUS_EXTENDED_INDEX 0x2E 355 #define PCIC_CIRRUS_EXTENDED_DATA 0x2F 357 #define PCIC_CIRRUS_EXT_CONTROL_1 0x03 358 #define PCIC_CIRRUS_EXT_CONTROL_1_PCI_INTR_MASK 0x18 360 #define PCIC_CIRRUS_PROD_ID 0x35 361 #define PCIC_CIRRUS_PROD_ID_FAM_MASK 0xF0 362 #define PCIC_CIRRUS_PROD_ID_FAM_PD6729 0x20 363 #define PCIC_CIRRUS_PROD_ID_PROD_MASK 0x0F 364 #define PCIC_CIRRUS_PROD_ID_PROD_PD6729 0x00 366 #define PCIC_RICOH_REG_CHIP_ID 0x3A 367 #define PCIC_RICOH_CHIP_ID_5C296 0x32 368 #define PCIC_RICOH_CHIP_ID_5C396 0xB2 369 #define PCIC_RICOH_REG_MCR2 0x2F 370 #define PCIC_RICOH_MCR2_VCC_DIRECT 0x08 371 #define PCIC_RICOH_MCR2_VCC_SEL_MASK 0x01 372 #define PCIC_RICOH_MCR2_VCC_SEL_3V 0x01 373 #define PCIC_RICOH_MCR2_VCC_SEL_5V 0x00
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