50 #define DYNTRANS_PAGESIZE 8192 74 while (cpu_type_defs[i].
name != NULL) {
75 if (strcasecmp(cpu_type_defs[i].
name, cpu_type_name) == 0) {
80 if (cpu_type_defs[i].
name == NULL)
122 memset(&templ, 0,
sizeof(templ));
156 while (tdefs[i].
name != NULL) {
158 for (j=13 -
strlen(tdefs[i].name); j>0; j--)
161 if ((i % 4) == 0 || tdefs[i].name == NULL)
184 debug(
"cpu%i:\t pc = 0x%016" PRIx64, x, (uint64_t) cpu->
pc);
185 debug(
" <%s>\n", symbol != NULL? symbol :
" no symbol ");
187 int r = (i >> 1) + ((i & 1) << 4);
189 debug(
"cpu%i:\t", x);
191 debug(
"%3s = 0x%016" PRIx64, alpha_regname[r],
237 static void alpha_print_imm16_disp(
int imm,
int rb)
250 debug(
"(%s)", alpha_regname[rb]);
267 int running, uint64_t dumpaddr)
270 uint64_t offset, tmp;
271 int opcode, ra, rb, func, rc, imm, floating, rbrc = 0, indir = 0;
272 const char *
symbol, *mnem = NULL;
273 char palcode_name[30];
280 if (symbol != NULL && offset == 0)
281 debug(
"<%s>\n", symbol);
286 debug(
"%016" PRIx64
": ", (uint64_t) dumpaddr);
288 iw = ib[0] + (ib[1]<<8) + (ib[2]<<16) + (ib[3]<<24);
289 debug(
"%08x\t", (
int)iw);
292 ra = (iw >> 21) & 31;
293 rb = (iw >> 16) & 31;
294 func = (iw >> 5) & 0x7ff;
301 sizeof(palcode_name));
302 debug(
"call_pal %s\n", palcode_name);
306 debug(
"lda%s\t%s,", opcode == 9?
"h" :
"", alpha_regname[ra]);
307 alpha_print_imm16_disp(imm, rb);
334 case 0x0a: mnem =
"ldbu";
break;
335 case 0x0b: mnem =
"ldq_u";
break;
336 case 0x0c: mnem =
"ldwu";
break;
337 case 0x0d: mnem =
"stw";
break;
338 case 0x0e: mnem =
"stb";
break;
339 case 0x0f: mnem =
"stq_u";
break;
340 case 0x20: mnem =
"ldf"; floating = 1;
break;
341 case 0x21: mnem =
"ldg"; floating = 1;
break;
342 case 0x22: mnem =
"lds"; floating = 1;
break;
343 case 0x23: mnem =
"ldt"; floating = 1;
break;
344 case 0x24: mnem =
"stf"; floating = 1;
break;
345 case 0x25: mnem =
"stg"; floating = 1;
break;
346 case 0x26: mnem =
"sts"; floating = 1;
break;
347 case 0x27: mnem =
"stt"; floating = 1;
break;
348 case 0x28: mnem =
"ldl";
break;
349 case 0x29: mnem =
"ldq";
break;
350 case 0x2a: mnem =
"ldl_l";
break;
351 case 0x2b: mnem =
"ldq_l";
break;
352 case 0x2c: mnem =
"stl";
break;
353 case 0x2d: mnem =
"stq";
break;
354 case 0x2e: mnem =
"stl_c";
break;
355 case 0x2f: mnem =
"stq_c";
break;
364 debug(
"%s,", alpha_regname[ra]);
365 alpha_print_imm16_disp(imm, rb);
370 switch (func & 0x7f) {
371 case 0x00: mnem =
"addl";
break;
372 case 0x02: mnem =
"s4addl";
break;
373 case 0x09: mnem =
"subl";
break;
374 case 0x0b: mnem =
"s4subl";
break;
375 case 0x0f: mnem =
"cmpbge";
break;
376 case 0x12: mnem =
"s8addl";
break;
377 case 0x1b: mnem =
"s8subl";
break;
378 case 0x1d: mnem =
"cmpult";
break;
379 case 0x20: mnem =
"addq";
break;
380 case 0x22: mnem =
"s4addq";
break;
381 case 0x29: mnem =
"subq";
break;
382 case 0x2b: mnem =
"s4subq";
break;
383 case 0x2d: mnem =
"cmpeq";
break;
384 case 0x32: mnem =
"s8addq";
break;
385 case 0x3b: mnem =
"s8subq";
break;
386 case 0x3d: mnem =
"cmpule";
break;
387 case 0x40: mnem =
"addl/v";
break;
388 case 0x49: mnem =
"subl/v";
break;
389 case 0x4d: mnem =
"cmplt";
break;
390 case 0x60: mnem =
"addq/v";
break;
391 case 0x69: mnem =
"subq/v";
break;
392 case 0x6d: mnem =
"cmple";
break;
393 default:
debug(
"UNIMPLEMENTED opcode 0x%x func 0x%x\n",
399 debug(
"%s\t%s,0x%x,%s\n", mnem,
400 alpha_regname[ra], (rb << 3) + (func >> 8),
403 debug(
"%s\t%s,%s,%s\n", mnem, alpha_regname[ra],
404 alpha_regname[rb], alpha_regname[rc]);
407 switch (func & 0x7f) {
408 case 0x000: mnem =
"and";
break;
409 case 0x008: mnem =
"andnot";
break;
410 case 0x014: mnem =
"cmovlbs";
break;
411 case 0x016: mnem =
"cmovlbc";
break;
412 case 0x020: mnem =
"or";
break;
413 case 0x024: mnem =
"cmoveq";
break;
414 case 0x026: mnem =
"cmovne";
break;
415 case 0x028: mnem =
"ornot";
break;
416 case 0x040: mnem =
"xor";
break;
417 case 0x044: mnem =
"cmovlt";
break;
418 case 0x046: mnem =
"cmovge";
break;
419 case 0x048: mnem =
"eqv";
break;
420 case 0x061: mnem =
"amask";
break;
421 case 0x064: mnem =
"cmovle";
break;
422 case 0x066: mnem =
"cmovgt";
break;
423 case 0x06c: mnem =
"implver";
break;
424 default:
debug(
"UNIMPLEMENTED opcode 0x%x func 0x%x\n",
435 debug(
"clr\t%s\n", alpha_regname[rc]);
437 debug(
"mov\t%s,%s\n", alpha_regname[rb],
440 debug(
"mov\t%s,%s\n", alpha_regname[ra],
442 }
else if (func == 0x1ec) {
444 debug(
"%s\t%s\n", mnem, alpha_regname[rc]);
445 }
else if (func & 0x80)
446 debug(
"%s\t%s,0x%x,%s\n", mnem,
447 alpha_regname[ra], (rb << 3) + (func >> 8),
450 debug(
"%s\t%s,%s,%s\n", mnem, alpha_regname[ra],
451 alpha_regname[rb], alpha_regname[rc]);
454 switch (func & 0x7f) {
455 case 0x02: mnem =
"mskbl";
break;
456 case 0x06: mnem =
"extbl";
break;
457 case 0x0b: mnem =
"insbl";
break;
458 case 0x12: mnem =
"mskwl";
break;
459 case 0x16: mnem =
"extwl";
break;
460 case 0x1b: mnem =
"inswl";
break;
461 case 0x22: mnem =
"mskll";
break;
462 case 0x26: mnem =
"extll";
break;
463 case 0x2b: mnem =
"insll";
break;
464 case 0x30: mnem =
"zap";
break;
465 case 0x31: mnem =
"zapnot";
break;
466 case 0x32: mnem =
"mskql";
break;
467 case 0x34: mnem =
"srl";
break;
468 case 0x36: mnem =
"extql";
break;
469 case 0x39: mnem =
"sll";
break;
470 case 0x3b: mnem =
"insql";
break;
471 case 0x3c: mnem =
"sra";
break;
472 case 0x52: mnem =
"mskwh";
break;
473 case 0x57: mnem =
"inswh";
break;
474 case 0x5a: mnem =
"extwh";
break;
475 case 0x62: mnem =
"msklh";
break;
476 case 0x67: mnem =
"inslh";
break;
477 case 0x6a: mnem =
"extlh";
break;
478 case 0x72: mnem =
"mskqh";
break;
479 case 0x77: mnem =
"insqh";
break;
480 case 0x7a: mnem =
"extqh";
break;
481 default:
debug(
"UNIMPLEMENTED opcode 0x%x func 0x%x\n",
487 debug(
"%s\t%s,0x%x,%s\n", mnem,
488 alpha_regname[ra], (rb << 3) + (func >> 8),
491 debug(
"%s\t%s,%s,%s\n", mnem, alpha_regname[ra],
492 alpha_regname[rb], alpha_regname[rc]);
495 switch (func & 0x7f) {
496 case 0x00: mnem =
"mull";
break;
497 case 0x20: mnem =
"mulq";
break;
498 case 0x30: mnem =
"umulh";
break;
499 case 0x40: mnem =
"mull/v";
break;
500 case 0x60: mnem =
"mulq/v";
break;
501 default:
debug(
"UNIMPLEMENTED opcode 0x%x func 0x%x\n",
507 debug(
"%s\t%s,0x%x,%s\n", mnem,
508 alpha_regname[ra], (rb << 3) + (func >> 8),
511 debug(
"%s\t%s,%s,%s\n", mnem, alpha_regname[ra],
512 alpha_regname[rb], alpha_regname[rc]);
515 switch (func & 0x7ff) {
516 case 0x02f: mnem =
"cvttq/c"; rbrc = 1;
break;
517 case 0x080: mnem =
"adds";
break;
518 case 0x081: mnem =
"subs";
break;
519 case 0x082: mnem =
"muls";
break;
520 case 0x083: mnem =
"XXXx083";
break;
521 case 0x0a0: mnem =
"addt";
break;
522 case 0x0a1: mnem =
"subt";
break;
523 case 0x0a2: mnem =
"mult";
break;
524 case 0x0a3: mnem =
"divt";
break;
525 case 0x0a5: mnem =
"cmpteq";
break;
526 case 0x0a6: mnem =
"cmptlt";
break;
527 case 0x0a7: mnem =
"cmptle";
break;
528 case 0x0be: mnem =
"cvtqt"; rbrc = 1;
break;
529 default:
debug(
"UNIMPLEMENTED opcode 0x%x func 0x%x\n",
535 debug(
"%s\tf%i,f%i\n", mnem, rb, rc);
537 debug(
"%s\tf%i,f%i,f%i\n", mnem, ra, rb, rc);
540 switch (func & 0x7ff) {
541 case 0x020: mnem =
"fabs"; rbrc = 1;
break;
542 case 0x021: mnem =
"fneg"; rbrc = 1;
break;
543 default:
debug(
"UNIMPLEMENTED opcode 0x%x func 0x%x\n",
548 if ((func & 0x7ff) == 0x020 && ra == 31 && rb == 31)
549 debug(
"fclr\tf%i\n", rc);
551 debug(
"%s\tf%i,f%i\n", mnem, rb, rc);
553 debug(
"%s\tf%i,f%i,f%i\n", mnem, ra, rb, rc);
556 switch (iw & 0xffff) {
557 case 0x0000: mnem =
"trapb";
break;
558 case 0x0400: mnem =
"excb";
break;
559 case 0x4000: mnem =
"mb";
break;
560 case 0x4400: mnem =
"wmb";
break;
561 case 0x8000: mnem =
"fetch"; indir = 1;
break;
562 case 0xa000: mnem =
"fetch_m"; indir = 1;
break;
563 case 0xc000: mnem =
"rpcc";
break;
564 case 0xe000: mnem =
"rc";
break;
565 case 0xe800: mnem =
"ecb"; indir = 1;
break;
566 case 0xf000: mnem =
"rs";
break;
567 case 0xf800: mnem =
"wh64"; indir = 1;
break;
568 default:
debug(
"UNIMPLEMENTED opcode 0x%x func 0x%x\n",
574 if ((iw & 0xffff) >= 0x8000) {
577 debug(
"(%s)", alpha_regname[rb]);
579 debug(
"%s", alpha_regname[ra]);
586 tmp |= 0xffffffffffffc000ULL;
588 tmp += dumpaddr +
sizeof(uint32_t);
589 switch ((iw >> 14) & 3) {
591 case 1:
if (((iw >> 14) & 3) == 0)
595 debug(
"\t%s,", alpha_regname[ra]);
596 debug(
"(%s),", alpha_regname[rb]);
597 debug(
"0x%" PRIx64, (uint64_t) tmp);
601 debug(
"\t<%s>", symbol);
603 case 2:
debug(
"ret");
605 default:
fatal(
"unimpl JSR!");
613 tmp |= 0xffffffffffe00000ULL;
615 tmp += dumpaddr +
sizeof(uint32_t);
616 debug(
"%s\t", opcode==0x30?
"br" :
"bsr");
618 debug(
"%s,", alpha_regname[ra]);
619 debug(
"0x%" PRIx64, (uint64_t) tmp);
623 debug(
"\t<%s>", symbol);
638 case 0x31: mnem =
"fbeq"; floating = 1;
break;
639 case 0x35: mnem =
"fbne"; floating = 1;
break;
640 case 0x38: mnem =
"blbc";
break;
641 case 0x39: mnem =
"beq";
break;
642 case 0x3a: mnem =
"blt";
break;
643 case 0x3b: mnem =
"ble";
break;
644 case 0x3c: mnem =
"blbs";
break;
645 case 0x3d: mnem =
"bne";
break;
646 case 0x3e: mnem =
"bge";
break;
647 case 0x3f: mnem =
"bgt";
break;
651 tmp |= 0xffffffffffe00000ULL;
653 tmp += dumpaddr +
sizeof(uint32_t);
658 debug(
"%s,", alpha_regname[ra]);
659 debug(
"0x%" PRIx64, (uint64_t) tmp);
663 debug(
"\t<%s>", symbol);
666 default:
debug(
"UNIMPLEMENTED opcode 0x%x\n", opcode);
669 return sizeof(uint32_t);
673 #define MEMORY_RW alpha_userland_memory_rw void fatal(const char *fmt,...)
void(* interrupt_assert)(struct interrupt *)
int(* translate_v2p)(struct cpu *, uint64_t vaddr, uint64_t *return_paddr, int flags)
#define ALPHA_CPU_TYPE_DEFS
int store_32bit_word(struct cpu *cpu, uint64_t addr, uint64_t data32)
int alpha_translate_v2p(struct cpu *cpu, uint64_t vaddr, uint64_t *return_paddr, int flags)
void interrupt_handler_register(struct interrupt *templ)
void(* interrupt_deassert)(struct interrupt *)
int alpha_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib, int running, uint64_t dumpaddr)
int alpha_cpu_new(struct cpu *cpu, struct memory *mem, struct machine *machine, int cpu_id, char *cpu_type_name)
int(* run_instr)(struct cpu *cpu)
void alpha_invalidate_translation_caches(struct cpu *cpu, uint64_t, int)
void alpha_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page)
char * get_symbol_name(struct symbol_context *, uint64_t addr, uint64_t *offset)
#define EMUL_LITTLE_ENDIAN
void alpha_invalidate_code_translation(struct cpu *cpu, uint64_t, int)
void alpha_palcode_name(uint32_t palcode, char *buf, size_t buflen)
int alpha_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags)
int(* memory_rw)(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags)
void alpha_irq_interrupt_deassert(struct interrupt *interrupt)
void alpha_cpu_tlbdump(struct machine *m, int x, int rawflag)
void alpha_cpu_list_available_types(void)
int alpha_run_instr(struct cpu *cpu)
struct alpha_cpu_type_def cpu_type
void COMBINE() strlen(struct cpu *cpu, struct arm_instr_call *ic, int low_addr)
void alpha_irq_interrupt_assert(struct interrupt *interrupt)
struct symbol_context symbol_context
void alpha_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
void(* update_translation_table)(struct cpu *, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page)
void(* invalidate_code_translation)(struct cpu *, uint64_t paddr, int flags)
uint64_t kentry[N_ALPHA_KENTRY]
#define CPU_SETTINGS_ADD_REGISTER64(name, var)
void alpha_cpu_dumpinfo(struct cpu *cpu)
void(* invalidate_translation_caches)(struct cpu *, uint64_t paddr, int flags)