54 #define TICK_STEPS_SHIFT 14 57 #define DEV_PS2_GIF_FAKE_BASE 0x50000000 59 #define N_PS2_DMA_CHANNELS 10 60 #define N_PS2_TIMERS 4 83 #define DEV_PS2_LENGTH 0x10000 169 uint64_t idata = 0, odata = 0;
177 if (relative_addr >= 0x8000 && relative_addr < 0x8000 +
DMAC_REGSIZE) {
178 regnr = (relative_addr - 0x8000) / 16;
191 timer_nr = (relative_addr & 0x1800) >> 11;
195 switch (relative_addr) {
203 debug(
"[ ps2: read timer %i count: 0x%llx ]\n",
204 timer_nr, (
long long)odata);
207 debug(
"[ ps2: write timer %i count: 0x%llx ]\n",
208 timer_nr, (
long long)idata);
214 debug(
"[ ps2: read timer %i mode: 0x%llx ]\n",
215 timer_nr, (
long long)odata);
218 debug(
"[ ps2: write timer %i mode: 0x%llx ]\n",
219 timer_nr, (
long long)idata);
225 debug(
"[ ps2: read timer %i comp: 0x%llx ]\n",
226 timer_nr, (
long long)odata);
229 debug(
"[ ps2: write timer %i comp: 0x%llx ]\n",
230 timer_nr, (
long long)idata);
236 debug(
"[ ps2: read timer %i hold: 0x%llx ]\n",
237 timer_nr, (
long long)odata);
239 fatal(
"[ WARNING: ps2: read from non-" 240 "existant timer %i hold register ]\n");
243 debug(
"[ ps2: write timer %i hold: 0x%llx ]\n",
244 timer_nr, (
long long)idata);
246 fatal(
"[ WARNING: ps2: write to " 247 "non-existant timer %i hold register ]\n",
266 unsigned char *copy_buf;
268 debug(
"[ ps2: dmac [ch2] transfer addr=" 269 "0x%016llx len=0x%lx ]\n", (
long long)
286 idata &= ~D_CHCR_STR;
291 debug(
"[ ps2: dmac [ch2] stopping " 307 uint32_t oldmask = d->
dmac_reg[regnr] & 0xffff0000;
312 if (((d->
dmac_reg[regnr] & 0xffff) &
313 ((d->
dmac_reg[regnr]>>16) & 0xffff)) == 0) {
320 odata |= (odata << 16);
327 debug(
"[ ps2: read from Interrupt Register:" 328 " 0x%llx ]\n", (
long long)odata);
334 debug(
"[ ps2: write to Interrupt Register: " 335 "0x%llx ]\n", (
long long)idata);
361 debug(
"[ ps2: read from SBUS SMFLG:" 362 " 0x%llx ]\n", (
long long)odata);
365 debug(
"[ ps2: write to SBUS SMFLG:" 366 " 0x%llx ]\n", (
long long)idata);
375 debug(
"[ ps2: read from addr 0x%x: 0x%llx ]\n",
376 (
int)relative_addr, (
long long)odata);
378 debug(
"[ ps2: write to addr 0x%x: 0x%llx ]\n",
379 (
int)relative_addr, (
long long)idata);
398 memset(d, 0,
sizeof(
struct ps2_data));
415 for (i=0; i<16; i++) {
416 snprintf(n,
sizeof(n),
"%s.ps2_intr.%i",
418 memset(&templ, 0,
sizeof(templ));
426 for (i=0; i<16; i++) {
427 snprintf(n,
sizeof(n),
"%s.ps2_dmac.%i",
429 memset(&templ, 0,
sizeof(templ));
437 for (i=0; i<2; i++) {
438 snprintf(n,
sizeof(n),
"%s.ps2_sbus.%i",
440 memset(&templ, 0,
sizeof(templ));
460 snprintf(n,
sizeof(n),
"%s.ps2_intr.%i",
uint64_t memory_readmax64(struct cpu *cpu, unsigned char *buf, int len)
void fatal(const char *fmt,...)
uint64_t dmac_reg[DMAC_REGSIZE/0x10]
void(* interrupt_assert)(struct interrupt *)
void ps2_dmac_interrupt_deassert(struct interrupt *interrupt)
struct interrupt dma_channel2_irq
uint32_t timer_count[N_PS2_TIMERS]
void interrupt_handler_register(struct interrupt *templ)
void(* interrupt_deassert)(struct interrupt *)
struct interrupt intr_irq
void ps2_dmac_interrupt_assert(struct interrupt *interrupt)
#define CHECK_ALLOCATION(ptr)
int(* memory_rw)(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags)
uint64_t other_memory_base[N_PS2_DMA_CHANNELS]
#define INTERRUPT_ASSERT(istruct)
struct interrupt dmac_irq
void ps2_sbus_interrupt_deassert(struct interrupt *interrupt)
#define INTERRUPT_CONNECT(name, istruct)
#define N_PS2_DMA_CHANNELS
void ps2_intr_interrupt_deassert(struct interrupt *interrupt)
void memory_writemax64(struct cpu *cpu, unsigned char *buf, int len, uint64_t data)
uint32_t timer_hold[N_PS2_TIMERS]
void memory_device_register(struct memory *mem, const char *, uint64_t baseaddr, uint64_t len, int(*f)(struct cpu *, struct memory *, uint64_t, unsigned char *, size_t, int, void *), void *extra, int flags, unsigned char *dyntrans_data)
uint32_t timer_mode[N_PS2_TIMERS]
struct interrupt sbus_irq
struct interrupt timer_irq[N_PS2_TIMERS]
void machine_add_tickfunction(struct machine *machine, void(*func)(struct cpu *, void *), void *extra, int clockshift)
void ps2_intr_interrupt_assert(struct interrupt *interrupt)
uint32_t timer_comp[N_PS2_TIMERS]
void ps2_sbus_interrupt_assert(struct interrupt *interrupt)
#define DEV_PS2_GIF_FAKE_BASE
#define INTERRUPT_DEASSERT(istruct)