ppc_pte.h File Reference

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Macros
ppc_pte.h File Reference

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Macros

#define PTE_VALID   0x80000000
 
#define PTE_VSID   0x7fffff80
 
#define PTE_VSID_SHFT   7
 
#define PTE_VSID_LEN   24
 
#define PTE_HID   0x00000040
 
#define PTE_API   0x0000003f
 
#define PTE_API_SHFT   0
 
#define PTE_RPGN   (~0xfffL)
 
#define PTE_RPGN_SHFT   12
 
#define PTE_REF   0x00000100
 
#define PTE_CHG   0x00000080
 
#define PTE_W   0x00000040 /* 1 = write-through, 0 = write-back */
 
#define PTE_I   0x00000020 /* cache inhibit */
 
#define PTE_M   0x00000010 /* memory coherency enable */
 
#define PTE_G   0x00000008 /* guarded region (not on 601) */
 
#define PTE_WIMG   (PTE_W|PTE_I|PTE_M|PTE_G)
 
#define PTE_IG   (PTE_I|PTE_G)
 
#define PTE_PP   0x00000003
 
#define PTE_SO   0x00000000 /* Super. Only (U: XX, S: RW) */
 
#define PTE_SW   0x00000001 /* Super. Write-Only (U: RO, S: RW) */
 
#define PTE_BW   0x00000002 /* Supervisor (U: RW, S: RW) */
 
#define PTE_BR   0x00000003 /* Both Read Only (U: RO, S: RO) */
 
#define PTE_RW   PTE_BW
 
#define PTE_RO   PTE_BR
 
#define PTE_EXEC   0x00000200 /* pseudo bit; page is exec */
 
#define ADDR_SR   (~0x0fffffffL)
 
#define ADDR_SR_SHFT   28
 
#define ADDR_PIDX   0x0ffff000
 
#define ADDR_PIDX_SHFT   12
 
#define ADDR_API_SHFT   22 /* API is 6 bits */
 
#define ADDR_POFF   0x00000fff
 
#define SR_KEY_LEN   4 /* 16 segment registers */
 
#define SR_TYPE   0x80000000 /* T=0 selects memory format */
 
#define SR_SUKEY   0x40000000 /* Supervisor protection key */
 
#define SR_PRKEY   0x20000000 /* User protection key */
 
#define SR_NOEXEC   0x10000000 /* No-execute protection bit */
 
#define SR_VSID_SHFT   0 /* Starts at LSB */
 
#define SR_VSID_WIDTH   24 /* Goes for 24 bits */
 
#define SR_VSID   (((1L << SR_VSID_WIDTH) - 1) << SR_VSID_SHFT)
 

Macro Definition Documentation

◆ ADDR_API_SHFT

#define ADDR_API_SHFT   22 /* API is 6 bits */

Definition at line 107 of file ppc_pte.h.

◆ ADDR_PIDX

#define ADDR_PIDX   0x0ffff000

Definition at line 102 of file ppc_pte.h.

◆ ADDR_PIDX_SHFT

#define ADDR_PIDX_SHFT   12

Definition at line 103 of file ppc_pte.h.

◆ ADDR_POFF

#define ADDR_POFF   0x00000fff

Definition at line 109 of file ppc_pte.h.

◆ ADDR_SR

#define ADDR_SR   (~0x0fffffffL)

Definition at line 100 of file ppc_pte.h.

◆ ADDR_SR_SHFT

#define ADDR_SR_SHFT   28

Definition at line 101 of file ppc_pte.h.

◆ PTE_API

#define PTE_API   0x0000003f

Definition at line 71 of file ppc_pte.h.

◆ PTE_API_SHFT

#define PTE_API_SHFT   0

Definition at line 72 of file ppc_pte.h.

◆ PTE_BR

#define PTE_BR   0x00000003 /* Both Read Only (U: RO, S: RO) */

Definition at line 91 of file ppc_pte.h.

◆ PTE_BW

#define PTE_BW   0x00000002 /* Supervisor (U: RW, S: RW) */

Definition at line 90 of file ppc_pte.h.

◆ PTE_CHG

#define PTE_CHG   0x00000080

Definition at line 80 of file ppc_pte.h.

◆ PTE_EXEC

#define PTE_EXEC   0x00000200 /* pseudo bit; page is exec */

Definition at line 95 of file ppc_pte.h.

◆ PTE_G

#define PTE_G   0x00000008 /* guarded region (not on 601) */

Definition at line 84 of file ppc_pte.h.

◆ PTE_HID

#define PTE_HID   0x00000040

Definition at line 70 of file ppc_pte.h.

◆ PTE_I

#define PTE_I   0x00000020 /* cache inhibit */

Definition at line 82 of file ppc_pte.h.

◆ PTE_IG

#define PTE_IG   (PTE_I|PTE_G)

Definition at line 86 of file ppc_pte.h.

◆ PTE_M

#define PTE_M   0x00000010 /* memory coherency enable */

Definition at line 83 of file ppc_pte.h.

◆ PTE_PP

#define PTE_PP   0x00000003

Definition at line 87 of file ppc_pte.h.

◆ PTE_REF

#define PTE_REF   0x00000100

Definition at line 79 of file ppc_pte.h.

◆ PTE_RO

#define PTE_RO   PTE_BR

Definition at line 93 of file ppc_pte.h.

◆ PTE_RPGN

#define PTE_RPGN   (~0xfffL)

Definition at line 77 of file ppc_pte.h.

◆ PTE_RPGN_SHFT

#define PTE_RPGN_SHFT   12

Definition at line 78 of file ppc_pte.h.

◆ PTE_RW

#define PTE_RW   PTE_BW

Definition at line 92 of file ppc_pte.h.

◆ PTE_SO

#define PTE_SO   0x00000000 /* Super. Only (U: XX, S: RW) */

Definition at line 88 of file ppc_pte.h.

◆ PTE_SW

#define PTE_SW   0x00000001 /* Super. Write-Only (U: RO, S: RW) */

Definition at line 89 of file ppc_pte.h.

◆ PTE_VALID

#define PTE_VALID   0x80000000

Definition at line 66 of file ppc_pte.h.

◆ PTE_VSID

#define PTE_VSID   0x7fffff80

Definition at line 67 of file ppc_pte.h.

◆ PTE_VSID_LEN

#define PTE_VSID_LEN   24

Definition at line 69 of file ppc_pte.h.

◆ PTE_VSID_SHFT

#define PTE_VSID_SHFT   7

Definition at line 68 of file ppc_pte.h.

◆ PTE_W

#define PTE_W   0x00000040 /* 1 = write-through, 0 = write-back */

Definition at line 81 of file ppc_pte.h.

◆ PTE_WIMG

#define PTE_WIMG   (PTE_W|PTE_I|PTE_M|PTE_G)

Definition at line 85 of file ppc_pte.h.

◆ SR_KEY_LEN

#define SR_KEY_LEN   4 /* 16 segment registers */

Definition at line 152 of file ppc_pte.h.

◆ SR_NOEXEC

#define SR_NOEXEC   0x10000000 /* No-execute protection bit */

Definition at line 156 of file ppc_pte.h.

Referenced by ppc_cpu_register_dump().

◆ SR_PRKEY

#define SR_PRKEY   0x20000000 /* User protection key */

Definition at line 155 of file ppc_pte.h.

Referenced by ppc_cpu_register_dump().

◆ SR_SUKEY

#define SR_SUKEY   0x40000000 /* Supervisor protection key */

Definition at line 154 of file ppc_pte.h.

Referenced by ppc_cpu_register_dump().

◆ SR_TYPE

#define SR_TYPE   0x80000000 /* T=0 selects memory format */

Definition at line 153 of file ppc_pte.h.

Referenced by ppc_cpu_register_dump().

◆ SR_VSID

#define SR_VSID   (((1L << SR_VSID_WIDTH) - 1) << SR_VSID_SHFT)

Definition at line 163 of file ppc_pte.h.

◆ SR_VSID_SHFT

#define SR_VSID_SHFT   0 /* Starts at LSB */

Definition at line 157 of file ppc_pte.h.

◆ SR_VSID_WIDTH

#define SR_VSID_WIDTH   24 /* Goes for 24 bits */

Definition at line 158 of file ppc_pte.h.


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