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Macros | |
#define | ZSRR_IVEC 2 /* interrupt vector (channel 0) */ |
#define | ZSRR_IPEND 3 /* interrupt pending (ch. 0 only) */ |
#define | ZSRR_TXSYNC 6 /* sync transmit char (monosync mode) */ |
#define | ZSRR_RXSYNC 7 /* sync receive char (monosync mode) */ |
#define | ZSRR_SYNCLO 6 /* sync low byte (bisync mode) */ |
#define | ZSRR_SYNCHI 7 /* sync high byte (bisync mode) */ |
#define | ZSRR_SDLC_ADDR 6 /* SDLC address (SDLC mode) */ |
#define | ZSRR_SDLC_FLAG 7 /* SDLC flag 0x7E (SDLC mode) */ |
#define | ZSRR_BAUDLO 12 /* baud rate generator (low half) */ |
#define | ZSRR_BAUDHI 13 /* baud rate generator (high half) */ |
#define | ZSRR_ENHANCED 14 /* read address of WR7' - yes, it's not 7!*/ |
#define | ZSWR_IVEC 2 /* interrupt vector (shared) */ |
#define | ZSWR_TXSYNC 6 /* sync transmit char (monosync mode) */ |
#define | ZSWR_RXSYNC 7 /* sync receive char (monosync mode) */ |
#define | ZSWR_SYNCLO 6 /* sync low byte (bisync mode) */ |
#define | ZSWR_SYNCHI 7 /* sync high byte (bisync mode) */ |
#define | ZSWR_SDLC_ADDR 6 /* SDLC address (SDLC mode) */ |
#define | ZSWR_SDLC_FLAG 7 /* SDLC flag 0x7E (SDLC mode) */ |
#define | ZSWR_BAUDLO 12 /* baud rate generator (low half) */ |
#define | ZSWR_BAUDHI 13 /* baud rate generator (high half) */ |
#define | ZSWR_ENHANCED 7 /* write address of WR7' */ |
#define | ZSM_RESET_TXUEOM 0xc0 /* reset xmit underrun / eom latch */ |
#define | ZSM_RESET_TXCRC 0x80 /* reset xmit crc generator */ |
#define | ZSM_RESET_RXCRC 0x40 /* reset recv crc checker */ |
#define | ZSM_NULL 0x00 /* nothing special */ |
#define | ZSM_RESET_IUS 0x38 /* reset interrupt under service */ |
#define | ZSM_RESET_ERR 0x30 /* reset error cond */ |
#define | ZSM_RESET_TXINT 0x28 /* reset xmit interrupt pending */ |
#define | ZSM_EI_NEXTRXC 0x20 /* enable int. on next rcvd char */ |
#define | ZSM_SEND_ABORT 0x18 /* send abort (SDLC) */ |
#define | ZSM_RESET_STINT 0x10 /* reset external/status interrupt */ |
#define | ZSM_POINTHIGH 0x08 /* `point high' (use r8-r15) */ |
#define | ZSM_NULL 0x00 /* nothing special */ |
#define | ZSWR0_RESET_EOM ZSM_RESET_TXUEOM |
#define | ZSWR0_RESET_TXCRC ZSM_RESET_TXCRC |
#define | ZSWR0_RESET_RXCRC ZSM_RESET_RXCRC |
#define | ZSWR0_CLR_INTR ZSM_RESET_IUS |
#define | ZSWR0_RESET_ERRORS ZSM_RESET_ERR |
#define | ZSWR0_EI_NEXTRXC ZSM_EI_NEXTRXC |
#define | ZSWR0_SEND_ABORT ZSM_SEND_ABORT |
#define | ZSWR0_RESET_STATUS ZSM_RESET_STINT |
#define | ZSWR0_RESET_TXINT ZSM_RESET_TXINT |
#define | ZSWR1_REQ_WAIT 0x80 /* WAIT*-REQ* pin gives WAIT* */ |
#define | ZSWR1_REQ_REQ 0xc0 /* WAIT*-REQ* pin gives REQ* */ |
#define | ZSWR1_REQ_TX 0x00 /* WAIT*-REQ* pin follows xmit buf */ |
#define | ZSWR1_REQ_RX 0x20 /* WAIT*-REQ* pin follows recv buf */ |
#define | ZSWR1_RIE_NONE 0x00 /* disable rxint entirely */ |
#define | ZSWR1_RIE_FIRST 0x08 /* rxint on first char & on S.C. */ |
#define | ZSWR1_RIE 0x10 /* rxint per char & on S.C. */ |
#define | ZSWR1_RIE_SPECIAL_ONLY 0x18 /* rxint on S.C. only */ |
#define | ZSWR1_PE_SC 0x04 /* parity error is special condition */ |
#define | ZSWR1_TIE 0x02 /* transmit interrupt enable */ |
#define | ZSWR1_SIE 0x01 /* external/status interrupt enable */ |
#define | ZSWR1_IMASK 0x1F /* mask of all itr. enable bits. */ |
#define | ZSWR1_REQ_ENABLE (ZSWR1_REQ_WAIT | ZSWR1_REQ_TX) |
#define | ZSWR3_RX_5 0x00 /* receive 5 bits per char */ |
#define | ZSWR3_RX_7 0x40 /* receive 7 bits per char */ |
#define | ZSWR3_RX_6 0x80 /* receive 6 bits per char */ |
#define | ZSWR3_RX_8 0xc0 /* receive 8 bits per char */ |
#define | ZSWR3_RXSIZE 0xc0 /* receive char size mask */ |
#define | ZSWR3_HFC 0x20 /* hardware flow control */ |
#define | ZSWR3_HUNT 0x10 /* enter hunt mode */ |
#define | ZSWR3_RXCRC_ENABLE 0x08 /* enable recv crc calculation */ |
#define | ZSWR3_ADDR_SEARCH_MODE 0x04 /* address search mode (SDLC only) */ |
#define | ZSWR3_SDLC_SHORT_ADDR 0x02 /* short address mode (SDLC only) */ |
#define | ZSWR3_SYNC_LOAD_INH 0x02 /* sync character load inhibit */ |
#define | ZSWR3_RX_ENABLE 0x01 /* receiver enable */ |
#define | ZSWR4_CLK_X1 0x00 /* clock divisor = 1 */ |
#define | ZSWR4_CLK_X16 0x40 /* clock divisor = 16 */ |
#define | ZSWR4_CLK_X32 0x80 /* clock divisor = 32 */ |
#define | ZSWR4_CLK_X64 0xc0 /* clock divisor = 64 */ |
#define | ZSWR4_CLK_MASK 0xc0 /* clock divisor mask */ |
#define | ZSWR4_MONOSYNC 0x00 /* 8 bit sync char (sync only) */ |
#define | ZSWR4_BISYNC 0x10 /* 16 bit sync char (sync only) */ |
#define | ZSWR4_SDLC 0x20 /* SDLC mode */ |
#define | ZSWR4_EXTSYNC 0x30 /* external sync mode */ |
#define | ZSWR4_SYNC_MASK 0x30 /* sync mode bit mask */ |
#define | ZSWR4_SYNCMODE 0x00 /* no stop bit (sync mode only) */ |
#define | ZSWR4_ONESB 0x04 /* 1 stop bit */ |
#define | ZSWR4_1P5SB 0x08 /* 1.5 stop bits (clk cannot be 1x) */ |
#define | ZSWR4_TWOSB 0x0c /* 2 stop bits */ |
#define | ZSWR4_SBMASK 0x0c /* mask of all stop bits */ |
#define | ZSWR4_EVENP 0x02 /* check for even parity */ |
#define | ZSWR4_PARENB 0x01 /* enable parity checking */ |
#define | ZSWR4_PARMASK 0x03 /* mask of all parity bits */ |
#define | ZSWR5_DTR 0x80 /* assert (set to -12V) DTR */ |
#define | ZSWR5_TX_5 0x00 /* transmit 5 or fewer bits */ |
#define | ZSWR5_TX_7 0x20 /* transmit 7 bits */ |
#define | ZSWR5_TX_6 0x40 /* transmit 6 bits */ |
#define | ZSWR5_TX_8 0x60 /* transmit 8 bits */ |
#define | ZSWR5_TXSIZE 0x60 /* transmit char size mask */ |
#define | ZSWR5_BREAK 0x10 /* send break (continuous 0s) */ |
#define | ZSWR5_TX_ENABLE 0x08 /* enable transmitter */ |
#define | ZSWR5_CRC16 0x04 /* use CRC16 (off => use SDLC) */ |
#define | ZSWR5_RTS 0x02 /* assert RTS */ |
#define | ZSWR5_TXCRC_ENABLE 0x01 /* enable xmit crc calculation */ |
#define | ZSWR7P_EXTEND_READ 0x40 /* modify read map; make most regs readable */ |
#define | ZSWR7P_TX_FIFO 0x20 /* change level for Tx FIFO empty int */ |
#define | ZSWR7P_DTR_TIME 0x10 /* modifies deact. speed of /DTR//REQ */ |
#define | ZSWR7P_RX_FIFO 0x08 /* Rx FIFO int on 1/2 full? */ |
#define | ZSWR7P_RTS_DEACT 0x04 /* automatically deassert RTS */ |
#define | ZSWR7P_AUTO_EOM_RESET 0x02 /* automatically reset EMO/Tx Underrun */ |
#define | ZSWR7P_AUTO_TX_FLAG 0x01 /* Auto send SDLC flag at transmit start */ |
#define | ZSWR9_HARD_RESET 0xc0 /* force hardware reset */ |
#define | ZSWR9_A_RESET 0x80 /* reset channel A (0) */ |
#define | ZSWR9_B_RESET 0x40 /* reset channel B (1) */ |
#define | ZSWR9_SOFT_INTAC 0x20 /* Not in NMOS version */ |
#define | ZSWR9_STATUS_HIGH 0x10 /* status in high bits of intr vec */ |
#define | ZSWR9_MASTER_IE 0x08 /* master interrupt enable */ |
#define | ZSWR9_DLC 0x04 /* disable lower chain */ |
#define | ZSWR9_NO_VECTOR 0x02 /* no vector */ |
#define | ZSWR9_VECTOR_INCL_STAT 0x01 /* vector includes status */ |
#define | ZSWR10_PRESET_ONES 0x80 /* preset CRC to all 1 (else all 0) */ |
#define | ZSWR10_NRZ 0x00 /* NRZ encoding */ |
#define | ZSWR10_NRZI 0x20 /* NRZI encoding */ |
#define | ZSWR10_FM1 0x40 /* FM1 encoding */ |
#define | ZSWR10_FM0 0x60 /* FM0 encoding */ |
#define | ZSWR10_GA_ON_POLL 0x10 /* go active on poll (loop mode) */ |
#define | ZSWR10_MARK_IDLE 0x08 /* all 1s (vs flag) when idle (SDLC) */ |
#define | ZSWR10_ABORT_ON_UNDERRUN 0x4 /* abort on xmit underrun (SDLC) */ |
#define | ZSWR10_LOOP_MODE 0x02 /* loop mode (SDLC) */ |
#define | ZSWR10_6_BIT_SYNC 0x01 /* 6 bits per sync char (sync modes) */ |
#define | ZSWR11_XTAL 0x80 /* have xtal between RTxC* and SYNC* */ |
#define | ZSWR11_RXCLK_RTXC 0x00 /* recv clock taken from RTxC* pin */ |
#define | ZSWR11_RXCLK_TRXC 0x20 /* recv clock taken from TRxC* pin */ |
#define | ZSWR11_RXCLK_BAUD 0x40 /* recv clock taken from BRG */ |
#define | ZSWR11_RXCLK_DPLL 0x60 /* recv clock taken from DPLL */ |
#define | ZSWR11_TXCLK_RTXC 0x00 /* xmit clock taken from RTxC* pin */ |
#define | ZSWR11_TXCLK_TRXC 0x08 /* xmit clock taken from TRxC* pin */ |
#define | ZSWR11_TXCLK_BAUD 0x10 /* xmit clock taken from BRG */ |
#define | ZSWR11_TXCLK_DPLL 0x18 /* xmit clock taken from DPLL */ |
#define | ZSWR11_TRXC_OUT_ENA 0x04 /* TRxC* pin will be an output */ |
#define | ZSWR11_TRXC_XTAL 0x00 /* TRxC output from xtal oscillator */ |
#define | ZSWR11_TRXC_XMIT 0x01 /* TRxC output from xmit clock */ |
#define | ZSWR11_TRXC_BAUD 0x02 /* TRxC output from BRG */ |
#define | ZSWR11_TRXC_DPLL 0x03 /* TRxC output from DPLL */ |
#define | BPS_TO_TCONST(f, bps) ((((f) + (bps)) / (2 * (bps))) - 2) |
#define | TCONST_TO_BPS(f, tc) ((f) / 2 / ((tc) + 2)) |
#define | ZSWR14_DPLL_NOOP 0x00 /* leave DPLL alone */ |
#define | ZSWR14_DPLL_SEARCH 0x20 /* enter search mode */ |
#define | ZSWR14_DPLL_RESET_CM 0x40 /* reset `clock missing' in RR10 */ |
#define | ZSWR14_DPLL_DISABLE 0x60 /* disable DPLL (continuous search) */ |
#define | ZSWR14_DPLL_SRC_BAUD 0x80 /* set DPLL src = BRG */ |
#define | ZSWR14_DPLL_SRC_RTXC 0xa0 /* set DPLL src = RTxC* or xtal osc */ |
#define | ZSWR14_DPLL_FM 0xc0 /* operate in FM mode */ |
#define | ZSWR14_DPLL_NRZI 0xe0 /* operate in NRZI mode */ |
#define | ZSWR14_LOCAL_LOOPBACK 0x10 /* set local loopback mode */ |
#define | ZSWR14_AUTO_ECHO 0x08 /* set auto echo mode */ |
#define | ZSWR14_DTR_REQ 0x04 /* DTR* / REQ* pin gives REQ* */ |
#define | ZSWR14_BAUD_FROM_PCLK 0x02 /* BRG clock taken from PCLK */ |
#define | ZSWR14_BAUD_ENA 0x01 /* enable BRG countdown */ |
#define | ZSWR15_BREAK_IE 0x80 /* enable break/abort status int */ |
#define | ZSWR15_TXUEOM_IE 0x40 /* enable TX underrun/EOM status int */ |
#define | ZSWR15_CTS_IE 0x20 /* enable CTS* pin status int */ |
#define | ZSWR15_SYNCHUNT_IE 0x10 /* enable SYNC* pin/hunt status int */ |
#define | ZSWR15_DCD_IE 0x08 /* enable DCD* pin status int */ |
#define | ZSWR15_SDLC_FIFO 0x04 /* enable SDLC FIFO enhancements */ |
#define | ZSWR15_ZERO_COUNT_IE 0x02 /* enable BRG-counter = 0 status int */ |
#define | ZSWR15_ENABLE_ENHANCED 0x01 /* enable writing WR7' at reg 7 */ |
#define | ZSRR0_BREAK 0x80 /* break/abort detected */ |
#define | ZSRR0_TXUNDER 0x40 /* transmit underrun/EOM (sync) */ |
#define | ZSRR0_CTS 0x20 /* clear to send */ |
#define | ZSRR0_SYNC_HUNT 0x10 /* sync/hunt (sync mode) */ |
#define | ZSRR0_DCD 0x08 /* data carrier detect */ |
#define | ZSRR0_TX_READY 0x04 /* transmit buffer empty */ |
#define | ZSRR0_ZERO_COUNT 0x02 /* zero count in baud clock */ |
#define | ZSRR0_RX_READY 0x01 /* received character ready */ |
#define | ZSRR1_EOF 0x80 /* end of frame (SDLC mode) */ |
#define | ZSRR1_FE 0x40 /* CRC/framing error */ |
#define | ZSRR1_DO 0x20 /* data (receiver) overrun */ |
#define | ZSRR1_PE 0x10 /* parity error */ |
#define | ZSRR1_RC0 0x08 /* residue code 0 (SDLC mode) */ |
#define | ZSRR1_RC1 0x04 /* residue code 1 (SDLC mode) */ |
#define | ZSRR1_RC2 0x02 /* residue code 2 (SDLC mode) */ |
#define | ZSRR1_ALL_SENT 0x01 /* all chars out of xmitter (async) */ |
#define | ZSRR3_IP_A_RX 0x20 /* channel A recv int pending */ |
#define | ZSRR3_IP_A_TX 0x10 /* channel A xmit int pending */ |
#define | ZSRR3_IP_A_STAT 0x08 /* channel A status int pending */ |
#define | ZSRR3_IP_B_RX 0x04 /* channel B recv int pending */ |
#define | ZSRR3_IP_B_TX 0x02 /* channel B xmit int pending */ |
#define | ZSRR3_IP_B_STAT 0x01 /* channel B status int pending */ |
#define | ZSRR10_1_CLOCK_MISSING 0x80 /* 1 clock edge missing (FM mode) */ |
#define | ZSRR10_2_CLOCKS_MISSING 0x40 /* 2 clock edges missing (FM mode) */ |
#define | ZSRR10_LOOP_SENDING 0x10 /* xmitter controls loop (SDLC loop) */ |
#define | ZSRR10_ON_LOOP 0x02 /* SCC is on loop (SDLC/X.21 modes) */ |
#define | ZSRR15_BREAK_IE 0x80 /* break/abort status int enable */ |
#define | ZSRR15_TXUEOM_IE 0x40 /* TX underrun/EOM status int enable */ |
#define | ZSRR15_CTS_IE 0x20 /* CTS* pin status int enable */ |
#define | ZSRR15_SYNCHUNT_IE 0x10 /* SYNC* pin/hunt status int enable */ |
#define | ZSRR15_DCD_IE 0x08 /* DCD* pin status int enable */ |
#define | ZSRR15_ZERO_COUNT_IE 0x02 /* BRG-counter = 0 status int enable */ |
Definition at line 341 of file z8530reg.h.
Definition at line 344 of file z8530reg.h.
#define ZSM_EI_NEXTRXC 0x20 /* enable int. on next rcvd char */ |
Definition at line 127 of file z8530reg.h.
#define ZSM_NULL 0x00 /* nothing special */ |
Definition at line 131 of file z8530reg.h.
#define ZSM_NULL 0x00 /* nothing special */ |
Definition at line 131 of file z8530reg.h.
#define ZSM_POINTHIGH 0x08 /* `point high' (use r8-r15) */ |
Definition at line 130 of file z8530reg.h.
#define ZSM_RESET_ERR 0x30 /* reset error cond */ |
Definition at line 125 of file z8530reg.h.
#define ZSM_RESET_IUS 0x38 /* reset interrupt under service */ |
Definition at line 124 of file z8530reg.h.
#define ZSM_RESET_RXCRC 0x40 /* reset recv crc checker */ |
Definition at line 121 of file z8530reg.h.
#define ZSM_RESET_STINT 0x10 /* reset external/status interrupt */ |
Definition at line 129 of file z8530reg.h.
#define ZSM_RESET_TXCRC 0x80 /* reset xmit crc generator */ |
Definition at line 120 of file z8530reg.h.
#define ZSM_RESET_TXINT 0x28 /* reset xmit interrupt pending */ |
Definition at line 126 of file z8530reg.h.
#define ZSM_RESET_TXUEOM 0xc0 /* reset xmit underrun / eom latch */ |
Definition at line 119 of file z8530reg.h.
#define ZSM_SEND_ABORT 0x18 /* send abort (SDLC) */ |
Definition at line 128 of file z8530reg.h.
#define ZSRR0_BREAK 0x80 /* break/abort detected */ |
Definition at line 388 of file z8530reg.h.
#define ZSRR0_CTS 0x20 /* clear to send */ |
Definition at line 390 of file z8530reg.h.
Referenced by DEVICE_ACCESS().
#define ZSRR0_DCD 0x08 /* data carrier detect */ |
Definition at line 392 of file z8530reg.h.
Referenced by DEVICE_ACCESS().
#define ZSRR0_RX_READY 0x01 /* received character ready */ |
Definition at line 395 of file z8530reg.h.
Referenced by DEVICE_ACCESS().
#define ZSRR0_SYNC_HUNT 0x10 /* sync/hunt (sync mode) */ |
Definition at line 391 of file z8530reg.h.
#define ZSRR0_TX_READY 0x04 /* transmit buffer empty */ |
Definition at line 393 of file z8530reg.h.
Referenced by DEVICE_ACCESS().
#define ZSRR0_TXUNDER 0x40 /* transmit underrun/EOM (sync) */ |
Definition at line 389 of file z8530reg.h.
#define ZSRR0_ZERO_COUNT 0x02 /* zero count in baud clock */ |
Definition at line 394 of file z8530reg.h.
#define ZSRR10_1_CLOCK_MISSING 0x80 /* 1 clock edge missing (FM mode) */ |
Definition at line 430 of file z8530reg.h.
#define ZSRR10_2_CLOCKS_MISSING 0x40 /* 2 clock edges missing (FM mode) */ |
Definition at line 431 of file z8530reg.h.
#define ZSRR10_LOOP_SENDING 0x10 /* xmitter controls loop (SDLC loop) */ |
Definition at line 433 of file z8530reg.h.
#define ZSRR10_ON_LOOP 0x02 /* SCC is on loop (SDLC/X.21 modes) */ |
Definition at line 436 of file z8530reg.h.
#define ZSRR15_BREAK_IE 0x80 /* break/abort status int enable */ |
Definition at line 442 of file z8530reg.h.
#define ZSRR15_CTS_IE 0x20 /* CTS* pin status int enable */ |
Definition at line 444 of file z8530reg.h.
#define ZSRR15_DCD_IE 0x08 /* DCD* pin status int enable */ |
Definition at line 446 of file z8530reg.h.
#define ZSRR15_SYNCHUNT_IE 0x10 /* SYNC* pin/hunt status int enable */ |
Definition at line 445 of file z8530reg.h.
#define ZSRR15_TXUEOM_IE 0x40 /* TX underrun/EOM status int enable */ |
Definition at line 443 of file z8530reg.h.
#define ZSRR15_ZERO_COUNT_IE 0x02 /* BRG-counter = 0 status int enable */ |
Definition at line 448 of file z8530reg.h.
#define ZSRR1_ALL_SENT 0x01 /* all chars out of xmitter (async) */ |
Definition at line 407 of file z8530reg.h.
#define ZSRR1_DO 0x20 /* data (receiver) overrun */ |
Definition at line 402 of file z8530reg.h.
#define ZSRR1_EOF 0x80 /* end of frame (SDLC mode) */ |
Definition at line 400 of file z8530reg.h.
#define ZSRR1_FE 0x40 /* CRC/framing error */ |
Definition at line 401 of file z8530reg.h.
#define ZSRR1_PE 0x10 /* parity error */ |
Definition at line 403 of file z8530reg.h.
#define ZSRR1_RC0 0x08 /* residue code 0 (SDLC mode) */ |
Definition at line 404 of file z8530reg.h.
#define ZSRR1_RC1 0x04 /* residue code 1 (SDLC mode) */ |
Definition at line 405 of file z8530reg.h.
#define ZSRR1_RC2 0x02 /* residue code 2 (SDLC mode) */ |
Definition at line 406 of file z8530reg.h.
#define ZSRR3_IP_A_RX 0x20 /* channel A recv int pending */ |
Definition at line 420 of file z8530reg.h.
Referenced by DEVICE_TICK().
#define ZSRR3_IP_A_STAT 0x08 /* channel A status int pending */ |
Definition at line 422 of file z8530reg.h.
#define ZSRR3_IP_A_TX 0x10 /* channel A xmit int pending */ |
Definition at line 421 of file z8530reg.h.
Referenced by DEVICE_ACCESS(), and DEVICE_TICK().
#define ZSRR3_IP_B_RX 0x04 /* channel B recv int pending */ |
Definition at line 423 of file z8530reg.h.
Referenced by DEVICE_TICK().
#define ZSRR3_IP_B_STAT 0x01 /* channel B status int pending */ |
Definition at line 425 of file z8530reg.h.
#define ZSRR3_IP_B_TX 0x02 /* channel B xmit int pending */ |
Definition at line 424 of file z8530reg.h.
Referenced by DEVICE_ACCESS(), and DEVICE_TICK().
#define ZSRR_BAUDHI 13 /* baud rate generator (high half) */ |
Definition at line 97 of file z8530reg.h.
#define ZSRR_BAUDLO 12 /* baud rate generator (low half) */ |
Definition at line 96 of file z8530reg.h.
#define ZSRR_ENHANCED 14 /* read address of WR7' - yes, it's not 7!*/ |
Definition at line 98 of file z8530reg.h.
#define ZSRR_IPEND 3 /* interrupt pending (ch. 0 only) */ |
Definition at line 89 of file z8530reg.h.
#define ZSRR_IVEC 2 /* interrupt vector (channel 0) */ |
Definition at line 88 of file z8530reg.h.
#define ZSRR_RXSYNC 7 /* sync receive char (monosync mode) */ |
Definition at line 91 of file z8530reg.h.
#define ZSRR_SDLC_ADDR 6 /* SDLC address (SDLC mode) */ |
Definition at line 94 of file z8530reg.h.
#define ZSRR_SDLC_FLAG 7 /* SDLC flag 0x7E (SDLC mode) */ |
Definition at line 95 of file z8530reg.h.
#define ZSRR_SYNCHI 7 /* sync high byte (bisync mode) */ |
Definition at line 93 of file z8530reg.h.
#define ZSRR_SYNCLO 6 /* sync low byte (bisync mode) */ |
Definition at line 92 of file z8530reg.h.
#define ZSRR_TXSYNC 6 /* sync transmit char (monosync mode) */ |
Definition at line 90 of file z8530reg.h.
#define ZSWR0_CLR_INTR ZSM_RESET_IUS |
Definition at line 141 of file z8530reg.h.
Referenced by DEVICE_ACCESS().
#define ZSWR0_EI_NEXTRXC ZSM_EI_NEXTRXC |
Definition at line 143 of file z8530reg.h.
#define ZSWR0_RESET_EOM ZSM_RESET_TXUEOM |
Definition at line 138 of file z8530reg.h.
#define ZSWR0_RESET_ERRORS ZSM_RESET_ERR |
Definition at line 142 of file z8530reg.h.
#define ZSWR0_RESET_RXCRC ZSM_RESET_RXCRC |
Definition at line 140 of file z8530reg.h.
#define ZSWR0_RESET_STATUS ZSM_RESET_STINT |
Definition at line 145 of file z8530reg.h.
#define ZSWR0_RESET_TXCRC ZSM_RESET_TXCRC |
Definition at line 139 of file z8530reg.h.
#define ZSWR0_RESET_TXINT ZSM_RESET_TXINT |
Definition at line 146 of file z8530reg.h.
#define ZSWR0_SEND_ABORT ZSM_SEND_ABORT |
Definition at line 144 of file z8530reg.h.
#define ZSWR10_6_BIT_SYNC 0x01 /* 6 bits per sync char (sync modes) */ |
Definition at line 294 of file z8530reg.h.
#define ZSWR10_ABORT_ON_UNDERRUN 0x4 /* abort on xmit underrun (SDLC) */ |
Definition at line 292 of file z8530reg.h.
#define ZSWR10_FM0 0x60 /* FM0 encoding */ |
Definition at line 288 of file z8530reg.h.
#define ZSWR10_FM1 0x40 /* FM1 encoding */ |
Definition at line 287 of file z8530reg.h.
#define ZSWR10_GA_ON_POLL 0x10 /* go active on poll (loop mode) */ |
Definition at line 290 of file z8530reg.h.
#define ZSWR10_LOOP_MODE 0x02 /* loop mode (SDLC) */ |
Definition at line 293 of file z8530reg.h.
#define ZSWR10_MARK_IDLE 0x08 /* all 1s (vs flag) when idle (SDLC) */ |
Definition at line 291 of file z8530reg.h.
#define ZSWR10_NRZ 0x00 /* NRZ encoding */ |
Definition at line 285 of file z8530reg.h.
#define ZSWR10_NRZI 0x20 /* NRZI encoding */ |
Definition at line 286 of file z8530reg.h.
#define ZSWR10_PRESET_ONES 0x80 /* preset CRC to all 1 (else all 0) */ |
Definition at line 283 of file z8530reg.h.
#define ZSWR11_RXCLK_BAUD 0x40 /* recv clock taken from BRG */ |
Definition at line 305 of file z8530reg.h.
#define ZSWR11_RXCLK_DPLL 0x60 /* recv clock taken from DPLL */ |
Definition at line 306 of file z8530reg.h.
#define ZSWR11_RXCLK_RTXC 0x00 /* recv clock taken from RTxC* pin */ |
Definition at line 303 of file z8530reg.h.
#define ZSWR11_RXCLK_TRXC 0x20 /* recv clock taken from TRxC* pin */ |
Definition at line 304 of file z8530reg.h.
#define ZSWR11_TRXC_BAUD 0x02 /* TRxC output from BRG */ |
Definition at line 317 of file z8530reg.h.
#define ZSWR11_TRXC_DPLL 0x03 /* TRxC output from DPLL */ |
Definition at line 318 of file z8530reg.h.
#define ZSWR11_TRXC_OUT_ENA 0x04 /* TRxC* pin will be an output */ |
Definition at line 313 of file z8530reg.h.
#define ZSWR11_TRXC_XMIT 0x01 /* TRxC output from xmit clock */ |
Definition at line 316 of file z8530reg.h.
#define ZSWR11_TRXC_XTAL 0x00 /* TRxC output from xtal oscillator */ |
Definition at line 315 of file z8530reg.h.
#define ZSWR11_TXCLK_BAUD 0x10 /* xmit clock taken from BRG */ |
Definition at line 310 of file z8530reg.h.
#define ZSWR11_TXCLK_DPLL 0x18 /* xmit clock taken from DPLL */ |
Definition at line 311 of file z8530reg.h.
#define ZSWR11_TXCLK_RTXC 0x00 /* xmit clock taken from RTxC* pin */ |
Definition at line 308 of file z8530reg.h.
#define ZSWR11_TXCLK_TRXC 0x08 /* xmit clock taken from TRxC* pin */ |
Definition at line 309 of file z8530reg.h.
#define ZSWR11_XTAL 0x80 /* have xtal between RTxC* and SYNC* */ |
Definition at line 301 of file z8530reg.h.
#define ZSWR14_AUTO_ECHO 0x08 /* set auto echo mode */ |
Definition at line 360 of file z8530reg.h.
#define ZSWR14_BAUD_ENA 0x01 /* enable BRG countdown */ |
Definition at line 364 of file z8530reg.h.
#define ZSWR14_BAUD_FROM_PCLK 0x02 /* BRG clock taken from PCLK */ |
Definition at line 362 of file z8530reg.h.
#define ZSWR14_DPLL_DISABLE 0x60 /* disable DPLL (continuous search) */ |
Definition at line 353 of file z8530reg.h.
#define ZSWR14_DPLL_FM 0xc0 /* operate in FM mode */ |
Definition at line 356 of file z8530reg.h.
#define ZSWR14_DPLL_NOOP 0x00 /* leave DPLL alone */ |
Definition at line 350 of file z8530reg.h.
#define ZSWR14_DPLL_NRZI 0xe0 /* operate in NRZI mode */ |
Definition at line 357 of file z8530reg.h.
#define ZSWR14_DPLL_RESET_CM 0x40 /* reset `clock missing' in RR10 */ |
Definition at line 352 of file z8530reg.h.
#define ZSWR14_DPLL_SEARCH 0x20 /* enter search mode */ |
Definition at line 351 of file z8530reg.h.
#define ZSWR14_DPLL_SRC_BAUD 0x80 /* set DPLL src = BRG */ |
Definition at line 354 of file z8530reg.h.
#define ZSWR14_DPLL_SRC_RTXC 0xa0 /* set DPLL src = RTxC* or xtal osc */ |
Definition at line 355 of file z8530reg.h.
#define ZSWR14_DTR_REQ 0x04 /* DTR* / REQ* pin gives REQ* */ |
Definition at line 361 of file z8530reg.h.
#define ZSWR14_LOCAL_LOOPBACK 0x10 /* set local loopback mode */ |
Definition at line 359 of file z8530reg.h.
#define ZSWR15_BREAK_IE 0x80 /* enable break/abort status int */ |
Definition at line 375 of file z8530reg.h.
#define ZSWR15_CTS_IE 0x20 /* enable CTS* pin status int */ |
Definition at line 377 of file z8530reg.h.
#define ZSWR15_DCD_IE 0x08 /* enable DCD* pin status int */ |
Definition at line 379 of file z8530reg.h.
#define ZSWR15_ENABLE_ENHANCED 0x01 /* enable writing WR7' at reg 7 */ |
Definition at line 382 of file z8530reg.h.
#define ZSWR15_SDLC_FIFO 0x04 /* enable SDLC FIFO enhancements */ |
Definition at line 380 of file z8530reg.h.
#define ZSWR15_SYNCHUNT_IE 0x10 /* enable SYNC* pin/hunt status int */ |
Definition at line 378 of file z8530reg.h.
#define ZSWR15_TXUEOM_IE 0x40 /* enable TX underrun/EOM status int */ |
Definition at line 376 of file z8530reg.h.
#define ZSWR15_ZERO_COUNT_IE 0x02 /* enable BRG-counter = 0 status int */ |
Definition at line 381 of file z8530reg.h.
#define ZSWR1_IMASK 0x1F /* mask of all itr. enable bits. */ |
Definition at line 167 of file z8530reg.h.
#define ZSWR1_PE_SC 0x04 /* parity error is special condition */ |
Definition at line 163 of file z8530reg.h.
#define ZSWR1_REQ_ENABLE (ZSWR1_REQ_WAIT | ZSWR1_REQ_TX) |
Definition at line 170 of file z8530reg.h.
#define ZSWR1_REQ_REQ 0xc0 /* WAIT*-REQ* pin gives REQ* */ |
Definition at line 154 of file z8530reg.h.
#define ZSWR1_REQ_RX 0x20 /* WAIT*-REQ* pin follows recv buf */ |
Definition at line 156 of file z8530reg.h.
#define ZSWR1_REQ_TX 0x00 /* WAIT*-REQ* pin follows xmit buf */ |
Definition at line 155 of file z8530reg.h.
#define ZSWR1_REQ_WAIT 0x80 /* WAIT*-REQ* pin gives WAIT* */ |
Definition at line 153 of file z8530reg.h.
#define ZSWR1_RIE 0x10 /* rxint per char & on S.C. */ |
Definition at line 160 of file z8530reg.h.
#define ZSWR1_RIE_FIRST 0x08 /* rxint on first char & on S.C. */ |
Definition at line 159 of file z8530reg.h.
#define ZSWR1_RIE_NONE 0x00 /* disable rxint entirely */ |
Definition at line 158 of file z8530reg.h.
#define ZSWR1_RIE_SPECIAL_ONLY 0x18 /* rxint on S.C. only */ |
Definition at line 161 of file z8530reg.h.
#define ZSWR1_SIE 0x01 /* external/status interrupt enable */ |
Definition at line 165 of file z8530reg.h.
#define ZSWR1_TIE 0x02 /* transmit interrupt enable */ |
Definition at line 164 of file z8530reg.h.
Referenced by DEVICE_TICK().
#define ZSWR3_ADDR_SEARCH_MODE 0x04 /* address search mode (SDLC only) */ |
Definition at line 190 of file z8530reg.h.
#define ZSWR3_HFC 0x20 /* hardware flow control */ |
Definition at line 187 of file z8530reg.h.
#define ZSWR3_HUNT 0x10 /* enter hunt mode */ |
Definition at line 188 of file z8530reg.h.
#define ZSWR3_RX_5 0x00 /* receive 5 bits per char */ |
Definition at line 181 of file z8530reg.h.
#define ZSWR3_RX_6 0x80 /* receive 6 bits per char */ |
Definition at line 183 of file z8530reg.h.
#define ZSWR3_RX_7 0x40 /* receive 7 bits per char */ |
Definition at line 182 of file z8530reg.h.
#define ZSWR3_RX_8 0xc0 /* receive 8 bits per char */ |
Definition at line 184 of file z8530reg.h.
#define ZSWR3_RX_ENABLE 0x01 /* receiver enable */ |
Definition at line 193 of file z8530reg.h.
#define ZSWR3_RXCRC_ENABLE 0x08 /* enable recv crc calculation */ |
Definition at line 189 of file z8530reg.h.
#define ZSWR3_RXSIZE 0xc0 /* receive char size mask */ |
Definition at line 185 of file z8530reg.h.
#define ZSWR3_SDLC_SHORT_ADDR 0x02 /* short address mode (SDLC only) */ |
Definition at line 191 of file z8530reg.h.
#define ZSWR3_SYNC_LOAD_INH 0x02 /* sync character load inhibit */ |
Definition at line 192 of file z8530reg.h.
#define ZSWR4_1P5SB 0x08 /* 1.5 stop bits (clk cannot be 1x) */ |
Definition at line 213 of file z8530reg.h.
#define ZSWR4_BISYNC 0x10 /* 16 bit sync char (sync only) */ |
Definition at line 206 of file z8530reg.h.
#define ZSWR4_CLK_MASK 0xc0 /* clock divisor mask */ |
Definition at line 203 of file z8530reg.h.
#define ZSWR4_CLK_X1 0x00 /* clock divisor = 1 */ |
Definition at line 199 of file z8530reg.h.
#define ZSWR4_CLK_X16 0x40 /* clock divisor = 16 */ |
Definition at line 200 of file z8530reg.h.
#define ZSWR4_CLK_X32 0x80 /* clock divisor = 32 */ |
Definition at line 201 of file z8530reg.h.
#define ZSWR4_CLK_X64 0xc0 /* clock divisor = 64 */ |
Definition at line 202 of file z8530reg.h.
#define ZSWR4_EVENP 0x02 /* check for even parity */ |
Definition at line 217 of file z8530reg.h.
#define ZSWR4_EXTSYNC 0x30 /* external sync mode */ |
Definition at line 208 of file z8530reg.h.
#define ZSWR4_MONOSYNC 0x00 /* 8 bit sync char (sync only) */ |
Definition at line 205 of file z8530reg.h.
#define ZSWR4_ONESB 0x04 /* 1 stop bit */ |
Definition at line 212 of file z8530reg.h.
#define ZSWR4_PARENB 0x01 /* enable parity checking */ |
Definition at line 218 of file z8530reg.h.
#define ZSWR4_PARMASK 0x03 /* mask of all parity bits */ |
Definition at line 219 of file z8530reg.h.
#define ZSWR4_SBMASK 0x0c /* mask of all stop bits */ |
Definition at line 215 of file z8530reg.h.
#define ZSWR4_SDLC 0x20 /* SDLC mode */ |
Definition at line 207 of file z8530reg.h.
#define ZSWR4_SYNC_MASK 0x30 /* sync mode bit mask */ |
Definition at line 209 of file z8530reg.h.
#define ZSWR4_SYNCMODE 0x00 /* no stop bit (sync mode only) */ |
Definition at line 211 of file z8530reg.h.
#define ZSWR4_TWOSB 0x0c /* 2 stop bits */ |
Definition at line 214 of file z8530reg.h.
#define ZSWR5_BREAK 0x10 /* send break (continuous 0s) */ |
Definition at line 234 of file z8530reg.h.
#define ZSWR5_CRC16 0x04 /* use CRC16 (off => use SDLC) */ |
Definition at line 236 of file z8530reg.h.
#define ZSWR5_DTR 0x80 /* assert (set to -12V) DTR */ |
Definition at line 226 of file z8530reg.h.
#define ZSWR5_RTS 0x02 /* assert RTS */ |
Definition at line 237 of file z8530reg.h.
#define ZSWR5_TX_5 0x00 /* transmit 5 or fewer bits */ |
Definition at line 228 of file z8530reg.h.
#define ZSWR5_TX_6 0x40 /* transmit 6 bits */ |
Definition at line 230 of file z8530reg.h.
#define ZSWR5_TX_7 0x20 /* transmit 7 bits */ |
Definition at line 229 of file z8530reg.h.
#define ZSWR5_TX_8 0x60 /* transmit 8 bits */ |
Definition at line 231 of file z8530reg.h.
#define ZSWR5_TX_ENABLE 0x08 /* enable transmitter */ |
Definition at line 235 of file z8530reg.h.
#define ZSWR5_TXCRC_ENABLE 0x01 /* enable xmit crc calculation */ |
Definition at line 238 of file z8530reg.h.
#define ZSWR5_TXSIZE 0x60 /* transmit char size mask */ |
Definition at line 232 of file z8530reg.h.
#define ZSWR7P_AUTO_EOM_RESET 0x02 /* automatically reset EMO/Tx Underrun */ |
Definition at line 259 of file z8530reg.h.
#define ZSWR7P_AUTO_TX_FLAG 0x01 /* Auto send SDLC flag at transmit start */ |
Definition at line 260 of file z8530reg.h.
#define ZSWR7P_DTR_TIME 0x10 /* modifies deact. speed of /DTR//REQ */ |
Definition at line 256 of file z8530reg.h.
#define ZSWR7P_EXTEND_READ 0x40 /* modify read map; make most regs readable */ |
Definition at line 254 of file z8530reg.h.
#define ZSWR7P_RTS_DEACT 0x04 /* automatically deassert RTS */ |
Definition at line 258 of file z8530reg.h.
#define ZSWR7P_RX_FIFO 0x08 /* Rx FIFO int on 1/2 full? */ |
Definition at line 257 of file z8530reg.h.
#define ZSWR7P_TX_FIFO 0x20 /* change level for Tx FIFO empty int */ |
Definition at line 255 of file z8530reg.h.
#define ZSWR9_A_RESET 0x80 /* reset channel A (0) */ |
Definition at line 268 of file z8530reg.h.
#define ZSWR9_B_RESET 0x40 /* reset channel B (1) */ |
Definition at line 269 of file z8530reg.h.
#define ZSWR9_DLC 0x04 /* disable lower chain */ |
Definition at line 274 of file z8530reg.h.
#define ZSWR9_HARD_RESET 0xc0 /* force hardware reset */ |
Definition at line 267 of file z8530reg.h.
#define ZSWR9_MASTER_IE 0x08 /* master interrupt enable */ |
Definition at line 273 of file z8530reg.h.
#define ZSWR9_NO_VECTOR 0x02 /* no vector */ |
Definition at line 275 of file z8530reg.h.
#define ZSWR9_SOFT_INTAC 0x20 /* Not in NMOS version */ |
Definition at line 270 of file z8530reg.h.
#define ZSWR9_STATUS_HIGH 0x10 /* status in high bits of intr vec */ |
Definition at line 272 of file z8530reg.h.
#define ZSWR9_VECTOR_INCL_STAT 0x01 /* vector includes status */ |
Definition at line 276 of file z8530reg.h.
#define ZSWR_BAUDHI 13 /* baud rate generator (high half) */ |
Definition at line 108 of file z8530reg.h.
#define ZSWR_BAUDLO 12 /* baud rate generator (low half) */ |
Definition at line 107 of file z8530reg.h.
#define ZSWR_ENHANCED 7 /* write address of WR7' */ |
Definition at line 109 of file z8530reg.h.
#define ZSWR_IVEC 2 /* interrupt vector (shared) */ |
Definition at line 100 of file z8530reg.h.
#define ZSWR_RXSYNC 7 /* sync receive char (monosync mode) */ |
Definition at line 102 of file z8530reg.h.
#define ZSWR_SDLC_ADDR 6 /* SDLC address (SDLC mode) */ |
Definition at line 105 of file z8530reg.h.
#define ZSWR_SDLC_FLAG 7 /* SDLC flag 0x7E (SDLC mode) */ |
Definition at line 106 of file z8530reg.h.
#define ZSWR_SYNCHI 7 /* sync high byte (bisync mode) */ |
Definition at line 104 of file z8530reg.h.
#define ZSWR_SYNCLO 6 /* sync low byte (bisync mode) */ |
Definition at line 103 of file z8530reg.h.
#define ZSWR_TXSYNC 6 /* sync transmit char (monosync mode) */ |
Definition at line 101 of file z8530reg.h.