sccreg.h File Reference

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sccreg.h File Reference

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Classes

struct  scc_regmap
 

Macros

#define SCC_CHANNEL_A   1
 
#define SCC_CHANNEL_B   0
 
#define SCC_INIT_REG(scc, chan)
 
#define SCC_READ_REG(scc, chan, reg, val)
 
#define SCC_READ_REG_ZERO(scc, chan, val)
 
#define SCC_WRITE_REG(scc, chan, reg, val)
 
#define SCC_WRITE_REG_ZERO(scc, chan, val)
 
#define SCC_READ_DATA(scc, chan, val)
 
#define SCC_WRITE_DATA(scc, chan, val)
 
#define SCC_RR0   0 /* status register */
 
#define SCC_RR1   1 /* special receive conditions */
 
#define SCC_RR2   2 /* (modified) interrupt vector */
 
#define SCC_RR3   3 /* interrupts pending (cha A only) */
 
#define SCC_RR8   8 /* recv buffer (alias for data) */
 
#define SCC_RR10   10 /* sdlc status */
 
#define SCC_RR12   12 /* BRG constant, low part */
 
#define SCC_RR13   13 /* BRG constant, high part */
 
#define SCC_RR15   15 /* interrupts currently enabled */
 
#define SCC_WR0   0 /* reg select, and commands */
 
#define SCC_WR1   1 /* interrupt and DMA enables */
 
#define SCC_WR2   2 /* interrupt vector */
 
#define SCC_WR3   3 /* receiver params and enables */
 
#define SCC_WR4   4 /* clock/char/parity params */
 
#define SCC_WR5   5 /* xmit params and enables */
 
#define SCC_WR6   6 /* synchr SYNCH/address */
 
#define SCC_WR7   7 /* synchr SYNCH/flag */
 
#define SCC_WR8   8 /* xmit buffer (alias for data) */
 
#define SCC_WR9   9 /* vectoring and resets */
 
#define SCC_WR10   10 /* synchr params */
 
#define SCC_WR11   11 /* clocking definitions */
 
#define SCC_WR12   12 /* BRG constant, low part */
 
#define SCC_WR13   13 /* BRG constant, high part */
 
#define SCC_WR14   14 /* BRG enables and commands */
 
#define SCC_WR15   15 /* interrupt enables */
 
#define SCC_RR0_BREAK   0x80 /* break detected (rings twice), or */
 
#define SCC_RR0_ABORT   0x80 /* abort (synchr) */
 
#define SCC_RR0_TX_UNDERRUN   0x40 /* xmit buffer empty/end of message */
 
#define SCC_RR0_CTS
 
#define SCC_RR0_SYNCH   0x10 /* SYNCH found/still hunting */
 
#define SCC_RR0_DCD   0x08 /* carrier-detect (same as CTS) */
 
#define SCC_RR0_TX_EMPTY   0x04 /* xmit buffer empty */
 
#define SCC_RR0_ZERO_COUNT   0x02 /* ? */
 
#define SCC_RR0_RX_AVAIL   0x01 /* recv fifo not empty */
 
#define SCC_RR1_EOF   0x80 /* end-of-frame, SDLC mode */
 
#define SCC_RR1_CRC_ERR   0x40 /* incorrect CRC or.. */
 
#define SCC_RR1_FRAME_ERR   0x40 /* ..bad frame */
 
#define SCC_RR1_RX_OVERRUN   0x20 /* rcv fifo overflow */
 
#define SCC_RR1_PARITY_ERR   0x10 /* incorrect parity in data */
 
#define SCC_RR1_RESIDUE0   0x08
 
#define SCC_RR1_RESIDUE1   0x04
 
#define SCC_RR1_RESIDUE2   0x02
 
#define SCC_RR1_ALL_SENT   0x01
 
#define SCC_RR2_STATUS(val)   ((val)&0xf)
 
#define SCC_RR2_B_XMIT_DONE   0x0
 
#define SCC_RR2_B_EXT_STATUS   0x2
 
#define SCC_RR2_B_RECV_DONE   0x4
 
#define SCC_RR2_B_RECV_SPECIAL   0x6
 
#define SCC_RR2_A_XMIT_DONE   0x8
 
#define SCC_RR2_A_EXT_STATUS   0xa
 
#define SCC_RR2_A_RECV_DONE   0xc
 
#define SCC_RR2_A_RECV_SPECIAL   0xe
 
#define SCC_RR3_zero   0xc0
 
#define SCC_RR3_RX_IP_A   0x20
 
#define SCC_RR3_TX_IP_A   0x10
 
#define SCC_RR3_EXT_IP_A   0x08
 
#define SCC_RR3_RX_IP_B   0x04
 
#define SCC_RR3_TX_IP_B   0x02
 
#define SCC_RR3_EXT_IP_B   0x01
 
#define SCC_RECV_BUFFER   SCC_RR8
 
#define SCC_RECV_FIFO_DEEP   3
 
#define SCC_RR10_1CLKS   0x80
 
#define SCC_RR10_2CLKS   0x40
 
#define SCC_RR10_zero   0x2d
 
#define SCC_RR10_LOOP_SND   0x10
 
#define SCC_RR10_ON_LOOP   0x02
 
#define SCC_GET_TIMING_BASE(scc, chan, val)
 
#define SCC_RR15_BREAK_IE   0x80
 
#define SCC_RR15_TX_UNDERRUN_IE   0x40
 
#define SCC_RR15_CTS_IE   0x20
 
#define SCC_RR15_SYNCH_IE   0x10
 
#define SCC_RR15_DCD_IE   0x08
 
#define SCC_RR15_zero   0x05
 
#define SCC_RR15_ZERO_COUNT_IE   0x02
 
#define SCC_RESET_TXURUN_LATCH   0xc0
 
#define SCC_RESET_TX_CRC   0x80
 
#define SCC_RESET_RX_CRC   0x40
 
#define SCC_RESET_HIGHEST_IUS   0x38 /* channel A only */
 
#define SCC_RESET_ERROR   0x30
 
#define SCC_RESET_TX_IP   0x28
 
#define SCC_IE_NEXT_CHAR   0x20
 
#define SCC_SEND_SDLC_ABORT   0x18
 
#define SCC_RESET_EXT_IP   0x10
 
#define SCC_WR1_DMA_ENABLE   0x80 /* dma control */
 
#define SCC_WR1_DMA_MODE   0x40 /* drive ~req for DMA controller */
 
#define SCC_WR1_DMA_RECV_DATA   0x20 /* from wire to host memory */
 
#define SCC_WR1_RXI_SPECIAL_O   0x18 /* on special only */
 
#define SCC_WR1_RXI_ALL_CHAR   0x10 /* on each char, or special */
 
#define SCC_WR1_RXI_FIRST_CHAR   0x08 /* on first char, or special */
 
#define SCC_WR1_RXI_DISABLE   0x00 /* never on recv */
 
#define SCC_WR1_PARITY_IE   0x04 /* on parity errors */
 
#define SCC_WR1_TX_IE   0x02
 
#define SCC_WR1_EXT_IE   0x01
 
#define SCC_WR3_RX_8_BITS   0xc0
 
#define SCC_WR3_RX_6_BITS   0x80
 
#define SCC_WR3_RX_7_BITS   0x40
 
#define SCC_WR3_RX_5_BITS   0x00
 
#define SCC_WR3_AUTO_ENABLE   0x20
 
#define SCC_WR3_HUNT_MODE   0x10
 
#define SCC_WR3_RX_CRC_ENABLE   0x08
 
#define SCC_WR3_SDLC_SRCH   0x04
 
#define SCC_WR3_INHIBIT_SYNCH   0x02
 
#define SCC_WR3_RX_ENABLE   0x01
 
#define SCC_WR4_CLK_x64   0xc0 /* clock divide factor */
 
#define SCC_WR4_CLK_x32   0x80
 
#define SCC_WR4_CLK_x16   0x40
 
#define SCC_WR4_CLK_x1   0x00
 
#define SCC_WR4_EXT_SYNCH_MODE   0x30 /* synch modes */
 
#define SCC_WR4_SDLC_MODE   0x20
 
#define SCC_WR4_16BIT_SYNCH   0x10
 
#define SCC_WR4_8BIT_SYNCH   0x00
 
#define SCC_WR4_2_STOP   0x0c /* asynch modes */
 
#define SCC_WR4_1_5_STOP   0x08
 
#define SCC_WR4_1_STOP   0x04
 
#define SCC_WR4_SYNCH_MODE   0x00
 
#define SCC_WR4_EVEN_PARITY   0x02
 
#define SCC_WR4_PARITY_ENABLE   0x01
 
#define SCC_WR5_DTR   0x80 /* drive DTR pin */
 
#define SCC_WR5_TX_8_BITS   0x60
 
#define SCC_WR5_TX_6_BITS   0x40
 
#define SCC_WR5_TX_7_BITS   0x20
 
#define SCC_WR5_TX_5_BITS   0x00
 
#define SCC_WR5_SEND_BREAK   0x10
 
#define SCC_WR5_TX_ENABLE   0x08
 
#define SCC_WR5_CRC_16   0x04 /* CRC if non zero, .. */
 
#define SCC_WR5_SDLC   0x00 /* ..SDLC otherwise */
 
#define SCC_WR5_RTS   0x02 /* drive RTS pin */
 
#define SCC_WR5_TX_CRC_ENABLE   0x01
 
#define SCC_WR6_BISYNCH_12   0x0f
 
#define SCC_WR6_SDLC_RANGE_MASK   0x0f
 
#define SCC_WR7_SDLC_FLAG   0x7e
 
#define SCC_XMT_BUFFER   SCC_WR8
 
#define SCC_WR9_HW_RESET   0xc0 /* force hardware reset */
 
#define SCC_WR9_RESET_CHA_A   0x80
 
#define SCC_WR9_RESET_CHA_B   0x40
 
#define SCC_WR9_NON_VECTORED   0x20 /* mbz for Zilog chip */
 
#define SCC_WR9_STATUS_HIGH   0x10
 
#define SCC_WR9_MASTER_IE   0x08
 
#define SCC_WR9_DLC   0x04 /* disable-lower-chain */
 
#define SCC_WR9_NV   0x02 /* no vector */
 
#define SCC_WR9_VIS   0x01 /* vector-includes-status */
 
#define SCC_WR10_CRC_PRESET   0x80
 
#define SCC_WR10_FM0   0x60
 
#define SCC_WR10_FM1   0x40
 
#define SCC_WR10_NRZI   0x20
 
#define SCC_WR10_NRZ   0x00
 
#define SCC_WR10_ACTIVE_ON_POLL   0x10
 
#define SCC_WR10_MARK_IDLE   0x08 /* flag if zero */
 
#define SCC_WR10_ABORT_ON_URUN   0x04 /* flag if zero */
 
#define SCC_WR10_LOOP_MODE   0x02
 
#define SCC_WR10_6BIT_SYNCH   0x01
 
#define SCC_WR10_8BIT_SYNCH   0x00
 
#define SCC_WR11_RTxC_XTAL   0x80 /* RTxC pin is input (ext oscill) */
 
#define SCC_WR11_RCLK_DPLL   0x60 /* clock received data on dpll */
 
#define SCC_WR11_RCLK_BAUDR   0x40 /* .. on BRG */
 
#define SCC_WR11_RCLK_TRc_PIN   0x20 /* .. on TRxC pin */
 
#define SCC_WR11_RCLK_RTc_PIN   0x00 /* .. on RTxC pin */
 
#define SCC_WR11_XTLK_DPLL   0x18
 
#define SCC_WR11_XTLK_BAUDR   0x10
 
#define SCC_WR11_XTLK_TRc_PIN   0x08
 
#define SCC_WR11_XTLK_RTc_PIN   0x00
 
#define SCC_WR11_TRc_OUT   0x04 /* drive TRxC pin as output from..*/
 
#define SCC_WR11_TRcOUT_DPLL   0x03 /* .. the dpll */
 
#define SCC_WR11_TRcOUT_BAUDR   0x02 /* .. the BRG */
 
#define SCC_WR11_TRcOUT_XMTCLK   0x01 /* .. the xmit clock */
 
#define SCC_WR11_TRcOUT_XTAL   0x00 /* .. the external oscillator */
 
#define SCC_SET_TIMING_BASE(scc, chan, val)
 
#define SCC_WR14_NRZI_MODE   0xe0 /* synch modulations */
 
#define SCC_WR14_FM_MODE   0xc0
 
#define SCC_WR14_RTc_SOURCE   0xa0 /* clock is from pin .. */
 
#define SCC_WR14_BAUDR_SOURCE   0x80 /* .. or internal BRG */
 
#define SCC_WR14_DISABLE_DPLL   0x60
 
#define SCC_WR14_RESET_CLKMISS   0x40
 
#define SCC_WR14_SEARCH_MODE   0x20
 
#define SCC_WR14_LOCAL_LOOPB   0x10
 
#define SCC_WR14_AUTO_ECHO   0x08
 
#define SCC_WR14_DTR_REQUEST   0x04
 
#define SCC_WR14_BAUDR_SRC   0x02
 
#define SCC_WR14_BAUDR_ENABLE   0x01
 
#define SCC_WR15_BREAK_IE   0x80
 
#define SCC_WR15_TX_UNDERRUN_IE   0x40
 
#define SCC_WR15_CTS_IE   0x20
 
#define SCC_WR15_SYNCHUNT_IE   0x10
 
#define SCC_WR15_DCD_IE   0x08
 
#define SCC_WR15_zero   0x05
 
#define SCC_WR15_ZERO_COUNT_IE   0x02
 
#define DML_DSR   0000400 /* data set ready, not a real DM bit */
 
#define DML_RNG   0000200 /* ring */
 
#define DML_CAR   0000100 /* carrier detect */
 
#define DML_CTS   0000040 /* clear to send */
 
#define DML_SR   0000020 /* secondary receive */
 
#define DML_ST   0000010 /* secondary transmit */
 
#define DML_RTS   0000004 /* request to send */
 
#define DML_DTR   0000002 /* data terminal ready */
 
#define DML_LE   0000001 /* line enable */
 
#define SCCCOMM2_PORT   0x0
 
#define SCCMOUSE_PORT   0x1
 
#define SCCCOMM3_PORT   0x2
 
#define SCCKBD_PORT   0x3
 

Typedefs

typedef struct scc_regmap scc_regmap_t
 

Macro Definition Documentation

◆ DML_CAR

#define DML_CAR   0000100 /* carrier detect */

Definition at line 368 of file sccreg.h.

◆ DML_CTS

#define DML_CTS   0000040 /* clear to send */

Definition at line 369 of file sccreg.h.

◆ DML_DSR

#define DML_DSR   0000400 /* data set ready, not a real DM bit */

Definition at line 366 of file sccreg.h.

◆ DML_DTR

#define DML_DTR   0000002 /* data terminal ready */

Definition at line 373 of file sccreg.h.

◆ DML_LE

#define DML_LE   0000001 /* line enable */

Definition at line 374 of file sccreg.h.

◆ DML_RNG

#define DML_RNG   0000200 /* ring */

Definition at line 367 of file sccreg.h.

◆ DML_RTS

#define DML_RTS   0000004 /* request to send */

Definition at line 372 of file sccreg.h.

◆ DML_SR

#define DML_SR   0000020 /* secondary receive */

Definition at line 370 of file sccreg.h.

◆ DML_ST

#define DML_ST   0000010 /* secondary transmit */

Definition at line 371 of file sccreg.h.

◆ SCC_CHANNEL_A

#define SCC_CHANNEL_A   1

Definition at line 87 of file sccreg.h.

Referenced by dev_scc_dma_func().

◆ SCC_CHANNEL_B

#define SCC_CHANNEL_B   0

Definition at line 88 of file sccreg.h.

Referenced by DEVICE_ACCESS().

◆ SCC_GET_TIMING_BASE

#define SCC_GET_TIMING_BASE (   scc,
  chan,
  val 
)
Value:
{ \
char tmp; \
SCC_READ_REG(scc,chan,SCC_RR12,val);\
SCC_READ_REG(scc,chan,SCC_RR13,tmp);\
(val) = ((val)<<8)|(tmp&0xff);\
}
#define SCC_RR13
Definition: sccreg.h:129
#define SCC_RR12
Definition: sccreg.h:128

Definition at line 208 of file sccreg.h.

◆ SCC_IE_NEXT_CHAR

#define SCC_IE_NEXT_CHAR   0x20

Definition at line 233 of file sccreg.h.

◆ SCC_INIT_REG

#define SCC_INIT_REG (   scc,
  chan 
)
Value:
{ \
char tmp; \
tmp = (scc)->scc_channel[(chan)].scc_command; \
tmp = (scc)->scc_channel[(chan)].scc_command; \
}

Definition at line 90 of file sccreg.h.

◆ SCC_READ_DATA

#define SCC_READ_DATA (   scc,
  chan,
  val 
)
Value:
{ \
(val) = (scc)->scc_channel[(chan)].scc_data; \
}

Definition at line 114 of file sccreg.h.

◆ SCC_READ_REG

#define SCC_READ_REG (   scc,
  chan,
  reg,
  val 
)
Value:
{ \
(scc)->scc_channel[(chan)].scc_command = (reg); \
(val) = (scc)->scc_channel[(chan)].scc_command; \
}
#define reg(x)

Definition at line 96 of file sccreg.h.

◆ SCC_READ_REG_ZERO

#define SCC_READ_REG_ZERO (   scc,
  chan,
  val 
)
Value:
{ \
(val) = (scc)->scc_channel[(chan)].scc_command; \
}

Definition at line 101 of file sccreg.h.

◆ SCC_RECV_BUFFER

#define SCC_RECV_BUFFER   SCC_RR8

Definition at line 197 of file sccreg.h.

◆ SCC_RECV_FIFO_DEEP

#define SCC_RECV_FIFO_DEEP   3

Definition at line 198 of file sccreg.h.

◆ SCC_RESET_ERROR

#define SCC_RESET_ERROR   0x30

Definition at line 231 of file sccreg.h.

◆ SCC_RESET_EXT_IP

#define SCC_RESET_EXT_IP   0x10

Definition at line 235 of file sccreg.h.

◆ SCC_RESET_HIGHEST_IUS

#define SCC_RESET_HIGHEST_IUS   0x38 /* channel A only */

Definition at line 230 of file sccreg.h.

◆ SCC_RESET_RX_CRC

#define SCC_RESET_RX_CRC   0x40

Definition at line 229 of file sccreg.h.

◆ SCC_RESET_TX_CRC

#define SCC_RESET_TX_CRC   0x80

Definition at line 228 of file sccreg.h.

◆ SCC_RESET_TX_IP

#define SCC_RESET_TX_IP   0x28

Definition at line 232 of file sccreg.h.

◆ SCC_RESET_TXURUN_LATCH

#define SCC_RESET_TXURUN_LATCH   0xc0

Definition at line 227 of file sccreg.h.

◆ SCC_RR0

#define SCC_RR0   0 /* status register */

Definition at line 122 of file sccreg.h.

Referenced by dev_scc_init(), and DEVICE_TICK().

◆ SCC_RR0_ABORT

#define SCC_RR0_ABORT   0x80 /* abort (synchr) */

Definition at line 153 of file sccreg.h.

◆ SCC_RR0_BREAK

#define SCC_RR0_BREAK   0x80 /* break detected (rings twice), or */

Definition at line 152 of file sccreg.h.

◆ SCC_RR0_CTS

#define SCC_RR0_CTS
Value:
0x20 /* clear-to-send pin active (sampled
only on intr and after RESI cmd */

Definition at line 155 of file sccreg.h.

◆ SCC_RR0_DCD

#define SCC_RR0_DCD   0x08 /* carrier-detect (same as CTS) */

Definition at line 158 of file sccreg.h.

◆ SCC_RR0_RX_AVAIL

#define SCC_RR0_RX_AVAIL   0x01 /* recv fifo not empty */

Definition at line 161 of file sccreg.h.

Referenced by DEVICE_TICK().

◆ SCC_RR0_SYNCH

#define SCC_RR0_SYNCH   0x10 /* SYNCH found/still hunting */

Definition at line 157 of file sccreg.h.

◆ SCC_RR0_TX_EMPTY

#define SCC_RR0_TX_EMPTY   0x04 /* xmit buffer empty */

Definition at line 159 of file sccreg.h.

Referenced by DEVICE_TICK().

◆ SCC_RR0_TX_UNDERRUN

#define SCC_RR0_TX_UNDERRUN   0x40 /* xmit buffer empty/end of message */

Definition at line 154 of file sccreg.h.

Referenced by dev_scc_init().

◆ SCC_RR0_ZERO_COUNT

#define SCC_RR0_ZERO_COUNT   0x02 /* ? */

Definition at line 160 of file sccreg.h.

◆ SCC_RR1

#define SCC_RR1   1 /* special receive conditions */

Definition at line 123 of file sccreg.h.

Referenced by DEVICE_TICK().

◆ SCC_RR10

#define SCC_RR10   10 /* sdlc status */

Definition at line 127 of file sccreg.h.

◆ SCC_RR10_1CLKS

#define SCC_RR10_1CLKS   0x80

Definition at line 200 of file sccreg.h.

◆ SCC_RR10_2CLKS

#define SCC_RR10_2CLKS   0x40

Definition at line 201 of file sccreg.h.

◆ SCC_RR10_LOOP_SND

#define SCC_RR10_LOOP_SND   0x10

Definition at line 203 of file sccreg.h.

◆ SCC_RR10_ON_LOOP

#define SCC_RR10_ON_LOOP   0x02

Definition at line 204 of file sccreg.h.

◆ SCC_RR10_zero

#define SCC_RR10_zero   0x2d

Definition at line 202 of file sccreg.h.

◆ SCC_RR12

#define SCC_RR12   12 /* BRG constant, low part */

Definition at line 128 of file sccreg.h.

Referenced by DEVICE_ACCESS().

◆ SCC_RR13

#define SCC_RR13   13 /* BRG constant, high part */

Definition at line 129 of file sccreg.h.

Referenced by DEVICE_ACCESS().

◆ SCC_RR15

#define SCC_RR15   15 /* interrupts currently enabled */

Definition at line 130 of file sccreg.h.

◆ SCC_RR15_BREAK_IE

#define SCC_RR15_BREAK_IE   0x80

Definition at line 215 of file sccreg.h.

◆ SCC_RR15_CTS_IE

#define SCC_RR15_CTS_IE   0x20

Definition at line 217 of file sccreg.h.

◆ SCC_RR15_DCD_IE

#define SCC_RR15_DCD_IE   0x08

Definition at line 219 of file sccreg.h.

◆ SCC_RR15_SYNCH_IE

#define SCC_RR15_SYNCH_IE   0x10

Definition at line 218 of file sccreg.h.

◆ SCC_RR15_TX_UNDERRUN_IE

#define SCC_RR15_TX_UNDERRUN_IE   0x40

Definition at line 216 of file sccreg.h.

◆ SCC_RR15_zero

#define SCC_RR15_zero   0x05

Definition at line 220 of file sccreg.h.

◆ SCC_RR15_ZERO_COUNT_IE

#define SCC_RR15_ZERO_COUNT_IE   0x02

Definition at line 221 of file sccreg.h.

◆ SCC_RR1_ALL_SENT

#define SCC_RR1_ALL_SENT   0x01

Definition at line 171 of file sccreg.h.

◆ SCC_RR1_CRC_ERR

#define SCC_RR1_CRC_ERR   0x40 /* incorrect CRC or.. */

Definition at line 164 of file sccreg.h.

◆ SCC_RR1_EOF

#define SCC_RR1_EOF   0x80 /* end-of-frame, SDLC mode */

Definition at line 163 of file sccreg.h.

◆ SCC_RR1_FRAME_ERR

#define SCC_RR1_FRAME_ERR   0x40 /* ..bad frame */

Definition at line 165 of file sccreg.h.

◆ SCC_RR1_PARITY_ERR

#define SCC_RR1_PARITY_ERR   0x10 /* incorrect parity in data */

Definition at line 167 of file sccreg.h.

◆ SCC_RR1_RESIDUE0

#define SCC_RR1_RESIDUE0   0x08

Definition at line 168 of file sccreg.h.

◆ SCC_RR1_RESIDUE1

#define SCC_RR1_RESIDUE1   0x04

Definition at line 169 of file sccreg.h.

◆ SCC_RR1_RESIDUE2

#define SCC_RR1_RESIDUE2   0x02

Definition at line 170 of file sccreg.h.

◆ SCC_RR1_RX_OVERRUN

#define SCC_RR1_RX_OVERRUN   0x20 /* rcv fifo overflow */

Definition at line 166 of file sccreg.h.

◆ SCC_RR2

#define SCC_RR2   2 /* (modified) interrupt vector */

Definition at line 124 of file sccreg.h.

◆ SCC_RR2_A_EXT_STATUS

#define SCC_RR2_A_EXT_STATUS   0xa

Definition at line 183 of file sccreg.h.

◆ SCC_RR2_A_RECV_DONE

#define SCC_RR2_A_RECV_DONE   0xc

Definition at line 184 of file sccreg.h.

◆ SCC_RR2_A_RECV_SPECIAL

#define SCC_RR2_A_RECV_SPECIAL   0xe

Definition at line 185 of file sccreg.h.

◆ SCC_RR2_A_XMIT_DONE

#define SCC_RR2_A_XMIT_DONE   0x8

Definition at line 182 of file sccreg.h.

◆ SCC_RR2_B_EXT_STATUS

#define SCC_RR2_B_EXT_STATUS   0x2

Definition at line 179 of file sccreg.h.

◆ SCC_RR2_B_RECV_DONE

#define SCC_RR2_B_RECV_DONE   0x4

Definition at line 180 of file sccreg.h.

◆ SCC_RR2_B_RECV_SPECIAL

#define SCC_RR2_B_RECV_SPECIAL   0x6

Definition at line 181 of file sccreg.h.

◆ SCC_RR2_B_XMIT_DONE

#define SCC_RR2_B_XMIT_DONE   0x0

Definition at line 178 of file sccreg.h.

◆ SCC_RR2_STATUS

#define SCC_RR2_STATUS (   val)    ((val)&0xf)

Definition at line 176 of file sccreg.h.

◆ SCC_RR3

#define SCC_RR3   3 /* interrupts pending (cha A only) */

Definition at line 125 of file sccreg.h.

Referenced by DEVICE_ACCESS().

◆ SCC_RR3_EXT_IP_A

#define SCC_RR3_EXT_IP_A   0x08

Definition at line 191 of file sccreg.h.

◆ SCC_RR3_EXT_IP_B

#define SCC_RR3_EXT_IP_B   0x01

Definition at line 194 of file sccreg.h.

◆ SCC_RR3_RX_IP_A

#define SCC_RR3_RX_IP_A   0x20

Definition at line 189 of file sccreg.h.

◆ SCC_RR3_RX_IP_B

#define SCC_RR3_RX_IP_B   0x04

Definition at line 192 of file sccreg.h.

◆ SCC_RR3_TX_IP_A

#define SCC_RR3_TX_IP_A   0x10

Definition at line 190 of file sccreg.h.

◆ SCC_RR3_TX_IP_B

#define SCC_RR3_TX_IP_B   0x02

Definition at line 193 of file sccreg.h.

◆ SCC_RR3_zero

#define SCC_RR3_zero   0xc0

Definition at line 188 of file sccreg.h.

◆ SCC_RR8

#define SCC_RR8   8 /* recv buffer (alias for data) */

Definition at line 126 of file sccreg.h.

◆ SCC_SEND_SDLC_ABORT

#define SCC_SEND_SDLC_ABORT   0x18

Definition at line 234 of file sccreg.h.

◆ SCC_SET_TIMING_BASE

#define SCC_SET_TIMING_BASE (   scc,
  chan,
  val 
)
Value:
{ \
SCC_WRITE_REG(scc,chan,SCC_RR12,val);\
SCC_WRITE_REG(scc,chan,SCC_RR13,(val)>>8);\
}
#define SCC_RR13
Definition: sccreg.h:129
#define SCC_RR12
Definition: sccreg.h:128

Definition at line 337 of file sccreg.h.

◆ SCC_WR0

#define SCC_WR0   0 /* reg select, and commands */

Definition at line 132 of file sccreg.h.

◆ SCC_WR1

#define SCC_WR1   1 /* interrupt and DMA enables */

Definition at line 133 of file sccreg.h.

◆ SCC_WR10

#define SCC_WR10   10 /* synchr params */

Definition at line 142 of file sccreg.h.

◆ SCC_WR10_6BIT_SYNCH

#define SCC_WR10_6BIT_SYNCH   0x01

Definition at line 318 of file sccreg.h.

◆ SCC_WR10_8BIT_SYNCH

#define SCC_WR10_8BIT_SYNCH   0x00

Definition at line 319 of file sccreg.h.

◆ SCC_WR10_ABORT_ON_URUN

#define SCC_WR10_ABORT_ON_URUN   0x04 /* flag if zero */

Definition at line 316 of file sccreg.h.

◆ SCC_WR10_ACTIVE_ON_POLL

#define SCC_WR10_ACTIVE_ON_POLL   0x10

Definition at line 314 of file sccreg.h.

◆ SCC_WR10_CRC_PRESET

#define SCC_WR10_CRC_PRESET   0x80

Definition at line 309 of file sccreg.h.

◆ SCC_WR10_FM0

#define SCC_WR10_FM0   0x60

Definition at line 310 of file sccreg.h.

◆ SCC_WR10_FM1

#define SCC_WR10_FM1   0x40

Definition at line 311 of file sccreg.h.

◆ SCC_WR10_LOOP_MODE

#define SCC_WR10_LOOP_MODE   0x02

Definition at line 317 of file sccreg.h.

◆ SCC_WR10_MARK_IDLE

#define SCC_WR10_MARK_IDLE   0x08 /* flag if zero */

Definition at line 315 of file sccreg.h.

◆ SCC_WR10_NRZ

#define SCC_WR10_NRZ   0x00

Definition at line 313 of file sccreg.h.

◆ SCC_WR10_NRZI

#define SCC_WR10_NRZI   0x20

Definition at line 312 of file sccreg.h.

◆ SCC_WR11

#define SCC_WR11   11 /* clocking definitions */

Definition at line 143 of file sccreg.h.

◆ SCC_WR11_RCLK_BAUDR

#define SCC_WR11_RCLK_BAUDR   0x40 /* .. on BRG */

Definition at line 323 of file sccreg.h.

◆ SCC_WR11_RCLK_DPLL

#define SCC_WR11_RCLK_DPLL   0x60 /* clock received data on dpll */

Definition at line 322 of file sccreg.h.

◆ SCC_WR11_RCLK_RTc_PIN

#define SCC_WR11_RCLK_RTc_PIN   0x00 /* .. on RTxC pin */

Definition at line 325 of file sccreg.h.

◆ SCC_WR11_RCLK_TRc_PIN

#define SCC_WR11_RCLK_TRc_PIN   0x20 /* .. on TRxC pin */

Definition at line 324 of file sccreg.h.

◆ SCC_WR11_RTxC_XTAL

#define SCC_WR11_RTxC_XTAL   0x80 /* RTxC pin is input (ext oscill) */

Definition at line 321 of file sccreg.h.

◆ SCC_WR11_TRc_OUT

#define SCC_WR11_TRc_OUT   0x04 /* drive TRxC pin as output from..*/

Definition at line 330 of file sccreg.h.

◆ SCC_WR11_TRcOUT_BAUDR

#define SCC_WR11_TRcOUT_BAUDR   0x02 /* .. the BRG */

Definition at line 332 of file sccreg.h.

◆ SCC_WR11_TRcOUT_DPLL

#define SCC_WR11_TRcOUT_DPLL   0x03 /* .. the dpll */

Definition at line 331 of file sccreg.h.

◆ SCC_WR11_TRcOUT_XMTCLK

#define SCC_WR11_TRcOUT_XMTCLK   0x01 /* .. the xmit clock */

Definition at line 333 of file sccreg.h.

◆ SCC_WR11_TRcOUT_XTAL

#define SCC_WR11_TRcOUT_XTAL   0x00 /* .. the external oscillator */

Definition at line 334 of file sccreg.h.

◆ SCC_WR11_XTLK_BAUDR

#define SCC_WR11_XTLK_BAUDR   0x10

Definition at line 327 of file sccreg.h.

◆ SCC_WR11_XTLK_DPLL

#define SCC_WR11_XTLK_DPLL   0x18

Definition at line 326 of file sccreg.h.

◆ SCC_WR11_XTLK_RTc_PIN

#define SCC_WR11_XTLK_RTc_PIN   0x00

Definition at line 329 of file sccreg.h.

◆ SCC_WR11_XTLK_TRc_PIN

#define SCC_WR11_XTLK_TRc_PIN   0x08

Definition at line 328 of file sccreg.h.

◆ SCC_WR12

#define SCC_WR12   12 /* BRG constant, low part */

Definition at line 144 of file sccreg.h.

Referenced by DEVICE_ACCESS().

◆ SCC_WR13

#define SCC_WR13   13 /* BRG constant, high part */

Definition at line 145 of file sccreg.h.

Referenced by DEVICE_ACCESS().

◆ SCC_WR14

#define SCC_WR14   14 /* BRG enables and commands */

Definition at line 146 of file sccreg.h.

Referenced by dev_scc_dma_func().

◆ SCC_WR14_AUTO_ECHO

#define SCC_WR14_AUTO_ECHO   0x08

Definition at line 352 of file sccreg.h.

◆ SCC_WR14_BAUDR_ENABLE

#define SCC_WR14_BAUDR_ENABLE   0x01

Definition at line 355 of file sccreg.h.

◆ SCC_WR14_BAUDR_SOURCE

#define SCC_WR14_BAUDR_SOURCE   0x80 /* .. or internal BRG */

Definition at line 346 of file sccreg.h.

◆ SCC_WR14_BAUDR_SRC

#define SCC_WR14_BAUDR_SRC   0x02

Definition at line 354 of file sccreg.h.

◆ SCC_WR14_DISABLE_DPLL

#define SCC_WR14_DISABLE_DPLL   0x60

Definition at line 347 of file sccreg.h.

◆ SCC_WR14_DTR_REQUEST

#define SCC_WR14_DTR_REQUEST   0x04

Definition at line 353 of file sccreg.h.

◆ SCC_WR14_FM_MODE

#define SCC_WR14_FM_MODE   0xc0

Definition at line 344 of file sccreg.h.

◆ SCC_WR14_LOCAL_LOOPB

#define SCC_WR14_LOCAL_LOOPB   0x10

Definition at line 351 of file sccreg.h.

Referenced by dev_scc_dma_func().

◆ SCC_WR14_NRZI_MODE

#define SCC_WR14_NRZI_MODE   0xe0 /* synch modulations */

Definition at line 343 of file sccreg.h.

◆ SCC_WR14_RESET_CLKMISS

#define SCC_WR14_RESET_CLKMISS   0x40

Definition at line 348 of file sccreg.h.

◆ SCC_WR14_RTc_SOURCE

#define SCC_WR14_RTc_SOURCE   0xa0 /* clock is from pin .. */

Definition at line 345 of file sccreg.h.

◆ SCC_WR14_SEARCH_MODE

#define SCC_WR14_SEARCH_MODE   0x20

Definition at line 349 of file sccreg.h.

◆ SCC_WR15

#define SCC_WR15   15 /* interrupt enables */

Definition at line 147 of file sccreg.h.

◆ SCC_WR15_BREAK_IE

#define SCC_WR15_BREAK_IE   0x80

Definition at line 357 of file sccreg.h.

◆ SCC_WR15_CTS_IE

#define SCC_WR15_CTS_IE   0x20

Definition at line 359 of file sccreg.h.

◆ SCC_WR15_DCD_IE

#define SCC_WR15_DCD_IE   0x08

Definition at line 361 of file sccreg.h.

◆ SCC_WR15_SYNCHUNT_IE

#define SCC_WR15_SYNCHUNT_IE   0x10

Definition at line 360 of file sccreg.h.

◆ SCC_WR15_TX_UNDERRUN_IE

#define SCC_WR15_TX_UNDERRUN_IE   0x40

Definition at line 358 of file sccreg.h.

◆ SCC_WR15_zero

#define SCC_WR15_zero   0x05

Definition at line 362 of file sccreg.h.

◆ SCC_WR15_ZERO_COUNT_IE

#define SCC_WR15_ZERO_COUNT_IE   0x02

Definition at line 363 of file sccreg.h.

◆ SCC_WR1_DMA_ENABLE

#define SCC_WR1_DMA_ENABLE   0x80 /* dma control */

Definition at line 237 of file sccreg.h.

◆ SCC_WR1_DMA_MODE

#define SCC_WR1_DMA_MODE   0x40 /* drive ~req for DMA controller */

Definition at line 238 of file sccreg.h.

◆ SCC_WR1_DMA_RECV_DATA

#define SCC_WR1_DMA_RECV_DATA   0x20 /* from wire to host memory */

Definition at line 239 of file sccreg.h.

◆ SCC_WR1_EXT_IE

#define SCC_WR1_EXT_IE   0x01

Definition at line 247 of file sccreg.h.

◆ SCC_WR1_PARITY_IE

#define SCC_WR1_PARITY_IE   0x04 /* on parity errors */

Definition at line 245 of file sccreg.h.

◆ SCC_WR1_RXI_ALL_CHAR

#define SCC_WR1_RXI_ALL_CHAR   0x10 /* on each char, or special */

Definition at line 242 of file sccreg.h.

◆ SCC_WR1_RXI_DISABLE

#define SCC_WR1_RXI_DISABLE   0x00 /* never on recv */

Definition at line 244 of file sccreg.h.

◆ SCC_WR1_RXI_FIRST_CHAR

#define SCC_WR1_RXI_FIRST_CHAR   0x08 /* on first char, or special */

Definition at line 243 of file sccreg.h.

◆ SCC_WR1_RXI_SPECIAL_O

#define SCC_WR1_RXI_SPECIAL_O   0x18 /* on special only */

Definition at line 241 of file sccreg.h.

◆ SCC_WR1_TX_IE

#define SCC_WR1_TX_IE   0x02

Definition at line 246 of file sccreg.h.

◆ SCC_WR2

#define SCC_WR2   2 /* interrupt vector */

Definition at line 134 of file sccreg.h.

◆ SCC_WR3

#define SCC_WR3   3 /* receiver params and enables */

Definition at line 135 of file sccreg.h.

◆ SCC_WR3_AUTO_ENABLE

#define SCC_WR3_AUTO_ENABLE   0x20

Definition at line 255 of file sccreg.h.

◆ SCC_WR3_HUNT_MODE

#define SCC_WR3_HUNT_MODE   0x10

Definition at line 256 of file sccreg.h.

◆ SCC_WR3_INHIBIT_SYNCH

#define SCC_WR3_INHIBIT_SYNCH   0x02

Definition at line 259 of file sccreg.h.

◆ SCC_WR3_RX_5_BITS

#define SCC_WR3_RX_5_BITS   0x00

Definition at line 254 of file sccreg.h.

◆ SCC_WR3_RX_6_BITS

#define SCC_WR3_RX_6_BITS   0x80

Definition at line 252 of file sccreg.h.

◆ SCC_WR3_RX_7_BITS

#define SCC_WR3_RX_7_BITS   0x40

Definition at line 253 of file sccreg.h.

◆ SCC_WR3_RX_8_BITS

#define SCC_WR3_RX_8_BITS   0xc0

Definition at line 251 of file sccreg.h.

◆ SCC_WR3_RX_CRC_ENABLE

#define SCC_WR3_RX_CRC_ENABLE   0x08

Definition at line 257 of file sccreg.h.

◆ SCC_WR3_RX_ENABLE

#define SCC_WR3_RX_ENABLE   0x01

Definition at line 260 of file sccreg.h.

◆ SCC_WR3_SDLC_SRCH

#define SCC_WR3_SDLC_SRCH   0x04

Definition at line 258 of file sccreg.h.

◆ SCC_WR4

#define SCC_WR4   4 /* clock/char/parity params */

Definition at line 136 of file sccreg.h.

◆ SCC_WR4_16BIT_SYNCH

#define SCC_WR4_16BIT_SYNCH   0x10

Definition at line 269 of file sccreg.h.

◆ SCC_WR4_1_5_STOP

#define SCC_WR4_1_5_STOP   0x08

Definition at line 272 of file sccreg.h.

◆ SCC_WR4_1_STOP

#define SCC_WR4_1_STOP   0x04

Definition at line 273 of file sccreg.h.

◆ SCC_WR4_2_STOP

#define SCC_WR4_2_STOP   0x0c /* asynch modes */

Definition at line 271 of file sccreg.h.

◆ SCC_WR4_8BIT_SYNCH

#define SCC_WR4_8BIT_SYNCH   0x00

Definition at line 270 of file sccreg.h.

◆ SCC_WR4_CLK_x1

#define SCC_WR4_CLK_x1   0x00

Definition at line 266 of file sccreg.h.

◆ SCC_WR4_CLK_x16

#define SCC_WR4_CLK_x16   0x40

Definition at line 265 of file sccreg.h.

◆ SCC_WR4_CLK_x32

#define SCC_WR4_CLK_x32   0x80

Definition at line 264 of file sccreg.h.

◆ SCC_WR4_CLK_x64

#define SCC_WR4_CLK_x64   0xc0 /* clock divide factor */

Definition at line 263 of file sccreg.h.

◆ SCC_WR4_EVEN_PARITY

#define SCC_WR4_EVEN_PARITY   0x02

Definition at line 275 of file sccreg.h.

◆ SCC_WR4_EXT_SYNCH_MODE

#define SCC_WR4_EXT_SYNCH_MODE   0x30 /* synch modes */

Definition at line 267 of file sccreg.h.

◆ SCC_WR4_PARITY_ENABLE

#define SCC_WR4_PARITY_ENABLE   0x01

Definition at line 276 of file sccreg.h.

◆ SCC_WR4_SDLC_MODE

#define SCC_WR4_SDLC_MODE   0x20

Definition at line 268 of file sccreg.h.

◆ SCC_WR4_SYNCH_MODE

#define SCC_WR4_SYNCH_MODE   0x00

Definition at line 274 of file sccreg.h.

◆ SCC_WR5

#define SCC_WR5   5 /* xmit params and enables */

Definition at line 137 of file sccreg.h.

◆ SCC_WR5_CRC_16

#define SCC_WR5_CRC_16   0x04 /* CRC if non zero, .. */

Definition at line 285 of file sccreg.h.

◆ SCC_WR5_DTR

#define SCC_WR5_DTR   0x80 /* drive DTR pin */

Definition at line 278 of file sccreg.h.

◆ SCC_WR5_RTS

#define SCC_WR5_RTS   0x02 /* drive RTS pin */

Definition at line 287 of file sccreg.h.

◆ SCC_WR5_SDLC

#define SCC_WR5_SDLC   0x00 /* ..SDLC otherwise */

Definition at line 286 of file sccreg.h.

◆ SCC_WR5_SEND_BREAK

#define SCC_WR5_SEND_BREAK   0x10

Definition at line 283 of file sccreg.h.

◆ SCC_WR5_TX_5_BITS

#define SCC_WR5_TX_5_BITS   0x00

Definition at line 282 of file sccreg.h.

◆ SCC_WR5_TX_6_BITS

#define SCC_WR5_TX_6_BITS   0x40

Definition at line 280 of file sccreg.h.

◆ SCC_WR5_TX_7_BITS

#define SCC_WR5_TX_7_BITS   0x20

Definition at line 281 of file sccreg.h.

◆ SCC_WR5_TX_8_BITS

#define SCC_WR5_TX_8_BITS   0x60

Definition at line 279 of file sccreg.h.

◆ SCC_WR5_TX_CRC_ENABLE

#define SCC_WR5_TX_CRC_ENABLE   0x01

Definition at line 288 of file sccreg.h.

◆ SCC_WR5_TX_ENABLE

#define SCC_WR5_TX_ENABLE   0x08

Definition at line 284 of file sccreg.h.

◆ SCC_WR6

#define SCC_WR6   6 /* synchr SYNCH/address */

Definition at line 138 of file sccreg.h.

◆ SCC_WR6_BISYNCH_12

#define SCC_WR6_BISYNCH_12   0x0f

Definition at line 292 of file sccreg.h.

◆ SCC_WR6_SDLC_RANGE_MASK

#define SCC_WR6_SDLC_RANGE_MASK   0x0f

Definition at line 293 of file sccreg.h.

◆ SCC_WR7

#define SCC_WR7   7 /* synchr SYNCH/flag */

Definition at line 139 of file sccreg.h.

◆ SCC_WR7_SDLC_FLAG

#define SCC_WR7_SDLC_FLAG   0x7e

Definition at line 294 of file sccreg.h.

◆ SCC_WR8

#define SCC_WR8   8 /* xmit buffer (alias for data) */

Definition at line 140 of file sccreg.h.

◆ SCC_WR9

#define SCC_WR9   9 /* vectoring and resets */

Definition at line 141 of file sccreg.h.

◆ SCC_WR9_DLC

#define SCC_WR9_DLC   0x04 /* disable-lower-chain */

Definition at line 305 of file sccreg.h.

◆ SCC_WR9_HW_RESET

#define SCC_WR9_HW_RESET   0xc0 /* force hardware reset */

Definition at line 299 of file sccreg.h.

◆ SCC_WR9_MASTER_IE

#define SCC_WR9_MASTER_IE   0x08

Definition at line 304 of file sccreg.h.

◆ SCC_WR9_NON_VECTORED

#define SCC_WR9_NON_VECTORED   0x20 /* mbz for Zilog chip */

Definition at line 302 of file sccreg.h.

◆ SCC_WR9_NV

#define SCC_WR9_NV   0x02 /* no vector */

Definition at line 306 of file sccreg.h.

◆ SCC_WR9_RESET_CHA_A

#define SCC_WR9_RESET_CHA_A   0x80

Definition at line 300 of file sccreg.h.

◆ SCC_WR9_RESET_CHA_B

#define SCC_WR9_RESET_CHA_B   0x40

Definition at line 301 of file sccreg.h.

◆ SCC_WR9_STATUS_HIGH

#define SCC_WR9_STATUS_HIGH   0x10

Definition at line 303 of file sccreg.h.

◆ SCC_WR9_VIS

#define SCC_WR9_VIS   0x01 /* vector-includes-status */

Definition at line 307 of file sccreg.h.

◆ SCC_WRITE_DATA

#define SCC_WRITE_DATA (   scc,
  chan,
  val 
)
Value:
{ \
(scc)->scc_channel[(chan)].scc_data = (val); \
}

Definition at line 118 of file sccreg.h.

◆ SCC_WRITE_REG

#define SCC_WRITE_REG (   scc,
  chan,
  reg,
  val 
)
Value:
{ \
(scc)->scc_channel[(chan)].scc_command = (reg); \
(scc)->scc_channel[(chan)].scc_command = (val); \
}
#define reg(x)

Definition at line 105 of file sccreg.h.

◆ SCC_WRITE_REG_ZERO

#define SCC_WRITE_REG_ZERO (   scc,
  chan,
  val 
)
Value:
{ \
(scc)->scc_channel[(chan)].scc_command = (val); \
}

Definition at line 110 of file sccreg.h.

◆ SCC_XMT_BUFFER

#define SCC_XMT_BUFFER   SCC_WR8

Definition at line 297 of file sccreg.h.

◆ SCCCOMM2_PORT

#define SCCCOMM2_PORT   0x0

Definition at line 381 of file sccreg.h.

◆ SCCCOMM3_PORT

#define SCCCOMM3_PORT   0x2

Definition at line 383 of file sccreg.h.

◆ SCCKBD_PORT

#define SCCKBD_PORT   0x3

Definition at line 384 of file sccreg.h.

◆ SCCMOUSE_PORT

#define SCCMOUSE_PORT   0x1

Definition at line 382 of file sccreg.h.

Typedef Documentation

◆ scc_regmap_t

typedef struct scc_regmap scc_regmap_t

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