55 #define PCI_PRODUCT_GALILEO_GT64011 0x4146 56 #define PCI_PRODUCT_GALILEO_GT64120 0x4620 57 #define PCI_PRODUCT_GALILEO_GT64260 0x6430 80 static void timer_tick(
struct timer *
timer,
void *extra)
98 uint64_t idata = 0, odata = 0;
99 int bus, dev, func,
reg;
105 switch (relative_addr) {
117 odata = d->
decode[relative_addr / 8];
118 debug(
"[ gt: read from offset 0x%x: 0x%x ]\n",
119 (
int)relative_addr, (
int)odata);
121 d->
decode[relative_addr / 8] = idata;
122 fatal(
"[ gt: write to offset 0x%x: 0x%x (TODO) ]\n",
123 (
int)relative_addr, (
int)idata);
129 debug(
"[ gt: write to GT_PCI0_CMD: 0x%08x (TODO) ]\n",
132 debug(
"[ gt: read from GT_PCI0_CMD (0x%08x) (TODO) ]\n",
139 debug(
"[ gt: write to GT_INTR_CAUSE: 0x%08x ]\n",
149 debug(
"[ gt: read from GT_INTR_CAUSE (0x%08x) ]\n",
164 if (d->
timer == NULL)
177 if (len ==
sizeof(uint32_t))
180 + (
data[2] << 16) + (
data[3] << 24);
190 if (len ==
sizeof(uint32_t))
193 + (
data[2] << 16) + (
data[3] << 24);
197 &odata : &idata, len, writeflag);
202 debug(
"[ gt: read from addr 0x%x ]\n",
205 debug(
"[ gt: write to addr 0x%x:", (
int)relative_addr);
206 for (i=0; i<len; i++)
226 uint64_t baseaddr,
const char *timer_irq_path,
const char *isa_irq_path,
int type)
229 uint64_t pci_portbase = 0, pci_membase = 0;
230 uint64_t isa_portbase = 0, isa_membase = 0;
231 uint64_t pci_io_offset = 0, pci_mem_offset = 0;
232 const char *gt_name =
"NO";
235 memset(d, 0,
sizeof(
struct gt_data));
246 pci_portbase = 0x10000000ULL;
247 pci_membase = 0x10100000ULL;
248 isa_portbase = 0x10000000ULL;
249 isa_membase = 0x10100000ULL;
257 pci_portbase = 0x18000000ULL;
258 pci_membase = 0x10000000ULL;
259 isa_portbase = 0x18000000ULL;
260 isa_membase = 0x10000000ULL;
268 pci_portbase = 0x18000000ULL;
269 pci_membase = 0x10000000ULL;
270 isa_portbase = 0x18000000ULL;
271 isa_membase = 0x10000000ULL;
273 default:
fatal(
"dev_gt_init(): unimplemented GT type (%i).\n", type);
292 "TODO_gt_irq", pci_io_offset, pci_mem_offset,
293 pci_portbase, pci_membase,
"TODO_pci_irqbase",
294 isa_portbase, isa_membase, isa_irq_path);
uint64_t memory_readmax64(struct cpu *cpu, unsigned char *buf, int len)
void fatal(const char *fmt,...)
#define GT_PCI0IOREMAP_OFS
#define PCI_PRODUCT_GALILEO_GT64011
void bus_pci_add(struct machine *machine, struct pci_data *pci_data, struct memory *mem, int bus, int device, int function, const char *name)
struct pci_data * pci_data
int pending_timer0_interrupts
struct isa_pic_data isa_pic_data
#define EMUL_LITTLE_ENDIAN
int dev_gt_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *)
#define CHECK_ALLOCATION(ptr)
void timer_update_frequency(struct timer *t, double new_freq)
void bus_pci_setaddr(struct cpu *cpu, struct pci_data *pci_data, int bus, int device, int function, int reg)
struct pci_data * dev_gt_init(struct machine *machine, struct memory *mem, uint64_t baseaddr, const char *timer_irq_path, const char *isa_irq_path, int type)
struct timer * timer_add(double freq, void(*timer_tick)(struct timer *timer, void *extra), void *extra)
#define INTERRUPT_ASSERT(istruct)
uint32_t decode[GT_N_DECODE_REGS]
#define PCI_PRODUCT_GALILEO_GT64120
#define INTERRUPT_CONNECT(name, istruct)
void memory_writemax64(struct cpu *cpu, unsigned char *buf, int len, uint64_t data)
void memory_device_register(struct memory *mem, const char *, uint64_t baseaddr, uint64_t len, int(*f)(struct cpu *, struct memory *, uint64_t, unsigned char *, size_t, int, void *), void *extra, int flags, unsigned char *dyntrans_data)
void bus_pci_decompose_1(uint32_t t, int *bus, int *dev, int *func, int *reg)
#define GT_PCI0M0REMAP_OFS
#define PCI_PRODUCT_GALILEO_GT64260
struct pci_data * bus_pci_init(struct machine *machine, const char *irq_path, uint64_t pci_actual_io_offset, uint64_t pci_actual_mem_offset, uint64_t pci_portbase, uint64_t pci_membase, const char *pci_irqbase, uint64_t isa_portbase, uint64_t isa_membase, const char *isa_irqbase)
void machine_add_tickfunction(struct machine *machine, void(*func)(struct cpu *, void *), void *extra, int clockshift)
struct interrupt timer0_irq
void bus_pci_data_access(struct cpu *cpu, struct pci_data *pci_data, uint64_t *data, int len, int writeflag)
#define GT_PCI0M1REMAP_OFS
#define INTERRUPT_DEASSERT(istruct)