dev_sh4.cc File Reference

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Classes | Macros | Functions
dev_sh4.cc File Reference
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "bus_pci.h"
#include "console.h"
#include "cpu.h"
#include "device.h"
#include "devices.h"
#include "interrupt.h"
#include "machine.h"
#include "memory.h"
#include "misc.h"
#include "sh4_dmacreg.h"
#include "timer.h"
#include "thirdparty/sh4_bscreg.h"
#include "thirdparty/sh4_cache.h"
#include "thirdparty/sh4_exception.h"
#include "thirdparty/sh4_intcreg.h"
#include "thirdparty/sh4_mmu.h"
#include "thirdparty/sh4_pcicreg.h"
#include "thirdparty/sh4_rtcreg.h"
#include "thirdparty/sh4_scifreg.h"
#include "thirdparty/sh4_scireg.h"
#include "thirdparty/sh4_tmureg.h"

Go to the source code of this file.

Classes

struct  sh4_data
 

Macros

#define SH4_REG_BASE   0xff000000
 
#define SH4_TICK_SHIFT   14
 
#define N_SH4_TIMERS   3
 
#define N_PCIC_REGS   (0x224 / sizeof(uint32_t))
 
#define N_PCIC_IRQS   16
 
#define PCIC_REG(addr)   ((addr - SH4_PCIC) / sizeof(uint32_t))
 
#define PCI_VENDOR_HITACHI   0x1054
 
#define PCI_PRODUCT_HITACHI_SH7751   0x3505
 
#define PCI_PRODUCT_HITACHI_SH7751R   0x350e
 
#define SCIF_TX_FIFO_SIZE   16
 
#define SCIF_DELAYED_TX_VALUE   2 /* 2 to be safe, 1 = fast but buggy */
 
#define SH4_CPG_FRQCR   0xffc00000 /* 16-bit */
 
#define SH4_CPG_STBCR   0xffc00004 /* 8-bit */
 
#define SH4_CPG_WTCNT   0xffc00008 /* 8/16-bit */
 
#define SH4_CPG_WTCSR   0xffc0000c /* 8/16-bit */
 
#define SH4_CPG_STBCR2   0xffc00010 /* 8-bit */
 
#define SH4_PSEUDO_TIMER_HZ   110.0
 

Functions

 DEVICE_TICK (sh4)
 
void sh4_dmac_transfer (struct cpu *cpu, struct sh4_data *d, int channel)
 
 DEVICE_ACCESS (sh4_itlb_aa)
 
 DEVICE_ACCESS (sh4_itlb_da1)
 
 DEVICE_ACCESS (sh4_utlb_aa)
 
 DEVICE_ACCESS (sh4_utlb_da1)
 
 DEVICE_ACCESS (sh4_pcic)
 
 DEVICE_ACCESS (sh4_sq)
 
 DEVICE_ACCESS (sh4)
 
 DEVINIT (sh4)
 

Macro Definition Documentation

◆ N_PCIC_IRQS

#define N_PCIC_IRQS   16

Definition at line 73 of file dev_sh4.cc.

Referenced by DEVINIT().

◆ N_PCIC_REGS

#define N_PCIC_REGS   (0x224 / sizeof(uint32_t))

Definition at line 72 of file dev_sh4.cc.

Referenced by DEVINIT().

◆ N_SH4_TIMERS

#define N_SH4_TIMERS   3

Definition at line 69 of file dev_sh4.cc.

◆ PCI_PRODUCT_HITACHI_SH7751

#define PCI_PRODUCT_HITACHI_SH7751   0x3505

Definition at line 76 of file dev_sh4.cc.

Referenced by DEVICE_ACCESS().

◆ PCI_PRODUCT_HITACHI_SH7751R

#define PCI_PRODUCT_HITACHI_SH7751R   0x350e

Definition at line 77 of file dev_sh4.cc.

Referenced by DEVICE_ACCESS().

◆ PCI_VENDOR_HITACHI

#define PCI_VENDOR_HITACHI   0x1054

Definition at line 75 of file dev_sh4.cc.

Referenced by DEVICE_ACCESS().

◆ PCIC_REG

#define PCIC_REG (   addr)    ((addr - SH4_PCIC) / sizeof(uint32_t))

Definition at line 74 of file dev_sh4.cc.

Referenced by DEVICE_ACCESS(), and DEVINIT().

◆ SCIF_DELAYED_TX_VALUE

#define SCIF_DELAYED_TX_VALUE   2 /* 2 to be safe, 1 = fast but buggy */

Definition at line 80 of file dev_sh4.cc.

◆ SCIF_TX_FIFO_SIZE

#define SCIF_TX_FIFO_SIZE   16

Definition at line 79 of file dev_sh4.cc.

◆ SH4_CPG_FRQCR

#define SH4_CPG_FRQCR   0xffc00000 /* 16-bit */

Definition at line 88 of file dev_sh4.cc.

◆ SH4_CPG_STBCR

#define SH4_CPG_STBCR   0xffc00004 /* 8-bit */

Definition at line 89 of file dev_sh4.cc.

◆ SH4_CPG_STBCR2

#define SH4_CPG_STBCR2   0xffc00010 /* 8-bit */

Definition at line 92 of file dev_sh4.cc.

◆ SH4_CPG_WTCNT

#define SH4_CPG_WTCNT   0xffc00008 /* 8/16-bit */

Definition at line 90 of file dev_sh4.cc.

◆ SH4_CPG_WTCSR

#define SH4_CPG_WTCSR   0xffc0000c /* 8/16-bit */

Definition at line 91 of file dev_sh4.cc.

◆ SH4_PSEUDO_TIMER_HZ

#define SH4_PSEUDO_TIMER_HZ   110.0

Definition at line 176 of file dev_sh4.cc.

◆ SH4_REG_BASE

#define SH4_REG_BASE   0xff000000

Definition at line 67 of file dev_sh4.cc.

Referenced by DEVICE_ACCESS(), and DEVINIT().

◆ SH4_TICK_SHIFT

#define SH4_TICK_SHIFT   14

Definition at line 68 of file dev_sh4.cc.

Function Documentation

◆ DEVICE_ACCESS() [1/7]

DEVICE_ACCESS ( sh4_itlb_aa  )

◆ DEVICE_ACCESS() [2/7]

DEVICE_ACCESS ( sh4_itlb_da1  )

◆ DEVICE_ACCESS() [3/7]

DEVICE_ACCESS ( sh4_utlb_aa  )

◆ DEVICE_ACCESS() [4/7]

DEVICE_ACCESS ( sh4_utlb_da1  )

◆ DEVICE_ACCESS() [5/7]

DEVICE_ACCESS ( sh4_pcic  )

◆ DEVICE_ACCESS() [6/7]

DEVICE_ACCESS ( sh4_sq  )

Definition at line 950 of file dev_sh4.cc.

References data, MEM_WRITE, and sh4_data::sq.

◆ DEVICE_ACCESS() [7/7]

DEVICE_ACCESS ( sh4  )

Definition at line 967 of file dev_sh4.cc.

References BCR1_LITTLE_ENDIAN, sh4_data::bsc_bcr1, sh4_data::bsc_bcr2, sh4_data::bsc_bcr3, sh4_data::bsc_gpioic, sh4_data::bsc_mcr, sh4_data::bsc_pcr, sh4_data::bsc_rfcr, sh4_data::bsc_rtcor, sh4_data::bsc_rtcsr, sh4_data::bsc_wcr1, sh4_data::bsc_wcr2, sh4_data::bsc_wcr3, cpu::byte_order, sh_cpu::ccr, cpu::cd, CHCR_CHSET, CHCR_TD, sh_cpu::cpu_type, data, debug, sh_cpu::dmac_chcr, sh_cpu::dmac_dar, sh_cpu::dmac_sar, sh_cpu::dmac_tcr, sh_cpu::dmaor, DMAOR_DDT, DMAOR_DME, DMAOR_PR0, DMAOR_PR1, EMUL_LITTLE_ENDIAN, sh_cpu::expevt, fatal(), INTERRUPT_DEASSERT, sh_cpu::intevt, INVALIDATE_ALL, cpu::invalidate_translation_caches, sh_cpu::itlb_lo, MEM_READ, MEM_WRITE, memory_readmax64(), sh_cpu::mmucr, sh_cpu::pclock, sh4_data::pctra, sh4_data::pctrb, sh4_data::pdtra, sh4_data::pdtrb, sh_cpu_type_def::prr, sh_cpu::ptea, sh_cpu::pteh, sh_cpu::ptel, sh_cpu_type_def::pvr, sh_cpu::qacr0, sh_cpu::qacr1, RTCSR_CMF, sh4_data::sdmr2, sh4_data::sdmr3, cpu::sh, SH4_BCR1, SH4_BCR2, SH4_BCR3, SH4_CCR, SH4_CHCR0, SH4_CHCR1, SH4_CHCR2, SH4_CHCR3, SH4_CHCR4, SH4_CHCR5, SH4_CHCR6, SH4_CHCR7, SH4_DAR0, SH4_DAR1, SH4_DAR2, SH4_DAR3, SH4_DAR4, SH4_DAR5, SH4_DAR6, SH4_DAR7, sh4_dmac_transfer(), SH4_DMAOR, SH4_DMATCR0, SH4_DMATCR1, SH4_DMATCR2, SH4_DMATCR3, SH4_DMATCR4, SH4_DMATCR5, SH4_DMATCR6, SH4_DMATCR7, SH4_EXPEVT, SH4_GPIOIC, SH4_INTEVT, SH4_MCR, SH4_MMUCR, SH4_MMUCR_TI, SH4_PCR, SH4_PCTRA, SH4_PCTRB, SH4_PDTRA, SH4_PDTRB, SH4_PRR_ADDR, SH4_PTEA, SH4_PTEH, SH4_PTEH_ASID_MASK, SH4_PTEL, SH4_PTEL_V, SH4_PVR_ADDR, SH4_QACR0, SH4_QACR1, SH4_REG_BASE, SH4_RFCR, SH4_RTCOR, SH4_RTCSR, SH4_SAR0, SH4_SAR1, SH4_SAR2, SH4_SAR3, SH4_SAR4, SH4_SAR5, SH4_SAR6, SH4_SAR7, SH4_TCNT0, SH4_TCNT1, SH4_TCNT2, SH4_TCOR0, SH4_TCOR1, SH4_TCOR2, SH4_TCR0, SH4_TCR1, SH4_TCR2, SH4_TEA, SH4_TOCR, SH4_TRA, SH4_TSTR, SH4_TTB, SH4_WCR1, SH4_WCR2, SH4_WCR3, SH_N_ITLB_ENTRIES, SH_N_UTLB_ENTRIES, SHREG_SCSPTR, sh4_data::tcnt, sh4_data::tcor, sh4_data::tcr, TCR_CKEG0, TCR_CKEG1, TCR_ICPE0, TCR_ICPE1, TCR_ICPF, TCR_TPSC2, TCR_TPSC_P16, TCR_TPSC_P256, TCR_TPSC_P4, TCR_TPSC_P64, TCR_UNF, sh_cpu::tea, sh4_data::timer_hz, sh4_data::timer_interrupts_pending, sh4_data::timer_irq, sh4_data::tocr, TOCR_TCOE, sh_cpu::tra, sh4_data::tstr, sh_cpu::ttb, and sh_cpu::utlb_lo.

◆ DEVICE_TICK()

DEVICE_TICK ( sh4  )

◆ DEVINIT()

DEVINIT ( sh4  )

◆ sh4_dmac_transfer()

void sh4_dmac_transfer ( struct cpu cpu,
struct sh4_data d,
int  channel 
)

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