sh4_dmacreg.h File Reference

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Macros
sh4_dmacreg.h File Reference

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Macros

#define N_SH4_DMA_CHANNELS   8 /* 4 on 7750, 8 on 7760 */
 
#define SH4_SAR0   0xffa00000 /* Source Address Register */
 
#define SH4_DAR0   0xffa00004 /* Destination Address Register */
 
#define SH4_DMATCR0   0xffa00008 /* Transfer Count Register */
 
#define SH4_CHCR0   0xffa0000c /* Channel Control Register */
 
#define SH4_SAR1   0xffa00010
 
#define SH4_DAR1   0xffa00014
 
#define SH4_DMATCR1   0xffa00018
 
#define SH4_CHCR1   0xffa0001c
 
#define SH4_SAR2   0xffa00020
 
#define SH4_DAR2   0xffa00024
 
#define SH4_DMATCR2   0xffa00028
 
#define SH4_CHCR2   0xffa0002c
 
#define SH4_SAR3   0xffa00030
 
#define SH4_DAR3   0xffa00034
 
#define SH4_DMATCR3   0xffa00038
 
#define SH4_CHCR3   0xffa0003c
 
#define SH4_DMAOR   0xffa00040 /* DMA operation register */
 
#define DMAOR_DDT   0x00008000 /* On-Demand Data Transfer */
 
#define DMAOR_PR1   0x00000200 /* Priority Mode 1 */
 
#define DMAOR_PR0   0x00000100 /* Priority Mode 0 */
 
#define DMAOR_AE   0x00000004 /* Address Error flag */
 
#define DMAOR_NMIF   0x00000002 /* NMI flag */
 
#define DMAOR_DME   0x00000001 /* DMAC master enable */
 
#define SH4_SAR4   0xffa00050
 
#define SH4_DAR4   0xffa00054
 
#define SH4_DMATCR4   0xffa00058
 
#define SH4_CHCR4   0xffa0005c
 
#define SH4_SAR5   0xffa00060
 
#define SH4_DAR5   0xffa00064
 
#define SH4_DMATCR5   0xffa00068
 
#define SH4_CHCR5   0xffa0006c
 
#define SH4_SAR6   0xffa00070
 
#define SH4_DAR6   0xffa00074
 
#define SH4_DMATCR6   0xffa00078
 
#define SH4_CHCR6   0xffa0007c
 
#define SH4_SAR7   0xffa00080
 
#define SH4_DAR7   0xffa00084
 
#define SH4_DMATCR7   0xffa00088
 
#define SH4_CHCR7   0xffa0008c
 
#define CHCR_SSA_MASK   0xe0000000 /* Source Address Space Attribute Specification */
 
#define CHCR_SSA_RESERVED   (0 << 29)
 
#define CHCR_SSA_DYNAMIC_BUS_SIZING   (1 << 29)
 
#define CHCR_SSA_8BIT_IO_SPACE   (2 << 29)
 
#define CHCR_SSA_16BIT_IO_SPACE   (3 << 29)
 
#define CHCR_SSA_8BIT_COMMON_MEMORY_SPACE   (4 << 29)
 
#define CHCR_SSA_16BIT_COMMON_MEMORY_SPACE   (5 << 29)
 
#define CHCR_SSA_8BIT_ATTRIBUTE_MEMORY_SPACE   (6 << 29)
 
#define CHCR_SSA_16BIT_ATTRIBUTE_MEMORY_SPACE   (7 << 29)
 
#define CHCR_STC   0x10000000 /* Source Address Wait Control Select */
 
#define CHCR_DSA_MASK   0x0e000000 /* Destination Address Space Attribute Specification */
 
#define CHCR_DSA_RESERVED   (0 << 25)
 
#define CHCR_DSA_DYNAMIC_BUS_SIZING   (1 << 25)
 
#define CHCR_DSA_8BIT_IO_SPACE   (2 << 25)
 
#define CHCR_DSA_16BIT_IO_SPACE   (3 << 25)
 
#define CHCR_DSA_8BIT_COMMON_MEMORY_SPACE   (4 << 25)
 
#define CHCR_DSA_16BIT_COMMON_MEMORY_SPACE   (5 << 25)
 
#define CHCR_DSA_8BIT_ATTRIBUTE_MEMORY_SPACE   (6 << 25)
 
#define CHCR_DSA_16BIT_ATTRIBUTE_MEMORY_SPACE   (7 << 25)
 
#define CHCR_DTC   0x01000000 /* Destination Address Wait Control Select */
 
#define CHCR_DS   0x00080000 /* DREQ Select */
 
#define CHCR_RL   0x00040000 /* Request Check Level */
 
#define CHCR_AM   0x00020000 /* Acknowledge Mode */
 
#define CHCR_AL   0x00010000 /* Acknowledge Level */
 
#define CHCR_DM   0x0000c000 /* Destination Address Mode 1 and 0 */
 
#define CHCR_DM_FIXED   (0 << 14) /* Destination Address Fixed */
 
#define CHCR_DM_INCREMENTED   (1 << 14) /* Destination Address Incremented */
 
#define CHCR_DM_DECREMENTED   (2 << 14) /* Destination Address Decremented */
 
#define CHCR_SM   0x00003000 /* Source Address Mode 1 and 0 */
 
#define CHCR_SM_FIXED   (0 << 12) /* Source Address Fixed */
 
#define CHCR_SM_INCREMENTED   (1 << 12) /* Source Address Incremented */
 
#define CHCR_SM_DECREMENTED   (2 << 12) /* Source Address Decremented */
 
#define CHCR_RS   0x00000f00 /* Resource Select */
 
#define CHCR_TM   0x00000080 /* Transmit Mode (0=cycle steal, 1=burst) */
 
#define CHCR_TS   0x00000070 /* Transmit Size */
 
#define CHCR_TS_8BYTE   (0 << 4)
 
#define CHCR_TS_1BYTE   (1 << 4)
 
#define CHCR_TS_2BYTE   (2 << 4)
 
#define CHCR_TS_4BYTE   (3 << 4)
 
#define CHCR_TS_32BYTE   (4 << 4)
 
#define CHCR_CHSET   0x00000008 /* Channel Setting */
 
#define CHCR_IE   0x00000004 /* Interrupt Enable */
 
#define CHCR_TE   0x00000002 /* Transfer End */
 
#define CHCR_TD   0x00000001 /* DMAC Enable */
 

Macro Definition Documentation

◆ CHCR_AL

#define CHCR_AL   0x00010000 /* Acknowledge Level */

Definition at line 116 of file sh4_dmacreg.h.

◆ CHCR_AM

#define CHCR_AM   0x00020000 /* Acknowledge Mode */

Definition at line 115 of file sh4_dmacreg.h.

◆ CHCR_CHSET

#define CHCR_CHSET   0x00000008 /* Channel Setting */

Definition at line 133 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ CHCR_DM

#define CHCR_DM   0x0000c000 /* Destination Address Mode 1 and 0 */

Definition at line 117 of file sh4_dmacreg.h.

Referenced by pvr_dma_transfer(), and sh4_dmac_transfer().

◆ CHCR_DM_DECREMENTED

#define CHCR_DM_DECREMENTED   (2 << 14) /* Destination Address Decremented */

Definition at line 120 of file sh4_dmacreg.h.

Referenced by pvr_dma_transfer(), and sh4_dmac_transfer().

◆ CHCR_DM_FIXED

#define CHCR_DM_FIXED   (0 << 14) /* Destination Address Fixed */

Definition at line 118 of file sh4_dmacreg.h.

Referenced by pvr_dma_transfer(), and sh4_dmac_transfer().

◆ CHCR_DM_INCREMENTED

#define CHCR_DM_INCREMENTED   (1 << 14) /* Destination Address Incremented */

Definition at line 119 of file sh4_dmacreg.h.

Referenced by pvr_dma_transfer(), and sh4_dmac_transfer().

◆ CHCR_DS

#define CHCR_DS   0x00080000 /* DREQ Select */

Definition at line 113 of file sh4_dmacreg.h.

◆ CHCR_DSA_16BIT_ATTRIBUTE_MEMORY_SPACE

#define CHCR_DSA_16BIT_ATTRIBUTE_MEMORY_SPACE   (7 << 25)

Definition at line 111 of file sh4_dmacreg.h.

◆ CHCR_DSA_16BIT_COMMON_MEMORY_SPACE

#define CHCR_DSA_16BIT_COMMON_MEMORY_SPACE   (5 << 25)

Definition at line 109 of file sh4_dmacreg.h.

◆ CHCR_DSA_16BIT_IO_SPACE

#define CHCR_DSA_16BIT_IO_SPACE   (3 << 25)

Definition at line 107 of file sh4_dmacreg.h.

◆ CHCR_DSA_8BIT_ATTRIBUTE_MEMORY_SPACE

#define CHCR_DSA_8BIT_ATTRIBUTE_MEMORY_SPACE   (6 << 25)

Definition at line 110 of file sh4_dmacreg.h.

◆ CHCR_DSA_8BIT_COMMON_MEMORY_SPACE

#define CHCR_DSA_8BIT_COMMON_MEMORY_SPACE   (4 << 25)

Definition at line 108 of file sh4_dmacreg.h.

◆ CHCR_DSA_8BIT_IO_SPACE

#define CHCR_DSA_8BIT_IO_SPACE   (2 << 25)

Definition at line 106 of file sh4_dmacreg.h.

◆ CHCR_DSA_DYNAMIC_BUS_SIZING

#define CHCR_DSA_DYNAMIC_BUS_SIZING   (1 << 25)

Definition at line 105 of file sh4_dmacreg.h.

◆ CHCR_DSA_MASK

#define CHCR_DSA_MASK   0x0e000000 /* Destination Address Space Attribute Specification */

Definition at line 103 of file sh4_dmacreg.h.

◆ CHCR_DSA_RESERVED

#define CHCR_DSA_RESERVED   (0 << 25)

Definition at line 104 of file sh4_dmacreg.h.

◆ CHCR_DTC

#define CHCR_DTC   0x01000000 /* Destination Address Wait Control Select */

Definition at line 112 of file sh4_dmacreg.h.

◆ CHCR_IE

#define CHCR_IE   0x00000004 /* Interrupt Enable */

Definition at line 134 of file sh4_dmacreg.h.

Referenced by pvr_dma_transfer(), and sh4_dmac_transfer().

◆ CHCR_RL

#define CHCR_RL   0x00040000 /* Request Check Level */

Definition at line 114 of file sh4_dmacreg.h.

◆ CHCR_RS

#define CHCR_RS   0x00000f00 /* Resource Select */

Definition at line 125 of file sh4_dmacreg.h.

Referenced by pvr_dma_transfer(), and sh4_dmac_transfer().

◆ CHCR_SM

#define CHCR_SM   0x00003000 /* Source Address Mode 1 and 0 */

Definition at line 121 of file sh4_dmacreg.h.

Referenced by pvr_dma_transfer(), and sh4_dmac_transfer().

◆ CHCR_SM_DECREMENTED

#define CHCR_SM_DECREMENTED   (2 << 12) /* Source Address Decremented */

Definition at line 124 of file sh4_dmacreg.h.

Referenced by pvr_dma_transfer(), and sh4_dmac_transfer().

◆ CHCR_SM_FIXED

#define CHCR_SM_FIXED   (0 << 12) /* Source Address Fixed */

Definition at line 122 of file sh4_dmacreg.h.

Referenced by pvr_dma_transfer(), and sh4_dmac_transfer().

◆ CHCR_SM_INCREMENTED

#define CHCR_SM_INCREMENTED   (1 << 12) /* Source Address Incremented */

Definition at line 123 of file sh4_dmacreg.h.

Referenced by pvr_dma_transfer(), and sh4_dmac_transfer().

◆ CHCR_SSA_16BIT_ATTRIBUTE_MEMORY_SPACE

#define CHCR_SSA_16BIT_ATTRIBUTE_MEMORY_SPACE   (7 << 29)

Definition at line 101 of file sh4_dmacreg.h.

◆ CHCR_SSA_16BIT_COMMON_MEMORY_SPACE

#define CHCR_SSA_16BIT_COMMON_MEMORY_SPACE   (5 << 29)

Definition at line 99 of file sh4_dmacreg.h.

◆ CHCR_SSA_16BIT_IO_SPACE

#define CHCR_SSA_16BIT_IO_SPACE   (3 << 29)

Definition at line 97 of file sh4_dmacreg.h.

◆ CHCR_SSA_8BIT_ATTRIBUTE_MEMORY_SPACE

#define CHCR_SSA_8BIT_ATTRIBUTE_MEMORY_SPACE   (6 << 29)

Definition at line 100 of file sh4_dmacreg.h.

◆ CHCR_SSA_8BIT_COMMON_MEMORY_SPACE

#define CHCR_SSA_8BIT_COMMON_MEMORY_SPACE   (4 << 29)

Definition at line 98 of file sh4_dmacreg.h.

◆ CHCR_SSA_8BIT_IO_SPACE

#define CHCR_SSA_8BIT_IO_SPACE   (2 << 29)

Definition at line 96 of file sh4_dmacreg.h.

◆ CHCR_SSA_DYNAMIC_BUS_SIZING

#define CHCR_SSA_DYNAMIC_BUS_SIZING   (1 << 29)

Definition at line 95 of file sh4_dmacreg.h.

◆ CHCR_SSA_MASK

#define CHCR_SSA_MASK   0xe0000000 /* Source Address Space Attribute Specification */

Definition at line 92 of file sh4_dmacreg.h.

◆ CHCR_SSA_RESERVED

#define CHCR_SSA_RESERVED   (0 << 29)

Definition at line 94 of file sh4_dmacreg.h.

◆ CHCR_STC

#define CHCR_STC   0x10000000 /* Source Address Wait Control Select */

Definition at line 102 of file sh4_dmacreg.h.

◆ CHCR_TD

#define CHCR_TD   0x00000001 /* DMAC Enable */

Definition at line 136 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS(), pvr_dma_transfer(), and sh4_dmac_transfer().

◆ CHCR_TE

#define CHCR_TE   0x00000002 /* Transfer End */

Definition at line 135 of file sh4_dmacreg.h.

Referenced by pvr_dma_transfer(), and sh4_dmac_transfer().

◆ CHCR_TM

#define CHCR_TM   0x00000080 /* Transmit Mode (0=cycle steal, 1=burst) */

Definition at line 126 of file sh4_dmacreg.h.

◆ CHCR_TS

#define CHCR_TS   0x00000070 /* Transmit Size */

Definition at line 127 of file sh4_dmacreg.h.

Referenced by pvr_dma_transfer(), and sh4_dmac_transfer().

◆ CHCR_TS_1BYTE

#define CHCR_TS_1BYTE   (1 << 4)

Definition at line 129 of file sh4_dmacreg.h.

Referenced by pvr_dma_transfer(), and sh4_dmac_transfer().

◆ CHCR_TS_2BYTE

#define CHCR_TS_2BYTE   (2 << 4)

Definition at line 130 of file sh4_dmacreg.h.

Referenced by pvr_dma_transfer(), and sh4_dmac_transfer().

◆ CHCR_TS_32BYTE

#define CHCR_TS_32BYTE   (4 << 4)

Definition at line 132 of file sh4_dmacreg.h.

Referenced by pvr_dma_transfer(), and sh4_dmac_transfer().

◆ CHCR_TS_4BYTE

#define CHCR_TS_4BYTE   (3 << 4)

Definition at line 131 of file sh4_dmacreg.h.

Referenced by pvr_dma_transfer(), and sh4_dmac_transfer().

◆ CHCR_TS_8BYTE

#define CHCR_TS_8BYTE   (0 << 4)

Definition at line 128 of file sh4_dmacreg.h.

Referenced by pvr_dma_transfer(), and sh4_dmac_transfer().

◆ DMAOR_AE

#define DMAOR_AE   0x00000004 /* Address Error flag */

Definition at line 61 of file sh4_dmacreg.h.

◆ DMAOR_DDT

#define DMAOR_DDT   0x00008000 /* On-Demand Data Transfer */

Definition at line 58 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ DMAOR_DME

#define DMAOR_DME   0x00000001 /* DMAC master enable */

Definition at line 63 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ DMAOR_NMIF

#define DMAOR_NMIF   0x00000002 /* NMI flag */

Definition at line 62 of file sh4_dmacreg.h.

◆ DMAOR_PR0

#define DMAOR_PR0   0x00000100 /* Priority Mode 0 */

Definition at line 60 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ DMAOR_PR1

#define DMAOR_PR1   0x00000200 /* Priority Mode 1 */

Definition at line 59 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ N_SH4_DMA_CHANNELS

#define N_SH4_DMA_CHANNELS   8 /* 4 on 7750, 8 on 7760 */

Definition at line 35 of file sh4_dmacreg.h.

◆ SH4_CHCR0

#define SH4_CHCR0   0xffa0000c /* Channel Control Register */

Definition at line 40 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ SH4_CHCR1

#define SH4_CHCR1   0xffa0001c

Definition at line 45 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ SH4_CHCR2

#define SH4_CHCR2   0xffa0002c

Definition at line 50 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ SH4_CHCR3

#define SH4_CHCR3   0xffa0003c

Definition at line 55 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ SH4_CHCR4

#define SH4_CHCR4   0xffa0005c

Definition at line 70 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ SH4_CHCR5

#define SH4_CHCR5   0xffa0006c

Definition at line 75 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ SH4_CHCR6

#define SH4_CHCR6   0xffa0007c

Definition at line 80 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ SH4_CHCR7

#define SH4_CHCR7   0xffa0008c

Definition at line 85 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ SH4_DAR0

#define SH4_DAR0   0xffa00004 /* Destination Address Register */

Definition at line 38 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ SH4_DAR1

#define SH4_DAR1   0xffa00014

Definition at line 43 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ SH4_DAR2

#define SH4_DAR2   0xffa00024

Definition at line 48 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ SH4_DAR3

#define SH4_DAR3   0xffa00034

Definition at line 53 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ SH4_DAR4

#define SH4_DAR4   0xffa00054

Definition at line 68 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ SH4_DAR5

#define SH4_DAR5   0xffa00064

Definition at line 73 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ SH4_DAR6

#define SH4_DAR6   0xffa00074

Definition at line 78 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ SH4_DAR7

#define SH4_DAR7   0xffa00084

Definition at line 83 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ SH4_DMAOR

#define SH4_DMAOR   0xffa00040 /* DMA operation register */

Definition at line 57 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ SH4_DMATCR0

#define SH4_DMATCR0   0xffa00008 /* Transfer Count Register */

Definition at line 39 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ SH4_DMATCR1

#define SH4_DMATCR1   0xffa00018

Definition at line 44 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ SH4_DMATCR2

#define SH4_DMATCR2   0xffa00028

Definition at line 49 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ SH4_DMATCR3

#define SH4_DMATCR3   0xffa00038

Definition at line 54 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ SH4_DMATCR4

#define SH4_DMATCR4   0xffa00058

Definition at line 69 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ SH4_DMATCR5

#define SH4_DMATCR5   0xffa00068

Definition at line 74 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ SH4_DMATCR6

#define SH4_DMATCR6   0xffa00078

Definition at line 79 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ SH4_DMATCR7

#define SH4_DMATCR7   0xffa00088

Definition at line 84 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ SH4_SAR0

#define SH4_SAR0   0xffa00000 /* Source Address Register */

Definition at line 37 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ SH4_SAR1

#define SH4_SAR1   0xffa00010

Definition at line 42 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ SH4_SAR2

#define SH4_SAR2   0xffa00020

Definition at line 47 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ SH4_SAR3

#define SH4_SAR3   0xffa00030

Definition at line 52 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ SH4_SAR4

#define SH4_SAR4   0xffa00050

Definition at line 67 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ SH4_SAR5

#define SH4_SAR5   0xffa00060

Definition at line 72 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ SH4_SAR6

#define SH4_SAR6   0xffa00070

Definition at line 77 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS().

◆ SH4_SAR7

#define SH4_SAR7   0xffa00080

Definition at line 82 of file sh4_dmacreg.h.

Referenced by DEVICE_ACCESS().


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