68 #define CRIME_TICKSHIFT 14 75 #define DEV_CRIME_LENGTH 0x280 103 printf(
"CRIME SOFTINT=0x%08x HARDINT=0x%08x => 0x%08x, INTMASK=0x%08x\n",
110 int asserted = !!status;
144 gettimeofday(&tv, NULL);
146 uint64_t microseconds = tv.tv_sec * 1000000 + tv.tv_usec;
153 fatal(
"[ crime_update_crime_time: host system time went backwards? ]\n");
159 int64_t to_add = delta * 66;
206 uint64_t idata = 0, odata = 0;
207 uint64_t preserved_CRIME_HARDINT = d->
reg[
CRIME_HARDINT /
sizeof(uint64_t)];
244 fatal(
"[ sgi_crime: SGI O2 can not have more than 1024 MB RAM ]\n");
255 fatal(
"[ sgi_crime: for up to 256 MB RAM, RAM size needs to be divisible " 256 "by 32 MB. for larger RAM sizes (up to 1024 MB), it needs to be " 257 "divisible by 128 MB. ]\n");
261 int flag_for_128MB = mb_per_bank == 128 ? 0x100 : 0x000;
263 for (
int bank = 0; bank < 8; ++bank) {
264 int b = mb_per_bank == 128 ? (bank << 2) : bank;
270 total_mb += mb_per_bank;
275 d->
reg[relative_addr / 8] = idata;
277 odata = d->
reg[relative_addr / 8];
278 }
else if (len == 4) {
280 if (relative_addr & 4) {
281 d->
reg[relative_addr / 8] &= ~0xffffffffULL;
282 d->
reg[relative_addr / 8] |= (uint32_t)idata;
284 d->
reg[relative_addr / 8] &= 0xffffffffULL;
285 d->
reg[relative_addr / 8] |= (uint64_t)(idata << 32ULL);
288 odata = d->
reg[relative_addr / 8];
289 if (relative_addr & 4)
290 odata = (int32_t)odata;
292 odata = (int32_t)(odata >> 32);
295 fatal(
"crime access len = %i!\n", len);
299 switch (relative_addr) {
321 if (((uint32_t)
cpu->
pc & 0xffffff00) == (uint32_t)0xbfc05100) {
339 idata &= ~CRIME_CONTROL_DOG_ENABLE;
349 exit_without_entering_debugger = 1;
350 idata &= ~CRIME_CONTROL_HARD_RESET;
356 fatal(
"[ CRIME_CONTROL: unimplemented " 357 "control 0x%016llx ]\n", (
long long)idata);
376 debug(
"[ crime: read from 0x%x, len=%i:",
377 (
int)relative_addr, len);
378 for (i=0; i<len; i++)
382 debug(
"[ crime: write to 0x%x:", (
int)relative_addr);
383 for (i=0; i<len; i++)
385 debug(
" (len=%i) ]\n", len);
405 uint64_t baseaddr,
char *irq_path,
int use_fb)
419 for (i=0; i<32; i++) {
422 snprintf(name,
sizeof(name),
"%s.crime.0x%x", irq_path, 1 << i);
423 memset(&templ, 0,
sizeof(templ));
435 snprintf(tmpstr,
sizeof(tmpstr),
"mace addr=0x1f310000 irq=%s.crime",
447 #define DEV_MACE_LENGTH 0x100 464 int assert_periph = s4 | s5 ? 1 : 0;
465 int assert_misc = s6 | s7 ? 1 : 0;
506 uint32_t line = 1 << interrupt->
line;
518 uint32_t line = 1 << interrupt->
line;
546 uint8_t old_mace_isa_flash_nic_reg =
550 memcpy(&d->
reg[relative_addr],
data, len);
552 memcpy(
data, &d->
reg[relative_addr], len);
554 switch (relative_addr & ~7) {
581 ^ old_mace_isa_flash_nic_reg) &
585 case 0:
debug(
"[ mace: turning LED WHITE/ORANGE ]\n");
588 debug(
"[ mace: turning LED GREEN ]\n");
591 debug(
"[ mace: turning LED RED ]\n");
593 default:
fatal(
"[ mace: turning LED OFF ]\n");
611 fatal(
"[ NOTE/TODO: WRITE to mace intr: " 612 "reladdr=0x%x data=", (
int)relative_addr);
613 for (i=0; i<len; i++)
615 fatal(
" (len=%i) ]\n", len);
624 debug(
"[ mace: read from 0x%x:", (
int)relative_addr);
625 for (i=0; i<len; i++)
627 debug(
" (len=%i) ]\n", len);
629 debug(
"[ mace: write to 0x%x:", (
int)relative_addr);
630 for (i=0; i<len; i++)
632 debug(
" (len=%i) ]\n", len);
649 snprintf(tmpstr,
sizeof(tmpstr),
"%s.0x%x",
653 snprintf(tmpstr,
sizeof(tmpstr),
"%s.0x%x",
661 for (i=0; i<32; i++) {
664 snprintf(name,
sizeof(name),
"%s.0x%x.mace.%i",
666 memset(&templ, 0,
sizeof(templ));
674 snprintf(name,
sizeof(name),
"%s.0x%x.mace.%i",
676 memset(&templ, 0,
sizeof(templ));
700 uint64_t idata = 0, odata=0;
701 int res = 1, bus, dev, func, pcireg;
704 fatal(
"[ macepci: unimplemented len %i ]\n", len);
709 fatal(
"[ macepci: write to address 0x%x, data=0x%02x (len %i) ]\n",
710 (
int)relative_addr, (
int)idata, len);
715 switch (relative_addr) {
756 &odata : &idata, len, writeflag);
761 fatal(
"[ macepci: unimplemented write to address " 762 "0x%x, data=0x%02x ]\n",
763 (
int)relative_addr, (
int)idata);
765 fatal(
"[ macepci: unimplemented read from address " 766 "0x%x ]\n", (
int)relative_addr);
777 fatal(
"[ macepci: read from address 0x%x, data=0x%02x (len %i) ]\n",
778 (
int)relative_addr, (
int)odata, len);
790 struct memory *mem, uint64_t baseaddr,
char *irq_path)
805 "TODO: pci irq path",
828 uint64_t idata = 0, odata = 0;
832 regnr = relative_addr /
sizeof(uint64_t);
836 d->
reg[regnr] = idata;
838 odata = d->
reg[regnr];
840 switch (relative_addr) {
842 d->
reg[regnr] += 0x2710;
846 debug(
"[ sgi_ust: unimplemented write to " 847 "address 0x%llx, data=0x%016llx ]\n",
848 (
long long)relative_addr, (
long long)idata);
850 debug(
"[ sgi_ust: unimplemented read from address" 851 " 0x%llx ]\n", (
long long)relative_addr);
uint64_t memory_readmax64(struct cpu *cpu, unsigned char *buf, int len)
void fatal(const char *fmt,...)
void(* interrupt_assert)(struct interrupt *)
unsigned char reg[DEV_MACE_LENGTH]
#define CRIME_CONTROL_HARD_RESET
#define MACE_ISA_FLASH_NIC_REG
#define MACE_ISA_INT_STATUS
void mace_interrupt_reassert(struct mace_data *d)
#define MACE_ISA_LED_GREEN
uint64_t last_microseconds
void dev_sgi_ust_init(struct memory *mem, uint64_t baseaddr)
void interrupt_handler_register(struct interrupt *templ)
void(* interrupt_deassert)(struct interrupt *)
void crime_interrupt_reassert(struct crime_data *d)
void crime_interrupt_deassert(struct interrupt *interrupt)
struct pci_data * dev_macepci_init(struct machine *machine, struct memory *mem, uint64_t baseaddr, char *irq_path)
#define DEV_SGI_UST_LENGTH
#define CRIME_MEM_BANK_CTRL0
#define MACE_ISA_PWD_CLEAR
void crime_update_crime_time(struct crime_data *d)
#define CRIME_CONTROL_ENDIANESS
void * device_add(struct machine *machine, const char *name_and_params)
void mips_pc_to_pointers(struct cpu *)
#define CRIME_CONTROL_DOG_ENABLE
uint64_t reg[DEV_CRIME_LENGTH/sizeof(uint64_t)]
struct pci_data * pci_data
#define CHECK_ALLOCATION(ptr)
void mace_interrupt_assert(struct interrupt *interrupt)
void crime_interrupt_assert(struct interrupt *interrupt)
void bus_pci_setaddr(struct cpu *cpu, struct pci_data *pci_data, int bus, int device, int function, int reg)
#define INTERRUPT_ASSERT(istruct)
#define DEV_MACEPCI_LENGTH
struct interrupt irq_periph
uint64_t reg[DEV_SGI_UST_LENGTH/sizeof(uint64_t)]
int dev_sgi_ust_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *)
#define INTERRUPT_CONNECT(name, istruct)
#define MACE_ISA_INT_MASK
void memory_writemax64(struct cpu *cpu, unsigned char *buf, int len, uint64_t data)
void mips32_pc_to_pointers(struct cpu *)
void dev_crime_init(struct machine *machine, struct memory *mem, uint64_t baseaddr, char *irq_path, int use_fb)
#define CRIME_INT_PERIPH_SERIAL
int dev_macepci_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *)
void memory_device_register(struct memory *mem, const char *, uint64_t baseaddr, uint64_t len, int(*f)(struct cpu *, struct memory *, uint64_t, unsigned char *, size_t, int, void *), void *extra, int flags, unsigned char *dyntrans_data)
void bus_pci_decompose_1(uint32_t t, int *bus, int *dev, int *func, int *reg)
#define MACE_ISA_RINGBASE
uint64_t gpr[N_MIPS_GPRS]
struct pci_data * bus_pci_init(struct machine *machine, const char *irq_path, uint64_t pci_actual_io_offset, uint64_t pci_actual_mem_offset, uint64_t pci_portbase, uint64_t pci_membase, const char *pci_irqbase, uint64_t isa_portbase, uint64_t isa_membase, const char *isa_irqbase)
void machine_add_tickfunction(struct machine *machine, void(*func)(struct cpu *, void *), void *extra, int clockshift)
struct interrupt irq_misc
void bus_pci_data_access(struct cpu *cpu, struct pci_data *pci_data, uint64_t *data, int len, int writeflag)
void mace_interrupt_deassert(struct interrupt *interrupt)
#define INTERRUPT_DEASSERT(istruct)
#define CRIME_INT_PERIPH_MISC